[PATCH 0/7] Fixes and improvements for SDHCI on Armada 38x

[PATCH 0/7] Fixes and improvements for SDHCI on Armada 38x

[Gregory CLEMENT]

Hi,

this series brings fixes and improvements for the SDHCI controller of
the Armada 38x SoCs.

The first two patches are fixes and should be also applied on the
stable branch (I added stable in copy for this).

The first one removes the SDR50 and DDR50 mode timing from the
capabilities of the controller because the current implementation
doesn't support it.

The second one fix controller's caps according to the limitation of
the hardware.

The third one extends the Device Tree binding of the Armada 38x. It
allows using the SDIO3 configuration register.

The forth patch adds the support of this new register in the
driver. Thanks to this one, specific clock adjustments can be done in
order to support the SDR50 and DDR50 modes timing.

The fifth patch is device tree clean-up.

The sixth patch update the SDHCI node on Armada 38x in order to use
the new register and then to be able to support the SDR50 and DDR50
modes timing.

Finally, the seventh patch add the description of SDHCI for the Armada
388 RD board which was missing.

Patches 1 to 4 should be merged through the mmc tree and patches 5 to
7 should be merged through mvebu and then arm-soc.

Patch 4 depend on patch 2.
Patch 2 depend on patch 1.
And patch 1 depend on commit aa8165f91442 "mmc: sdhci-pxav3: do the
mbus window configuration after enabling clocks" which have been
merged.

But as all this patch should be merged through the same tree it would
not be a problem

The patches 5 to 7 depend on the patches already merged in mvebu.

As they are fixes, patches 1 and 2 should be merged in 3.18-rc or at
least in 3.19 and then they will be part of 3.18.1. For the other
patches it would be nice if they could be part of 3.19.

Thanks,

Gregory

Gregory CLEMENT (7):
  mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x
    flavor
  mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to
    erratum ERR-7878951
  mmc: sdhci-pxav3: Extend binding with SDIO3 conf reg for the Armada
    38x
  mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes
  ARM: mvebu: Use macros for interrupt flags on Armada 38x sdhci node
  ARM: mvebu: Update the SDHCI node on Armada 38x
  ARM: mvebu: Add Device Tree description of SDHCI for Armada 388 RD

 .../devicetree/bindings/mmc/sdhci-pxa.txt          | 15 ++--
 arch/arm/boot/dts/armada-388-rd.dts                | 10 +++
 arch/arm/boot/dts/armada-38x.dtsi                  |  7 +-
 drivers/mmc/host/sdhci-pxav3.c                     | 79 ++++++++++++++++++++++
 4 files changed, 105 insertions(+), 6 deletions(-)

-- 
1.9.1

[PATCH 1/7] mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor

[Gregory CLEMENT]

According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not available. In this case we use the
SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities.

Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc: <stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> # v3.15+
Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 drivers/mmc/host/sdhci-pxav3.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index ca3424e7ef71..7b07325b4fba 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -118,6 +118,20 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
 	return 0;
 }
 
+static int armada_38x_quirks(struct sdhci_host *host)
+{
+	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
+	/*
+	 * According to erratum 'FE-2946959' both SDR50 and DDR50
+	 * modes require specific clock adjustments in SDIO3
+	 * Configuration register, if the adjustment is not done,
+	 * remove them from the capabilities.
+	 */
+	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+	return 0;
+}
+
 static void pxav3_reset(struct sdhci_host *host, u8 mask)
 {
 	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
@@ -319,6 +333,9 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		clk_prepare_enable(pxa->clk_core);
 
 	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
+		ret = armada_38x_quirks(host);
+		if (ret < 0)
+			goto err_quirks;
 		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
 		if (ret < 0)
 			goto err_mbus_win;
@@ -400,6 +417,7 @@ err_mbus_win:
 	if (!IS_ERR(pxa->clk_core))
 		clk_disable_unprepare(pxa->clk_core);
 err_clk_get:
+err_quirks:
 	sdhci_pltfm_free(pdev);
 	return ret;
 }
-- 
1.9.1

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[PATCH 2/7] mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to erratum ERR-7878951

[Gregory CLEMENT]

According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
different capabilities than the ones shown in its registers:

- it doesn't support the voltage switching: it can work either with
  3.3V or 1.8V supply
- it doesn't support the SDR104 mode
- SDR50 mode doesn't need tuning

The SDHCI_QUIRK_MISSING_CAPS quirk is used for updating the
capabilities accordingly.

Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc: <stable@vger.kernel.org> # v3.15+

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 7b07325b4fba..4daa47a53a62 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -118,8 +118,11 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
 	return 0;
 }
 
-static int armada_38x_quirks(struct sdhci_host *host)
+static int armada_38x_quirks(struct platform_device *pdev,
+			     struct sdhci_host *host)
 {
+	struct device_node *np = pdev->dev.of_node;
+
 	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 	/*
 	 * According to erratum 'FE-2946959' both SDR50 and DDR50
@@ -129,6 +132,20 @@ static int armada_38x_quirks(struct sdhci_host *host)
 	 */
 	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+
+	/*
+	 * According to erratum 'ERR-7878951' Armada 38x SDHCI
+	 * controller has different capabilities than the ones shown
+	 * in its registers
+	 */
+	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+	if (of_get_property(np, "no-1-8-v", NULL)) {
+		host->caps &= ~SDHCI_CAN_VDD_180;
+		host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
+	} else
+		host->caps &= ~SDHCI_CAN_VDD_330;
+	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
+
 	return 0;
 }
 
@@ -333,7 +350,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		clk_prepare_enable(pxa->clk_core);
 
 	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
-		ret = armada_38x_quirks(host);
+		ret = armada_38x_quirks(pdev, host);
 		if (ret < 0)
 			goto err_quirks;
 		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
-- 
1.9.1

[PATCH 3/7] mmc: sdhci-pxav3: Extend binding with SDIO3 conf reg for the Armada 38x

[Gregory CLEMENT]

The SDHCI unit used on the Armada 38x needs using an extra register to
do specific clock adjustments in order to support the SDR50 and DDR50
modes. This patch extends the binding to allow using this register.

Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 Documentation/devicetree/bindings/mmc/sdhci-pxa.txt | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
index 4dd6deb90719..3d1b449d6097 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
@@ -9,9 +9,13 @@ Required properties:
 - reg:
   * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
     the SDHCI registers.
-  * for "marvell,armada-380-sdhci", two register areas. The first one
-    for the SDHCI registers themselves, and the second one for the
-    AXI/Mbus bridge registers of the SDHCI unit.
+
+  * for "marvell,armada-380-sdhci", three register areas. The first
+    one for the SDHCI registers themselves, the second one for the
+    AXI/Mbus bridge registers of the SDHCI unit, the third one for the
+    SDIO3 Configuration register
+- reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory
+  for "marvell,armada-380-sdhci"
 - clocks: Array of clocks required for SDHCI; requires at least one for
     I/O clock.
 - clock-names: Array of names corresponding to clocks property; shall be
@@ -35,7 +39,10 @@ sdhci@d4280800 {
 
 sdhci@d8000 {
 	compatible = "marvell,armada-380-sdhci";
-	reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+	reg-names = "sdhci", "mbus", "conf-sdio3";
+	reg = <0xd8000 0x1000>,
+		<0xdc000 0x100>;
+		<0x18454 0x4>;
 	interrupts = <0 25 0x4>;
 	clocks = <&gateclk 17>;
 	clock-names = "io";
-- 
1.9.1

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[PATCH 4/7] mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes

[Gregory CLEMENT]

According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register.

This commit add the support of this register and for SDR50 or DDR50
mode use it as suggested by the erratum:
- Set the SDIO3 Clock Inv field in SDIO3 Configuration register to not
inverted.
- Set the Sample FeedBack Clock field to 0x1

Signed-off-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 drivers/mmc/host/sdhci-pxav3.c | 60 ++++++++++++++++++++++++++++++++++++------
 1 file changed, 52 insertions(+), 8 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 4daa47a53a62..505326052333 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -62,6 +62,7 @@ struct sdhci_pxa {
 	struct clk *clk_core;
 	struct clk *clk_io;
 	u8	power_mode;
+	void __iomem *sdio3_conf_reg;
 };
 
 /*
@@ -72,6 +73,14 @@ struct sdhci_pxa {
 #define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
 #define SDHCI_MAX_WIN_NUM	8
 
+/*
+ * Fields below belong to SDIO3 Configuration Register (third register
+ * region for the Armada 38x flavor)
+ */
+
+#define SDIO3_CONF_CLK_INV	BIT(0)
+#define SDIO3_CONF_SD_FB_CLK	BIT(2)
+
 static int mv_conf_mbus_windows(struct platform_device *pdev,
 				const struct mbus_dram_target_info *dram)
 {
@@ -122,16 +131,31 @@ static int armada_38x_quirks(struct platform_device *pdev,
 			     struct sdhci_host *host)
 {
 	struct device_node *np = pdev->dev.of_node;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_pxa *pxa = pltfm_host->priv;
+	struct resource *res;
 
 	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
-	/*
-	 * According to erratum 'FE-2946959' both SDR50 and DDR50
-	 * modes require specific clock adjustments in SDIO3
-	 * Configuration register, if the adjustment is not done,
-	 * remove them from the capabilities.
-	 */
-	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
-	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "conf-sdio3");
+	if (res) {
+		pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(pxa->sdio3_conf_reg))
+			return PTR_ERR(pxa->sdio3_conf_reg);
+	} else {
+		/*
+		 * According to erratum 'FE-2946959' both SDR50 and DDR50
+		 * modes require specific clock adjustments in SDIO3
+		 * Configuration register, if the adjustment is not done,
+		 * remove them from the capabilities.
+		 */
+		host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+		host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
+
+		dev_warn(&pdev->dev, "conf-sdio3 register not found\n");
+		dev_warn(&pdev->dev, "disabling SDR50 and DDR50 modes\n");
+		dev_warn(&pdev->dev, "consider updating your dtb\n");
+	}
 
 	/*
 	 * According to erratum 'ERR-7878951' Armada 38x SDHCI
@@ -225,6 +249,8 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 
 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 {
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_pxa *pxa = pltfm_host->priv;
 	u16 ctrl_2;
 
 	/*
@@ -254,6 +280,24 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 		break;
 	}
 
+	/*
+	 * Update SDIO3 Configuration register according to erratum
+	 * FE-2946959
+	 */
+	if (pxa->sdio3_conf_reg) {
+		u8 reg_val  = readb(pxa->sdio3_conf_reg);
+
+		if (uhs == MMC_TIMING_UHS_SDR50 ||
+		    uhs == MMC_TIMING_UHS_DDR50) {
+			reg_val &= ~SDIO3_CONF_CLK_INV;
+			reg_val |= SDIO3_CONF_SD_FB_CLK;
+		} else {
+			reg_val |= SDIO3_CONF_CLK_INV;
+			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
+		}
+		writeb(reg_val, pxa->sdio3_conf_reg);
+	}
+
 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 	dev_dbg(mmc_dev(host->mmc),
 		"%s uhs = %d, ctrl_2 = %04X\n",
-- 
1.9.1

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[PATCH 5/7] ARM: mvebu: Use macros for interrupt flags on Armada 38x sdhci node

[Gregory CLEMENT]

Instead of hardcoding the values of the interrupt flags, use the
macros provided by <include/dt-bindings/interrupt-controller/irq.h>
and <include/dt-bindings/interrupt-controller/arm-gic.h> for the
Armada 38x SDHCI node.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 79c4acf186e2..71d4eca5b497 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -516,7 +516,7 @@
 			sdhci@d8000 {
 				compatible = "marvell,armada-380-sdhci";
 				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
-				interrupts = <0 25 0x4>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&gateclk 17>;
 				mrvl,clk-delay-cycles = <0x1F>;
 				status = "disabled";
-- 
1.9.1

[PATCH 6/7] ARM: mvebu: Update the SDHCI node on Armada 38x

[Gregory CLEMENT]

The binding of the armada-380-sdhci has been extended with a new
register in order to be able to use the SDR50 and DDR50 mode. This
commit add the resource associated to this new register for the
Armada 38x.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 71d4eca5b497..474b2ebf4a82 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -515,7 +515,10 @@
 
 			sdhci@d8000 {
 				compatible = "marvell,armada-380-sdhci";
-				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+				reg-names = "sdhci", "mbus", "conf-sdio3";
+				reg = <0xd8000 0x1000>,
+					<0xdc000 0x100>,
+					<0x18454 0x4>;
 				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&gateclk 17>;
 				mrvl,clk-delay-cycles = <0x1F>;
-- 
1.9.1

[PATCH 7/7] ARM: mvebu: Add Device Tree description of SDHCI for Armada 388 RD

[Gregory CLEMENT]

The Device Tree description of SDHCI on Armada 388 RD board was
missing. This commit adds the node for it.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
 arch/arm/boot/dts/armada-388-rd.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index c98a8f8d01a9..7dfede145ea3 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -51,6 +51,16 @@
 				clock-frequency = <100000>;
 			};
 
+			sdhci@d8000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdhci_pins>;
+				broken-cd;
+				no-1-8-v;
+				wp-inverted;
+				bus-width = <8>;
+				status = "okay";
+			};
+
 			serial@12000 {
 				status = "okay";
 			};
-- 
1.9.1

Re: [PATCH 0/7] Fixes and improvements for SDHCI on Armada 38x

[Gregory CLEMENT]

On 21/01/2015 10:31, Gregory CLEMENT wrote:
> Hi,
> 
> this series brings fixes and improvements for the SDHCI controller of
> the Armada 38x SoCs.
> 
> The first two patches are fixes and should be also applied on the
> stable branch (I added stable in copy for this).
> 
> The first one removes the SDR50 and DDR50 mode timing from the
> capabilities of the controller because the current implementation
> doesn't support it.
> 
> The second one fix controller's caps according to the limitation of
> the hardware.
> 
> The third one extends the Device Tree binding of the Armada 38x. It
> allows using the SDIO3 configuration register.
> 
> The forth patch adds the support of this new register in the
> driver. Thanks to this one, specific clock adjustments can be done in
> order to support the SDR50 and DDR50 modes timing.
> 
> The fifth patch is device tree clean-up.
> 
> The sixth patch update the SDHCI node on Armada 38x in order to use
> the new register and then to be able to support the SDR50 and DDR50
> modes timing.
> 
> Finally, the seventh patch add the description of SDHCI for the Armada
> 388 RD board which was missing.
> 
> Patches 1 to 4 should be merged through the mmc tree and patches 5 to
> 7 should be merged through mvebu and then arm-soc.
> 
> Patch 4 depend on patch 2.
> Patch 2 depend on patch 1.
> And patch 1 depend on commit aa8165f91442 "mmc: sdhci-pxav3: do the
> mbus window configuration after enabling clocks" which have been
> merged.
> 
> But as all this patch should be merged through the same tree it would
> not be a problem
> 
> The patches 5 to 7 depend on the patches already merged in mvebu.
> 
> As they are fixes, patches 1 and 2 should be merged in 3.18-rc or at
> least in 3.19 and then they will be part of 3.18.1. For the other
> patches it would be nice if they could be part of 3.19.

I shifted the kernel release by one! I meant:

As they are fixes, patches 1 and 2 should be merged in _3.19-rc_ or at
least in _3.20_ and then they will be part of _3.19.1_. For the other
patches it would be nice if they could be part of _3.20_.

Thanks,

Gregory

> 
> Thanks,
> 
> Gregory
> 
> Gregory CLEMENT (7):
>   mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x
>     flavor
>   mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to
>     erratum ERR-7878951
>   mmc: sdhci-pxav3: Extend binding with SDIO3 conf reg for the Armada
>     38x
>   mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes
>   ARM: mvebu: Use macros for interrupt flags on Armada 38x sdhci node
>   ARM: mvebu: Update the SDHCI node on Armada 38x
>   ARM: mvebu: Add Device Tree description of SDHCI for Armada 388 RD
> 
>  .../devicetree/bindings/mmc/sdhci-pxa.txt          | 15 ++--
>  arch/arm/boot/dts/armada-388-rd.dts                | 10 +++
>  arch/arm/boot/dts/armada-38x.dtsi                  |  7 +-
>  drivers/mmc/host/sdhci-pxav3.c                     | 79 ++++++++++++++++++++++
>  4 files changed, 105 insertions(+), 6 deletions(-)
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 2/7] mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to erratum ERR-7878951

[Marcin Wojtas]

Hi Gregory,

2015-01-21 10:32 GMT+01:00 Gregory CLEMENT <gregory.clement@free-electrons.com>:
> According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
> different capabilities than the ones shown in its registers:
>
> - it doesn't support the voltage switching: it can work either with
>   3.3V or 1.8V supply
> - it doesn't support the SDR104 mode
> - SDR50 mode doesn't need tuning
>
> The SDHCI_QUIRK_MISSING_CAPS quirk is used for updating the
> capabilities accordingly.
>
> Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
> Cc: <stable@vger.kernel.org> # v3.15+
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
>  drivers/mmc/host/sdhci-pxav3.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 7b07325b4fba..4daa47a53a62 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -118,8 +118,11 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
>         return 0;
>  }
>
> -static int armada_38x_quirks(struct sdhci_host *host)
> +static int armada_38x_quirks(struct platform_device *pdev,
> +                            struct sdhci_host *host)
>  {
> +       struct device_node *np = pdev->dev.of_node;
> +
>         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
>         /*
>          * According to erratum 'FE-2946959' both SDR50 and DDR50
> @@ -129,6 +132,20 @@ static int armada_38x_quirks(struct sdhci_host *host)
>          */
>         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
>         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> +
> +       /*
> +        * According to erratum 'ERR-7878951' Armada 38x SDHCI
> +        * controller has different capabilities than the ones shown
> +        * in its registers
> +        */
> +       host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
> +       if (of_get_property(np, "no-1-8-v", NULL)) {
> +               host->caps &= ~SDHCI_CAN_VDD_180;
> +               host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
> +       } else
> +               host->caps &= ~SDHCI_CAN_VDD_330;
> +       host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
> +
>         return 0;
>  }
>
> @@ -333,7 +350,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>                 clk_prepare_enable(pxa->clk_core);
>
>         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
> -               ret = armada_38x_quirks(host);
> +               ret = armada_38x_quirks(pdev, host);
>                 if (ret < 0)
>                         goto err_quirks;
>                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
> --

Right here there are lines:
/* enable 1/8V DDR capable */
host->mmc->caps |= MMC_CAP_1_8V_DDR;

Which make a possible opposite change from armada_38x_quirks cacelled.

Best regards,
Marcin

Re: [PATCH 2/7] mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to erratum ERR-7878951

[Gregory CLEMENT]

Hi Marcin,

On 21/01/2015 15:52, Marcin Wojtas wrote:
> Hi Gregory,
> 
> 2015-01-21 10:32 GMT+01:00 Gregory CLEMENT <gregory.clement@free-electrons.com>:
>> According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
>> different capabilities than the ones shown in its registers:
>>
>> - it doesn't support the voltage switching: it can work either with
>>   3.3V or 1.8V supply
>> - it doesn't support the SDR104 mode
>> - SDR50 mode doesn't need tuning
>>
>> The SDHCI_QUIRK_MISSING_CAPS quirk is used for updating the
>> capabilities accordingly.
>>
>> Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
>> Cc: <stable@vger.kernel.org> # v3.15+
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>> ---
>>  drivers/mmc/host/sdhci-pxav3.c | 21 +++++++++++++++++++--
>>  1 file changed, 19 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
>> index 7b07325b4fba..4daa47a53a62 100644
>> --- a/drivers/mmc/host/sdhci-pxav3.c
>> +++ b/drivers/mmc/host/sdhci-pxav3.c
>> @@ -118,8 +118,11 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
>>         return 0;
>>  }
>>
>> -static int armada_38x_quirks(struct sdhci_host *host)
>> +static int armada_38x_quirks(struct platform_device *pdev,
>> +                            struct sdhci_host *host)
>>  {
>> +       struct device_node *np = pdev->dev.of_node;
>> +
>>         host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
>>         /*
>>          * According to erratum 'FE-2946959' both SDR50 and DDR50
>> @@ -129,6 +132,20 @@ static int armada_38x_quirks(struct sdhci_host *host)
>>          */
>>         host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
>>         host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
>> +
>> +       /*
>> +        * According to erratum 'ERR-7878951' Armada 38x SDHCI
>> +        * controller has different capabilities than the ones shown
>> +        * in its registers
>> +        */
>> +       host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
>> +       if (of_get_property(np, "no-1-8-v", NULL)) {
>> +               host->caps &= ~SDHCI_CAN_VDD_180;
>> +               host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
>> +       } else
>> +               host->caps &= ~SDHCI_CAN_VDD_330;
>> +       host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
>> +
>>         return 0;
>>  }
>>
>> @@ -333,7 +350,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>>                 clk_prepare_enable(pxa->clk_core);
>>
>>         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
>> -               ret = armada_38x_quirks(host);
>> +               ret = armada_38x_quirks(pdev, host);
>>                 if (ret < 0)
>>                         goto err_quirks;
>>                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
>> --
> 
> Right here there are lines:
> /* enable 1/8V DDR capable */
> host->mmc->caps |= MMC_CAP_1_8V_DDR;
> 
> Which make a possible opposite change from armada_38x_quirks cacelled.

Good catch!

I will remove it in the v2.

Thanks,

Gregory



-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com