From: Alim Akhtar <alim.akhtar@samsung.com>
To: Jaehoon Chung <jh80.chung@samsung.com>, linux-mmc@vger.kernel.org
Cc: ulf.hansson@linaro.org, k.kozlowski@samsung.com,
linux.amoon@gmail.com, jh80.chung@gmail.com
Subject: Re: [1/2] mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register
Date: Wed, 21 Oct 2015 16:55:46 +0530 [thread overview]
Message-ID: <5627763A.7030800@samsung.com> (raw)
In-Reply-To: <1445424582-7940-1-git-send-email-jh80.chung@samsung.com>
Hi Jaehoon
On 10/21/2015 04:19 PM, Jaehoon Chung wrote:
> According to DesignWare DoC file, CardThreshold bit should be
> bit[27:16].
> So it's correct to use (0xFFF << 16), not (0x1FFF << 16).
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>
Looks good.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
> drivers/mmc/host/dw_mmc.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
> index f2a88d4..01cdc86 100644
> --- a/drivers/mmc/host/dw_mmc.h
> +++ b/drivers/mmc/host/dw_mmc.h
> @@ -172,7 +172,7 @@
> /* Version ID register define */
> #define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
> /* Card read threshold */
> -#define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x))
> +#define SDMMC_SET_RD_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
> #define SDMMC_UHS_18V BIT(0)
> /* All ctrl reset bits */
> #define SDMMC_CTRL_ALL_RESET_FLAGS \
>
prev parent reply other threads:[~2015-10-21 11:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-21 10:49 [PATCH 1/2] mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register Jaehoon Chung
2015-10-21 10:49 ` [PATCH 2/2] mmc: dw_mmc: fix the wrong setting for UHS-DDR50 mode Jaehoon Chung
2015-10-21 11:21 ` [2/2] " Alim Akhtar
2015-10-21 11:25 ` Alim Akhtar [this message]
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