From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Subject: Re: [PATCH v2] mmc: dw_mmc: add hw_reset support Date: Mon, 04 Jan 2016 14:52:27 +0900 Message-ID: <568A089B.20109@samsung.com> References: <1451875854-12521-1-git-send-email-shawn.lin@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Received: from mailout3.samsung.com ([203.254.224.33]:54502 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751271AbcADFwc convert rfc822-to-8bit (ORCPT ); Mon, 4 Jan 2016 00:52:32 -0500 In-reply-to: <1451875854-12521-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-mmc-owner@vger.kernel.org List-Id: linux-mmc@vger.kernel.org To: Shawn Lin , Ulf Hansson Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org Hi, Shawn. On 01/04/2016 11:50 AM, Shawn Lin wrote: > This patch implement hw_reset function for DesignWare > MMC controller. By adding this feature, mmc blk can > do some basic recovery. >=20 >>>From Synopsys DesignWare Cores Mobile Storage Host Databook > (Section 7.4.4), we get the details: > 1. Program CMD12 to end any transfer in process. > 2. Wait for DTO, even if no response is sent back by the card. > 3. Set the following resets: > Software reset =E2=80=93 BMOD[0] for IDMAC only > DMA reset=E2=80=93 CTRL[2] > FIFO reset =E2=80=93 CTRL[1] bits > 4. Program the CARD_RESET register with a value of 0 for the bit > corresponding to the card number; This can be done at any time when > the card is connected to the controller. This programming asserts the > RST_n signal and resets the card. > 5. Wait for minimum of 1 =CE=BCs or cclk_in period, which ever is gre= ater > 6. After a minimum of 1 =CE=BCs, the application should program a val= ue of > 0 into the CARD_RESET register for the bit corresponding to the card > number. This de-asserts the RST_n signal and takes the card out of re= set. > 7. The application can program a new CMD only after a minimum of 200 = us > after the de-assertion of the RST_n signal, as per the MMC 4.41 stand= ard. >=20 > HW reset producer will be call in mmc_init_card before mmc_go_idle. A= t that > time=EF=BC=8Cdw mmc hasn't update clk for itself, so CMD12 is inappro= priate and > unnecessary. Moreover, if mmc device runs into broken states, DRTO or= RTO > generated by previous cmd w/ data will make mmc core issue stop alrea= dy. Then > it will retry again and again, issue stop and card status again until= the > cmd's retry number decrease to zero. That will finally trigger HW res= et producer > if we declare MMC_CAP_HW_RESET. So there's no need to do step 1 and 2= for the > reasons we mentioned above. Which IP version did you use? Could you share it..? Did you know about CHIP RESET sequence? >=20 > This implementation can be easily tested by cutting off->On vmmc whil= e doing data > accessing in background to simulate that case. And dw_mmc can generat= e timeout > interrupt and make mmc core trigger hw reset producer before re-init = mmc card > to recover itself. >=20 > Signed-off-by: Shawn Lin >=20 > --- >=20 > Changes in v2: > - remove unecessary mb > - reduce time cost for hw_reset > - combine SDMMC_CTRL_DMA_RESET and SDMMC_CTRL_FIFO_RESET >=20 > drivers/mmc/host/dw_mmc.c | 25 +++++++++++++++++++++++++ > drivers/mmc/host/dw_mmc.h | 4 ++++ > 2 files changed, 29 insertions(+) >=20 > diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c > index 7128351..98e75fc 100644 > --- a/drivers/mmc/host/dw_mmc.c > +++ b/drivers/mmc/host/dw_mmc.c > @@ -1477,6 +1477,30 @@ static int dw_mci_get_cd(struct mmc_host *mmc) > return present; > } > =20 > +static void dw_mci_hw_reset(struct mmc_host *mmc) > +{ > + struct dw_mci_slot *slot =3D mmc_priv(mmc); > + struct dw_mci *host =3D slot->host; > + > + if (host->use_dma =3D=3D TRANS_MODE_IDMAC) > + dw_mci_idmac_reset(host); > + > + if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET | > + SDMMC_CTRL_FIFO_RESET)) > + return; > + > + /* > + * According to eMMC spec, card reset procedure: > + * tRstW >=3D 1us: RST_n pulse width > + * tRSCA >=3D 200us: RST_n to Command time > + * tRSTH >=3D 1us: RST_n high period > + */ > + mci_writel(slot->host, RST_N, SDMMC_RST_HWRESET); Even though we used only one slot, but it needs to control bit with slo= t->id. Best Regards, Jaehoon Chung > + usleep_range(1, 2); > + mci_writel(slot->host, RST_N, SDMMC_RST_HWACTIVE); > + usleep_range(200, 300); > +} > + > static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *= card) > { > struct dw_mci_slot *slot =3D mmc_priv(mmc); > @@ -1563,6 +1587,7 @@ static const struct mmc_host_ops dw_mci_ops =3D= { > .set_ios =3D dw_mci_set_ios, > .get_ro =3D dw_mci_get_ro, > .get_cd =3D dw_mci_get_cd, > + .hw_reset =3D dw_mci_hw_reset, > .enable_sdio_irq =3D dw_mci_enable_sdio_irq, > .execute_tuning =3D dw_mci_execute_tuning, > .card_busy =3D dw_mci_card_busy, > diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h > index f695b58..684ee34 100644 > --- a/drivers/mmc/host/dw_mmc.h > +++ b/drivers/mmc/host/dw_mmc.h > @@ -46,6 +46,7 @@ > #define SDMMC_VERID 0x06c > #define SDMMC_HCON 0x070 > #define SDMMC_UHS_REG 0x074 > +#define SDMMC_RST_N 0x078 > #define SDMMC_BMOD 0x080 > #define SDMMC_PLDMND 0x084 > #define SDMMC_DBADDR 0x088 > @@ -169,6 +170,9 @@ > #define SDMMC_IDMAC_ENABLE BIT(7) > #define SDMMC_IDMAC_FB BIT(1) > #define SDMMC_IDMAC_SWRESET BIT(0) > +/* H/W reset */ > +#define SDMMC_RST_HWACTIVE 0x1 > +#define SDMMC_RST_HWRESET 0x0 > /* Version ID register define */ > #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) > /* Card read threshold */ >=20