[PATCH v5 00/14] Initial Microchip PIC32MZDA Support

[PATCH v5 00/14] Initial Microchip PIC32MZDA Support

[Joshua Henderson]

This patch series adds support for the Microchip PIC32MZDA MIPS platform.
All drivers required to boot from a MMC uSD card are included. Clock,
external interrupt controller, serial, SDHCI, and pinctrl/gpio drivers
are included. This has been tested on a PIC32MZDA Starter Kit. A tree
with these changes is available at [0].

[0] https://github.com/joshua-henderson/linux/tree/pic32-upstream-v5

Changes since v4 (https://lkml.org/lkml/2016/1/8/964
	          https://lkml.org/lkml/2016/1/8/965):

	+ Add soc node for core timer interrupt to DTS
        + Add external IRQ property to DTS
	+ Clean up irq alloc on failure
        + Fix rework regression with handling failure in probe
	+ Select config PIC32_EVIC for PIC32MZDA
        + Implement get_c0_compare_int() in platform using DTS
	+ Rearchitect (rewrite) to use generic chip
        + Be consistent with naming of functions, use pic32_ prefix
        + Move get_c0_compare_int() to platform where it belongs
        + Drop obsolete header
        + Add comments about the handler flow of the different interrupt types
        + Prevent external interrupts from being requested as level flow type
        + Simplify/optimize register access
        + Configure external interrupts from DT
        + Simplify plat_irq_dispatch() implementation
        + Change irq chip names to evic-*
        + Add EVIC_PIC32 config option and have platform select it
        + Support to configure core timer interrupt from DT
        + Use proper code comment formatting
	+ Add new microchip,external-interrupts property
        + Provide a better description of some of the features
        + Clean up formatting

Changes since v3 (https://lkml.org/lkml/2016/1/7/760):

	+ Remove broken URL and use full manual name for boot protocol
	+ Formatting and comment location
	+ Move functions to remove need for forward declaration

Changes since v2 (https://lkml.org/lkml/2015/12/14/818):

	+ Prefer dt/bindings: prefix for subject
	+ Remove redundant irq_chip functions in interrupt driver
	+ Use 'sdhci_pltfm_*' instead of 'sdhci_*_host' and other cleanup
	+ Use dynamic major/minor and ttyPIC* instead of ttyS*
	+ Follow device-tree node naming convention for clocks
	+ Remove pinctrl pins that are not port pins
	+ Force lowercase in PIC32 clock binding documentation
	+ Replace __clk_debug with pr_debug
	+ Add of_clk_parent_fill usage in PIC32 clock driver
	+ UART: Remove unused header files
	+ UART: Refactor register read/write functions
	+ UART: Reorder arguments to readl/writel functions
	+ UART: Add missing initializations to termios
	+ UART: Fix clk enable/disable mismatch

Changes since v1 (https://lkml.org/lkml/2015/11/20/848):

	+ Rename all DT compatible properties to be chip specific.
	+ Remove hardware interrupt priorities from interrupt controller DT
	  bindings.
	+ Remove all dependencies on include headers used by PIC32 DTS
	  files.
	+ Remove arch/mips/include/asm/mach-pic32/gpio.h
	+ Drop usage of the following, mostly non-standard, properties in
	  DT bindings:
		device_type
		piomode
		no-1-8-v
		uart-has-rtscts
		clock-frequency => assigned-clock-rate
	+ Remove PIC32 memory PLL support from DT.
	+ Replace empty 'ranges' with populated one for clock tree node.
	+ Rename all instances of "USART" to "UART".
	+ Remove 'interrupts' property from FSCM of PIC32 clock tree node.
	+ Add default REFCLK rate initialization required for SDHCI in DTS.
	+ Remove default frequency setup for REFOSC clocks in -clk DTS.
	+ Address missing static on local functions and other sparse
	  warnings in several drivers.
	+ Update pinctrl driver to address major binding and architectural
	  issues.
	+ Remove redundant probing 'pb7_clk' to find CPU clock.
	+ Remove unused PIC32 MPLL support.
	+ Remove support for initializing default parent/rate for REFOSC
	  clocks.
	+ Be consistent and use only "SDHCI" when referring to SD host
	  controller
	+ Remove unnecessary PIC32 sdhci_ops min clock function.
	+ Make platform PIC32[_CLR|_SET|_INV] register macros safer.


Andrei Pistirica (4):
  dt/bindings: Add bindings for PIC32 UART driver
  serial: pic32_uart: Add PIC32 UART driver
  dt/bindings: Add bindings for PIC32 SDHCI host controller
  mmc: sdhci-pic32: Add PIC32 SDHCI host controller driver

Cristian Birsan (2):
  dt/bindings: Add bindings for PIC32 interrupt controller
  irqchip: irq-pic32-evic: Add support for PIC32 interrupt controller

Joshua Henderson (6):
  dt/bindings: Add bindings for PIC32/MZDA platforms
  MIPS: Add support for PIC32MZDA platform
  dt/bindings: Add bindings for PIC32 pin control and GPIO
  pinctrl: pinctrl-pic32: Add PIC32 pin control driver
  MIPS: dts: Add initial DTS for the PIC32MZDA Starter Kit
  MIPS: pic32mzda: Add initial PIC32MZDA Starter Kit defconfig

Purna Chandra Mandal (2):
  dt/bindings: Add PIC32 clock binding documentation
  clk: clk-pic32: Add PIC32 clock driver

 .../devicetree/bindings/clock/microchip,pic32.txt  |  257 +++
 .../bindings/gpio/microchip,pic32-gpio.txt         |   49 +
 .../interrupt-controller/microchip,pic32-evic.txt  |   67 +
 .../bindings/mips/pic32/microchip,pic32mzda.txt    |   31 +
 .../bindings/mmc/microchip,sdhci-pic32.txt         |   29 +
 .../bindings/pinctrl/microchip,pic32-pinctrl.txt   |   60 +
 .../bindings/serial/microchip,pic32-uart.txt       |   29 +
 arch/mips/Kbuild.platforms                         |    1 +
 arch/mips/Kconfig                                  |    9 +
 arch/mips/boot/dts/Makefile                        |    1 +
 arch/mips/boot/dts/pic32/Makefile                  |   12 +
 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi        |  236 ++
 arch/mips/boot/dts/pic32/pic32mzda.dtsi            |  281 +++
 arch/mips/boot/dts/pic32/pic32mzda_sk.dts          |  151 ++
 arch/mips/configs/pic32mzda_defconfig              |   89 +
 .../include/asm/mach-pic32/cpu-feature-overrides.h |   32 +
 arch/mips/include/asm/mach-pic32/irq.h             |   22 +
 arch/mips/include/asm/mach-pic32/pic32.h           |   44 +
 arch/mips/include/asm/mach-pic32/spaces.h          |   24 +
 arch/mips/pic32/Kconfig                            |   51 +
 arch/mips/pic32/Makefile                           |    6 +
 arch/mips/pic32/Platform                           |    7 +
 arch/mips/pic32/common/Makefile                    |    5 +
 arch/mips/pic32/common/irq.c                       |   21 +
 arch/mips/pic32/common/reset.c                     |   62 +
 arch/mips/pic32/pic32mzda/Makefile                 |    9 +
 arch/mips/pic32/pic32mzda/config.c                 |  126 ++
 arch/mips/pic32/pic32mzda/early_clk.c              |  106 +
 arch/mips/pic32/pic32mzda/early_console.c          |  171 ++
 arch/mips/pic32/pic32mzda/early_pin.c              |  275 +++
 arch/mips/pic32/pic32mzda/early_pin.h              |  241 ++
 arch/mips/pic32/pic32mzda/init.c                   |  156 ++
 arch/mips/pic32/pic32mzda/pic32mzda.h              |   29 +
 arch/mips/pic32/pic32mzda/time.c                   |   73 +
 drivers/clk/Kconfig                                |    3 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/clk-pic32.c                            | 1801 +++++++++++++++
 drivers/irqchip/Kconfig                            |    5 +
 drivers/irqchip/Makefile                           |    1 +
 drivers/irqchip/irq-pic32-evic.c                   |  324 +++
 drivers/mmc/host/Kconfig                           |   11 +
 drivers/mmc/host/Makefile                          |    1 +
 drivers/mmc/host/sdhci-pic32.c                     |  257 +++
 drivers/pinctrl/Kconfig                            |   17 +
 drivers/pinctrl/Makefile                           |    1 +
 drivers/pinctrl/pinctrl-pic32.c                    | 2339 ++++++++++++++++++++
 drivers/pinctrl/pinctrl-pic32.h                    |  141 ++
 drivers/tty/serial/Kconfig                         |   21 +
 drivers/tty/serial/Makefile                        |    1 +
 drivers/tty/serial/pic32_uart.c                    |  960 ++++++++
 drivers/tty/serial/pic32_uart.h                    |  126 ++
 include/linux/platform_data/sdhci-pic32.h          |   22 +
 include/uapi/linux/serial_core.h                   |    3 +
 53 files changed, 8797 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/microchip,pic32.txt
 create mode 100644 Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32-evic.txt
 create mode 100644 Documentation/devicetree/bindings/mips/pic32/microchip,pic32mzda.txt
 create mode 100644 Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt
 create mode 100644 arch/mips/boot/dts/pic32/Makefile
 create mode 100644 arch/mips/boot/dts/pic32/pic32mzda-clk.dtsi
 create mode 100644 arch/mips/boot/dts/pic32/pic32mzda.dtsi
 create mode 100644 arch/mips/boot/dts/pic32/pic32mzda_sk.dts
 create mode 100644 arch/mips/configs/pic32mzda_defconfig
 create mode 100644 arch/mips/include/asm/mach-pic32/cpu-feature-overrides.h
 create mode 100644 arch/mips/include/asm/mach-pic32/irq.h
 create mode 100644 arch/mips/include/asm/mach-pic32/pic32.h
 create mode 100644 arch/mips/include/asm/mach-pic32/spaces.h
 create mode 100644 arch/mips/pic32/Kconfig
 create mode 100644 arch/mips/pic32/Makefile
 create mode 100644 arch/mips/pic32/Platform
 create mode 100644 arch/mips/pic32/common/Makefile
 create mode 100644 arch/mips/pic32/common/irq.c
 create mode 100644 arch/mips/pic32/common/reset.c
 create mode 100644 arch/mips/pic32/pic32mzda/Makefile
 create mode 100644 arch/mips/pic32/pic32mzda/config.c
 create mode 100644 arch/mips/pic32/pic32mzda/early_clk.c
 create mode 100644 arch/mips/pic32/pic32mzda/early_console.c
 create mode 100644 arch/mips/pic32/pic32mzda/early_pin.c
 create mode 100644 arch/mips/pic32/pic32mzda/early_pin.h
 create mode 100644 arch/mips/pic32/pic32mzda/init.c
 create mode 100644 arch/mips/pic32/pic32mzda/pic32mzda.h
 create mode 100644 arch/mips/pic32/pic32mzda/time.c
 create mode 100644 drivers/clk/clk-pic32.c
 create mode 100644 drivers/irqchip/irq-pic32-evic.c
 create mode 100644 drivers/mmc/host/sdhci-pic32.c
 create mode 100644 drivers/pinctrl/pinctrl-pic32.c
 create mode 100644 drivers/pinctrl/pinctrl-pic32.h
 create mode 100644 drivers/tty/serial/pic32_uart.c
 create mode 100644 drivers/tty/serial/pic32_uart.h
 create mode 100644 include/linux/platform_data/sdhci-pic32.h

--
1.7.9.5

[PATCH v5 12/14] mmc: sdhci-pic32: Add PIC32 SDHCI host controller driver

[Joshua Henderson]

From: Andrei Pistirica <andrei.pistirica@microchip.com>

This driver supports the SDHCI host controller found on a PIC32.

Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
---
Changes since v4: None
Changes since v3: None
Changes since v2:
	- Use 'sdhci_pltfm_*' instead of 'sdhci_*_host' and other cleanup
Changes since v1:
	- Be consistent and use only "SDHCI" when referring to SD host
	  controller
	- Remove unnecessary PIC32 sdhci_ops min clock function.
	- Drop usage of piomode and no-1-8-v DT properties
        - Formatting
        - Fix use of devm_iounmap
        - Address code comment
---
 drivers/mmc/host/Kconfig       |   11 ++
 drivers/mmc/host/Makefile      |    1 +
 drivers/mmc/host/sdhci-pic32.c |  257 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 269 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-pic32.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1dee533..c6a8916 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -785,3 +785,14 @@ config MMC_MTK
 	  If you have a machine with a integrated SD/MMC card reader, say Y or M here.
 	  This is needed if support for any SD/SDIO/MMC devices is required.
 	  If unsure, say N.
+
+config MMC_SDHCI_MICROCHIP_PIC32
+        tristate "Microchip PIC32MZDA SDHCI support"
+        depends on MMC_SDHCI && PIC32MZDA && MMC_SDHCI_PLTFM
+        help
+          This selects the Secure Digital Host Controller Interface (SDHCI)
+          for PIC32MZDA platform.
+
+          If you have a controller with this interface, say Y or M here.
+
+          If unsure, say N.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 3595f83..af918d2 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
 obj-$(CONFIG_MMC_SDHCI_IPROC)		+= sdhci-iproc.o
 obj-$(CONFIG_MMC_SDHCI_MSM)		+= sdhci-msm.o
 obj-$(CONFIG_MMC_SDHCI_ST)		+= sdhci-st.o
+obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32)	+= sdhci-pic32.o
 
 ifeq ($(CONFIG_CB710_DEBUG),y)
 	CFLAGS-cb710-mmc	+= -DDEBUG
diff --git a/drivers/mmc/host/sdhci-pic32.c b/drivers/mmc/host/sdhci-pic32.c
new file mode 100644
index 0000000..059df70
--- /dev/null
+++ b/drivers/mmc/host/sdhci-pic32.c
@@ -0,0 +1,257 @@
+/*
+ * Support of SDHCI platform devices for Microchip PIC32.
+ *
+ * Copyright (C) 2015 Microchip
+ * Andrei Pistirica, Paul Thacker
+ *
+ * Inspired by sdhci-pltfm.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/highmem.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/mmc/host.h>
+#include <linux/io.h>
+#include "sdhci.h"
+#include "sdhci-pltfm.h"
+#include <linux/platform_data/sdhci-pic32.h>
+
+#define SDH_SHARED_BUS_CTRL		0x000000E0
+#define SDH_SHARED_BUS_NR_CLK_PINS_MASK	0x7
+#define SDH_SHARED_BUS_NR_IRQ_PINS_MASK	0x30
+#define SDH_SHARED_BUS_CLK_PINS		0x10
+#define SDH_SHARED_BUS_IRQ_PINS		0x14
+#define SDH_CAPS_SDH_SLOT_TYPE_MASK	0xC0000000
+#define SDH_SLOT_TYPE_REMOVABLE		0x0
+#define SDH_SLOT_TYPE_EMBEDDED		0x1
+#define SDH_SLOT_TYPE_SHARED_BUS	0x2
+#define SDHCI_CTRL_CDSSEL		0x80
+#define SDHCI_CTRL_CDTLVL		0x40
+
+#define ADMA_FIFO_RD_THSHLD	512
+#define ADMA_FIFO_WR_THSHLD	512
+
+struct pic32_sdhci_priv {
+	struct platform_device	*pdev;
+	struct clk *sys_clk;
+	struct clk *base_clk;
+};
+
+static unsigned int pic32_sdhci_get_max_clock(struct sdhci_host *host)
+{
+	struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
+
+	return clk_get_rate(sdhci_pdata->base_clk);
+}
+
+static void pic32_sdhci_set_bus_width(struct sdhci_host *host, int width)
+{
+	u8 ctrl;
+
+	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+	if (width == MMC_BUS_WIDTH_8) {
+		ctrl &= ~SDHCI_CTRL_4BITBUS;
+		if (host->version >= SDHCI_SPEC_300)
+			ctrl |= SDHCI_CTRL_8BITBUS;
+	} else {
+		if (host->version >= SDHCI_SPEC_300)
+			ctrl &= ~SDHCI_CTRL_8BITBUS;
+		if (width == MMC_BUS_WIDTH_4)
+			ctrl |= SDHCI_CTRL_4BITBUS;
+		else
+			ctrl &= ~SDHCI_CTRL_4BITBUS;
+	}
+
+	/* CD select and test bits must be set for errata workaround. */
+	ctrl &= ~SDHCI_CTRL_CDTLVL;
+	ctrl |= SDHCI_CTRL_CDSSEL;
+	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
+static unsigned int pic32_sdhci_get_ro(struct sdhci_host *host)
+{
+	/*
+	 * The SDHCI_WRITE_PROTECT bit is unstable on current hardware so we
+	 * can't depend on its value in any way.
+	 */
+	return 0;
+}
+
+static const struct sdhci_ops pic32_sdhci_ops = {
+	.get_max_clock = pic32_sdhci_get_max_clock,
+	.set_clock = sdhci_set_clock,
+	.set_bus_width = pic32_sdhci_set_bus_width,
+	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_set_uhs_signaling,
+	.get_ro = pic32_sdhci_get_ro,
+};
+
+static struct sdhci_pltfm_data sdhci_pic32_pdata = {
+	.ops = &pic32_sdhci_ops,
+	.quirks = SDHCI_QUIRK_NO_HISPD_BIT,
+	.quirks2 = SDHCI_QUIRK2_NO_1_8_V,
+};
+
+static void pic32_sdhci_shared_bus(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL);
+	u32 clk_pins = (bus & SDH_SHARED_BUS_NR_CLK_PINS_MASK) >> 0;
+	u32 irq_pins = (bus & SDH_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4;
+
+	/* select first clock */
+	if (clk_pins & 1)
+		bus |= (1 << SDH_SHARED_BUS_CLK_PINS);
+
+	/* select first interrupt */
+	if (irq_pins & 1)
+		bus |= (1 << SDH_SHARED_BUS_IRQ_PINS);
+
+	writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL);
+}
+
+static int pic32_sdhci_probe_platform(struct platform_device *pdev,
+				      struct pic32_sdhci_priv *pdata)
+{
+	int ret = 0;
+	u32 caps_slot_type;
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+
+	/* Check card slot connected on shared bus. */
+	host->caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
+	caps_slot_type = (host->caps & SDH_CAPS_SDH_SLOT_TYPE_MASK) >> 30;
+	if (caps_slot_type == SDH_SLOT_TYPE_SHARED_BUS)
+		pic32_sdhci_shared_bus(pdev);
+
+	return ret;
+}
+
+static int pic32_sdhci_probe(struct platform_device *pdev)
+{
+	struct sdhci_host *host;
+	struct sdhci_pltfm_host *pltfm_host;
+	struct pic32_sdhci_priv *sdhci_pdata;
+	struct pic32_sdhci_platform_data *plat_data;
+	int ret;
+
+	host = sdhci_pltfm_init(pdev, &sdhci_pic32_pdata,
+				sizeof(struct pic32_sdhci_priv));
+	if (IS_ERR(host)) {
+		ret = PTR_ERR(host);
+		goto err;
+	}
+
+	pltfm_host = sdhci_priv(host);
+	sdhci_pdata = sdhci_pltfm_priv(pltfm_host);
+
+	plat_data = pdev->dev.platform_data;
+	if (plat_data && plat_data->setup_dma) {
+		ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD,
+					   ADMA_FIFO_WR_THSHLD);
+		if (ret)
+			goto err_host;
+	}
+
+	sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk");
+	if (IS_ERR(sdhci_pdata->sys_clk)) {
+		ret = PTR_ERR(sdhci_pdata->sys_clk);
+		dev_err(&pdev->dev, "Error getting clock\n");
+		goto err_host;
+	}
+
+	ret = clk_prepare_enable(sdhci_pdata->sys_clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Error enabling clock\n");
+		goto err_host;
+	}
+
+	sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk");
+	if (IS_ERR(sdhci_pdata->base_clk)) {
+		ret = PTR_ERR(sdhci_pdata->base_clk);
+		dev_err(&pdev->dev, "Error getting clock\n");
+		goto err_sys_clk;
+	}
+
+	ret = clk_prepare_enable(sdhci_pdata->base_clk);
+	if (ret) {
+		dev_err(&pdev->dev, "Error enabling clock\n");
+		goto err_base_clk;
+	}
+
+	ret = mmc_of_parse(host->mmc);
+	if (ret)
+		goto err_base_clk;
+
+	ret = pic32_sdhci_probe_platform(pdev, sdhci_pdata);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to probe platform!\n");
+		goto err_base_clk;
+	}
+
+	ret = sdhci_add_host(host);
+	if (ret) {
+		dev_err(&pdev->dev, "error adding host\n");
+		goto err_base_clk;
+	}
+
+	dev_info(&pdev->dev, "Successfully added sdhci host\n");
+	return 0;
+
+err_base_clk:
+	clk_disable_unprepare(sdhci_pdata->base_clk);
+err_sys_clk:
+	clk_disable_unprepare(sdhci_pdata->sys_clk);
+err_host:
+	sdhci_pltfm_free(pdev);
+err:
+	dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret);
+	return ret;
+}
+
+static int pic32_sdhci_remove(struct platform_device *pdev)
+{
+	struct sdhci_host *host = platform_get_drvdata(pdev);
+	struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
+	u32 scratch;
+
+	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
+	sdhci_remove_host(host, scratch == (u32)~0);
+	clk_disable_unprepare(sdhci_pdata->base_clk);
+	clk_disable_unprepare(sdhci_pdata->sys_clk);
+	sdhci_pltfm_free(pdev);
+
+	return 0;
+}
+
+static const struct of_device_id pic32_sdhci_id_table[] = {
+	{ .compatible = "microchip,pic32mzda-sdhci" },
+	{}
+};
+MODULE_DEVICE_TABLE(of, pic32_sdhci_id_table);
+
+static struct platform_driver pic32_sdhci_driver = {
+	.driver = {
+		.name	= "pic32-sdhci",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(pic32_sdhci_id_table),
+	},
+	.probe		= pic32_sdhci_probe,
+	.remove		= pic32_sdhci_remove,
+};
+
+module_platform_driver(pic32_sdhci_driver);
+
+MODULE_DESCRIPTION("Microchip PIC32 SDHCI driver");
+MODULE_AUTHOR("Pistirica Sorin Andrei & Sandeep Sheriker");
+MODULE_LICENSE("GPL v2");
-- 
1.7.9.5

Re: [PATCH v5 02/14] irqchip: irq-pic32-evic: Add support for PIC32 interrupt controller

[Ralf Baechle]

On Thu, Jan 14, 2016 at 09:10:09AM +0100, Thomas Gleixner wrote:

> I like that approach.
> 
> So except for the nit in pic32_set_type_edge() this looks good. It's pretty
> clear now what the code does and how the hardware works.
> 
> Thanks for following up!

So I take that for an ack.  I still haven't seen any acks or comments for
the patches:

     4/14      drivers/clk
     8/14      drivers/pinctrl
    10/14      drivers/serial
    12/14      drivers/mmc

Of this series.  Ping?

  Ralf

Re: [PATCH v5 12/14] mmc: sdhci-pic32: Add PIC32 SDHCI host controller driver

[Joshua Henderson]

Hi Ulf,

Ping! Need an ack for this or pull it upstream.

On 01/13/2016 06:15 PM, Joshua Henderson wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
> 
> This driver supports the SDHCI host controller found on a PIC32.
> 
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> ---
> Changes since v4: None
> Changes since v3: None
> Changes since v2:
> 	- Use 'sdhci_pltfm_*' instead of 'sdhci_*_host' and other cleanup
> Changes since v1:
> 	- Be consistent and use only "SDHCI" when referring to SD host
> 	  controller
> 	- Remove unnecessary PIC32 sdhci_ops min clock function.
> 	- Drop usage of piomode and no-1-8-v DT properties
>         - Formatting
>         - Fix use of devm_iounmap
>         - Address code comment
> ---
>  drivers/mmc/host/Kconfig       |   11 ++
>  drivers/mmc/host/Makefile      |    1 +
>  drivers/mmc/host/sdhci-pic32.c |  257 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 269 insertions(+)
>  create mode 100644 drivers/mmc/host/sdhci-pic32.c
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 1dee533..c6a8916 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -785,3 +785,14 @@ config MMC_MTK
>  	  If you have a machine with a integrated SD/MMC card reader, say Y or M here.
>  	  This is needed if support for any SD/SDIO/MMC devices is required.
>  	  If unsure, say N.
> +
> +config MMC_SDHCI_MICROCHIP_PIC32
> +        tristate "Microchip PIC32MZDA SDHCI support"
> +        depends on MMC_SDHCI && PIC32MZDA && MMC_SDHCI_PLTFM
> +        help
> +          This selects the Secure Digital Host Controller Interface (SDHCI)
> +          for PIC32MZDA platform.
> +
> +          If you have a controller with this interface, say Y or M here.
> +
> +          If unsure, say N.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 3595f83..af918d2 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -75,6 +75,7 @@ obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
>  obj-$(CONFIG_MMC_SDHCI_IPROC)		+= sdhci-iproc.o
>  obj-$(CONFIG_MMC_SDHCI_MSM)		+= sdhci-msm.o
>  obj-$(CONFIG_MMC_SDHCI_ST)		+= sdhci-st.o
> +obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32)	+= sdhci-pic32.o
>  
>  ifeq ($(CONFIG_CB710_DEBUG),y)
>  	CFLAGS-cb710-mmc	+= -DDEBUG
> diff --git a/drivers/mmc/host/sdhci-pic32.c b/drivers/mmc/host/sdhci-pic32.c
> new file mode 100644
> index 0000000..059df70
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-pic32.c
> @@ -0,0 +1,257 @@
> +/*
> + * Support of SDHCI platform devices for Microchip PIC32.
> + *
> + * Copyright (C) 2015 Microchip
> + * Andrei Pistirica, Paul Thacker
> + *
> + * Inspired by sdhci-pltfm.c
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/highmem.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm.h>
> +#include <linux/slab.h>
> +#include <linux/mmc/host.h>
> +#include <linux/io.h>
> +#include "sdhci.h"
> +#include "sdhci-pltfm.h"
> +#include <linux/platform_data/sdhci-pic32.h>
> +
> +#define SDH_SHARED_BUS_CTRL		0x000000E0
> +#define SDH_SHARED_BUS_NR_CLK_PINS_MASK	0x7
> +#define SDH_SHARED_BUS_NR_IRQ_PINS_MASK	0x30
> +#define SDH_SHARED_BUS_CLK_PINS		0x10
> +#define SDH_SHARED_BUS_IRQ_PINS		0x14
> +#define SDH_CAPS_SDH_SLOT_TYPE_MASK	0xC0000000
> +#define SDH_SLOT_TYPE_REMOVABLE		0x0
> +#define SDH_SLOT_TYPE_EMBEDDED		0x1
> +#define SDH_SLOT_TYPE_SHARED_BUS	0x2
> +#define SDHCI_CTRL_CDSSEL		0x80
> +#define SDHCI_CTRL_CDTLVL		0x40
> +
> +#define ADMA_FIFO_RD_THSHLD	512
> +#define ADMA_FIFO_WR_THSHLD	512
> +
> +struct pic32_sdhci_priv {
> +	struct platform_device	*pdev;
> +	struct clk *sys_clk;
> +	struct clk *base_clk;
> +};
> +
> +static unsigned int pic32_sdhci_get_max_clock(struct sdhci_host *host)
> +{
> +	struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
> +
> +	return clk_get_rate(sdhci_pdata->base_clk);
> +}
> +
> +static void pic32_sdhci_set_bus_width(struct sdhci_host *host, int width)
> +{
> +	u8 ctrl;
> +
> +	ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> +	if (width == MMC_BUS_WIDTH_8) {
> +		ctrl &= ~SDHCI_CTRL_4BITBUS;
> +		if (host->version >= SDHCI_SPEC_300)
> +			ctrl |= SDHCI_CTRL_8BITBUS;
> +	} else {
> +		if (host->version >= SDHCI_SPEC_300)
> +			ctrl &= ~SDHCI_CTRL_8BITBUS;
> +		if (width == MMC_BUS_WIDTH_4)
> +			ctrl |= SDHCI_CTRL_4BITBUS;
> +		else
> +			ctrl &= ~SDHCI_CTRL_4BITBUS;
> +	}
> +
> +	/* CD select and test bits must be set for errata workaround. */
> +	ctrl &= ~SDHCI_CTRL_CDTLVL;
> +	ctrl |= SDHCI_CTRL_CDSSEL;
> +	sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> +}
> +
> +static unsigned int pic32_sdhci_get_ro(struct sdhci_host *host)
> +{
> +	/*
> +	 * The SDHCI_WRITE_PROTECT bit is unstable on current hardware so we
> +	 * can't depend on its value in any way.
> +	 */
> +	return 0;
> +}
> +
> +static const struct sdhci_ops pic32_sdhci_ops = {
> +	.get_max_clock = pic32_sdhci_get_max_clock,
> +	.set_clock = sdhci_set_clock,
> +	.set_bus_width = pic32_sdhci_set_bus_width,
> +	.reset = sdhci_reset,
> +	.set_uhs_signaling = sdhci_set_uhs_signaling,
> +	.get_ro = pic32_sdhci_get_ro,
> +};
> +
> +static struct sdhci_pltfm_data sdhci_pic32_pdata = {
> +	.ops = &pic32_sdhci_ops,
> +	.quirks = SDHCI_QUIRK_NO_HISPD_BIT,
> +	.quirks2 = SDHCI_QUIRK2_NO_1_8_V,
> +};
> +
> +static void pic32_sdhci_shared_bus(struct platform_device *pdev)
> +{
> +	struct sdhci_host *host = platform_get_drvdata(pdev);
> +	u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL);
> +	u32 clk_pins = (bus & SDH_SHARED_BUS_NR_CLK_PINS_MASK) >> 0;
> +	u32 irq_pins = (bus & SDH_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4;
> +
> +	/* select first clock */
> +	if (clk_pins & 1)
> +		bus |= (1 << SDH_SHARED_BUS_CLK_PINS);
> +
> +	/* select first interrupt */
> +	if (irq_pins & 1)
> +		bus |= (1 << SDH_SHARED_BUS_IRQ_PINS);
> +
> +	writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL);
> +}
> +
> +static int pic32_sdhci_probe_platform(struct platform_device *pdev,
> +				      struct pic32_sdhci_priv *pdata)
> +{
> +	int ret = 0;
> +	u32 caps_slot_type;
> +	struct sdhci_host *host = platform_get_drvdata(pdev);
> +
> +	/* Check card slot connected on shared bus. */
> +	host->caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
> +	caps_slot_type = (host->caps & SDH_CAPS_SDH_SLOT_TYPE_MASK) >> 30;
> +	if (caps_slot_type == SDH_SLOT_TYPE_SHARED_BUS)
> +		pic32_sdhci_shared_bus(pdev);
> +
> +	return ret;
> +}
> +
> +static int pic32_sdhci_probe(struct platform_device *pdev)
> +{
> +	struct sdhci_host *host;
> +	struct sdhci_pltfm_host *pltfm_host;
> +	struct pic32_sdhci_priv *sdhci_pdata;
> +	struct pic32_sdhci_platform_data *plat_data;
> +	int ret;
> +
> +	host = sdhci_pltfm_init(pdev, &sdhci_pic32_pdata,
> +				sizeof(struct pic32_sdhci_priv));
> +	if (IS_ERR(host)) {
> +		ret = PTR_ERR(host);
> +		goto err;
> +	}
> +
> +	pltfm_host = sdhci_priv(host);
> +	sdhci_pdata = sdhci_pltfm_priv(pltfm_host);
> +
> +	plat_data = pdev->dev.platform_data;
> +	if (plat_data && plat_data->setup_dma) {
> +		ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD,
> +					   ADMA_FIFO_WR_THSHLD);
> +		if (ret)
> +			goto err_host;
> +	}
> +
> +	sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk");
> +	if (IS_ERR(sdhci_pdata->sys_clk)) {
> +		ret = PTR_ERR(sdhci_pdata->sys_clk);
> +		dev_err(&pdev->dev, "Error getting clock\n");
> +		goto err_host;
> +	}
> +
> +	ret = clk_prepare_enable(sdhci_pdata->sys_clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Error enabling clock\n");
> +		goto err_host;
> +	}
> +
> +	sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk");
> +	if (IS_ERR(sdhci_pdata->base_clk)) {
> +		ret = PTR_ERR(sdhci_pdata->base_clk);
> +		dev_err(&pdev->dev, "Error getting clock\n");
> +		goto err_sys_clk;
> +	}
> +
> +	ret = clk_prepare_enable(sdhci_pdata->base_clk);
> +	if (ret) {
> +		dev_err(&pdev->dev, "Error enabling clock\n");
> +		goto err_base_clk;
> +	}
> +
> +	ret = mmc_of_parse(host->mmc);
> +	if (ret)
> +		goto err_base_clk;
> +
> +	ret = pic32_sdhci_probe_platform(pdev, sdhci_pdata);
> +	if (ret) {
> +		dev_err(&pdev->dev, "failed to probe platform!\n");
> +		goto err_base_clk;
> +	}
> +
> +	ret = sdhci_add_host(host);
> +	if (ret) {
> +		dev_err(&pdev->dev, "error adding host\n");
> +		goto err_base_clk;
> +	}
> +
> +	dev_info(&pdev->dev, "Successfully added sdhci host\n");
> +	return 0;
> +
> +err_base_clk:
> +	clk_disable_unprepare(sdhci_pdata->base_clk);
> +err_sys_clk:
> +	clk_disable_unprepare(sdhci_pdata->sys_clk);
> +err_host:
> +	sdhci_pltfm_free(pdev);
> +err:
> +	dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret);
> +	return ret;
> +}
> +
> +static int pic32_sdhci_remove(struct platform_device *pdev)
> +{
> +	struct sdhci_host *host = platform_get_drvdata(pdev);
> +	struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
> +	u32 scratch;
> +
> +	scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
> +	sdhci_remove_host(host, scratch == (u32)~0);
> +	clk_disable_unprepare(sdhci_pdata->base_clk);
> +	clk_disable_unprepare(sdhci_pdata->sys_clk);
> +	sdhci_pltfm_free(pdev);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id pic32_sdhci_id_table[] = {
> +	{ .compatible = "microchip,pic32mzda-sdhci" },
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, pic32_sdhci_id_table);
> +
> +static struct platform_driver pic32_sdhci_driver = {
> +	.driver = {
> +		.name	= "pic32-sdhci",
> +		.owner	= THIS_MODULE,
> +		.of_match_table = of_match_ptr(pic32_sdhci_id_table),
> +	},
> +	.probe		= pic32_sdhci_probe,
> +	.remove		= pic32_sdhci_remove,
> +};
> +
> +module_platform_driver(pic32_sdhci_driver);
> +
> +MODULE_DESCRIPTION("Microchip PIC32 SDHCI driver");
> +MODULE_AUTHOR("Pistirica Sorin Andrei & Sandeep Sheriker");
> +MODULE_LICENSE("GPL v2");
> 

Re: [PATCH v5 12/14] mmc: sdhci-pic32: Add PIC32 SDHCI host controller driver

[Ulf Hansson]

+ Adrian

On 14 January 2016 at 02:15, Joshua Henderson
<joshua.henderson@microchip.com> wrote:
> From: Andrei Pistirica <andrei.pistirica@microchip.com>
>
> This driver supports the SDHCI host controller found on a PIC32.
>
> Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com>
> Signed-off-by: Joshua Henderson <joshua.henderson@microchip.com>
> Cc: Ralf Baechle <ralf@linux-mips.org>

I have queued this up for next via my mmc tree.

Adrian, please tell me if you have any objections.

Thanks and kind regards!
Uffe

> ---
> Changes since v4: None
> Changes since v3: None
> Changes since v2:
>         - Use 'sdhci_pltfm_*' instead of 'sdhci_*_host' and other cleanup
> Changes since v1:
>         - Be consistent and use only "SDHCI" when referring to SD host
>           controller
>         - Remove unnecessary PIC32 sdhci_ops min clock function.
>         - Drop usage of piomode and no-1-8-v DT properties
>         - Formatting
>         - Fix use of devm_iounmap
>         - Address code comment
> ---
>  drivers/mmc/host/Kconfig       |   11 ++
>  drivers/mmc/host/Makefile      |    1 +
>  drivers/mmc/host/sdhci-pic32.c |  257 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 269 insertions(+)
>  create mode 100644 drivers/mmc/host/sdhci-pic32.c
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 1dee533..c6a8916 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -785,3 +785,14 @@ config MMC_MTK
>           If you have a machine with a integrated SD/MMC card reader, say Y or M here.
>           This is needed if support for any SD/SDIO/MMC devices is required.
>           If unsure, say N.
> +
> +config MMC_SDHCI_MICROCHIP_PIC32
> +        tristate "Microchip PIC32MZDA SDHCI support"
> +        depends on MMC_SDHCI && PIC32MZDA && MMC_SDHCI_PLTFM
> +        help
> +          This selects the Secure Digital Host Controller Interface (SDHCI)
> +          for PIC32MZDA platform.
> +
> +          If you have a controller with this interface, say Y or M here.
> +
> +          If unsure, say N.
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 3595f83..af918d2 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -75,6 +75,7 @@ obj-$(CONFIG_MMC_SDHCI_BCM2835)               += sdhci-bcm2835.o
>  obj-$(CONFIG_MMC_SDHCI_IPROC)          += sdhci-iproc.o
>  obj-$(CONFIG_MMC_SDHCI_MSM)            += sdhci-msm.o
>  obj-$(CONFIG_MMC_SDHCI_ST)             += sdhci-st.o
> +obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32)        += sdhci-pic32.o
>
>  ifeq ($(CONFIG_CB710_DEBUG),y)
>         CFLAGS-cb710-mmc        += -DDEBUG
> diff --git a/drivers/mmc/host/sdhci-pic32.c b/drivers/mmc/host/sdhci-pic32.c
> new file mode 100644
> index 0000000..059df70
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-pic32.c
> @@ -0,0 +1,257 @@
> +/*
> + * Support of SDHCI platform devices for Microchip PIC32.
> + *
> + * Copyright (C) 2015 Microchip
> + * Andrei Pistirica, Paul Thacker
> + *
> + * Inspired by sdhci-pltfm.c
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/highmem.h>
> +#include <linux/module.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm.h>
> +#include <linux/slab.h>
> +#include <linux/mmc/host.h>
> +#include <linux/io.h>
> +#include "sdhci.h"
> +#include "sdhci-pltfm.h"
> +#include <linux/platform_data/sdhci-pic32.h>
> +
> +#define SDH_SHARED_BUS_CTRL            0x000000E0
> +#define SDH_SHARED_BUS_NR_CLK_PINS_MASK        0x7
> +#define SDH_SHARED_BUS_NR_IRQ_PINS_MASK        0x30
> +#define SDH_SHARED_BUS_CLK_PINS                0x10
> +#define SDH_SHARED_BUS_IRQ_PINS                0x14
> +#define SDH_CAPS_SDH_SLOT_TYPE_MASK    0xC0000000
> +#define SDH_SLOT_TYPE_REMOVABLE                0x0
> +#define SDH_SLOT_TYPE_EMBEDDED         0x1
> +#define SDH_SLOT_TYPE_SHARED_BUS       0x2
> +#define SDHCI_CTRL_CDSSEL              0x80
> +#define SDHCI_CTRL_CDTLVL              0x40
> +
> +#define ADMA_FIFO_RD_THSHLD    512
> +#define ADMA_FIFO_WR_THSHLD    512
> +
> +struct pic32_sdhci_priv {
> +       struct platform_device  *pdev;
> +       struct clk *sys_clk;
> +       struct clk *base_clk;
> +};
> +
> +static unsigned int pic32_sdhci_get_max_clock(struct sdhci_host *host)
> +{
> +       struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
> +
> +       return clk_get_rate(sdhci_pdata->base_clk);
> +}
> +
> +static void pic32_sdhci_set_bus_width(struct sdhci_host *host, int width)
> +{
> +       u8 ctrl;
> +
> +       ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> +       if (width == MMC_BUS_WIDTH_8) {
> +               ctrl &= ~SDHCI_CTRL_4BITBUS;
> +               if (host->version >= SDHCI_SPEC_300)
> +                       ctrl |= SDHCI_CTRL_8BITBUS;
> +       } else {
> +               if (host->version >= SDHCI_SPEC_300)
> +                       ctrl &= ~SDHCI_CTRL_8BITBUS;
> +               if (width == MMC_BUS_WIDTH_4)
> +                       ctrl |= SDHCI_CTRL_4BITBUS;
> +               else
> +                       ctrl &= ~SDHCI_CTRL_4BITBUS;
> +       }
> +
> +       /* CD select and test bits must be set for errata workaround. */
> +       ctrl &= ~SDHCI_CTRL_CDTLVL;
> +       ctrl |= SDHCI_CTRL_CDSSEL;
> +       sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> +}
> +
> +static unsigned int pic32_sdhci_get_ro(struct sdhci_host *host)
> +{
> +       /*
> +        * The SDHCI_WRITE_PROTECT bit is unstable on current hardware so we
> +        * can't depend on its value in any way.
> +        */
> +       return 0;
> +}
> +
> +static const struct sdhci_ops pic32_sdhci_ops = {
> +       .get_max_clock = pic32_sdhci_get_max_clock,
> +       .set_clock = sdhci_set_clock,
> +       .set_bus_width = pic32_sdhci_set_bus_width,
> +       .reset = sdhci_reset,
> +       .set_uhs_signaling = sdhci_set_uhs_signaling,
> +       .get_ro = pic32_sdhci_get_ro,
> +};
> +
> +static struct sdhci_pltfm_data sdhci_pic32_pdata = {
> +       .ops = &pic32_sdhci_ops,
> +       .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
> +       .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
> +};
> +
> +static void pic32_sdhci_shared_bus(struct platform_device *pdev)
> +{
> +       struct sdhci_host *host = platform_get_drvdata(pdev);
> +       u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL);
> +       u32 clk_pins = (bus & SDH_SHARED_BUS_NR_CLK_PINS_MASK) >> 0;
> +       u32 irq_pins = (bus & SDH_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4;
> +
> +       /* select first clock */
> +       if (clk_pins & 1)
> +               bus |= (1 << SDH_SHARED_BUS_CLK_PINS);
> +
> +       /* select first interrupt */
> +       if (irq_pins & 1)
> +               bus |= (1 << SDH_SHARED_BUS_IRQ_PINS);
> +
> +       writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL);
> +}
> +
> +static int pic32_sdhci_probe_platform(struct platform_device *pdev,
> +                                     struct pic32_sdhci_priv *pdata)
> +{
> +       int ret = 0;
> +       u32 caps_slot_type;
> +       struct sdhci_host *host = platform_get_drvdata(pdev);
> +
> +       /* Check card slot connected on shared bus. */
> +       host->caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
> +       caps_slot_type = (host->caps & SDH_CAPS_SDH_SLOT_TYPE_MASK) >> 30;
> +       if (caps_slot_type == SDH_SLOT_TYPE_SHARED_BUS)
> +               pic32_sdhci_shared_bus(pdev);
> +
> +       return ret;
> +}
> +
> +static int pic32_sdhci_probe(struct platform_device *pdev)
> +{
> +       struct sdhci_host *host;
> +       struct sdhci_pltfm_host *pltfm_host;
> +       struct pic32_sdhci_priv *sdhci_pdata;
> +       struct pic32_sdhci_platform_data *plat_data;
> +       int ret;
> +
> +       host = sdhci_pltfm_init(pdev, &sdhci_pic32_pdata,
> +                               sizeof(struct pic32_sdhci_priv));
> +       if (IS_ERR(host)) {
> +               ret = PTR_ERR(host);
> +               goto err;
> +       }
> +
> +       pltfm_host = sdhci_priv(host);
> +       sdhci_pdata = sdhci_pltfm_priv(pltfm_host);
> +
> +       plat_data = pdev->dev.platform_data;
> +       if (plat_data && plat_data->setup_dma) {
> +               ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD,
> +                                          ADMA_FIFO_WR_THSHLD);
> +               if (ret)
> +                       goto err_host;
> +       }
> +
> +       sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk");
> +       if (IS_ERR(sdhci_pdata->sys_clk)) {
> +               ret = PTR_ERR(sdhci_pdata->sys_clk);
> +               dev_err(&pdev->dev, "Error getting clock\n");
> +               goto err_host;
> +       }
> +
> +       ret = clk_prepare_enable(sdhci_pdata->sys_clk);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Error enabling clock\n");
> +               goto err_host;
> +       }
> +
> +       sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk");
> +       if (IS_ERR(sdhci_pdata->base_clk)) {
> +               ret = PTR_ERR(sdhci_pdata->base_clk);
> +               dev_err(&pdev->dev, "Error getting clock\n");
> +               goto err_sys_clk;
> +       }
> +
> +       ret = clk_prepare_enable(sdhci_pdata->base_clk);
> +       if (ret) {
> +               dev_err(&pdev->dev, "Error enabling clock\n");
> +               goto err_base_clk;
> +       }
> +
> +       ret = mmc_of_parse(host->mmc);
> +       if (ret)
> +               goto err_base_clk;
> +
> +       ret = pic32_sdhci_probe_platform(pdev, sdhci_pdata);
> +       if (ret) {
> +               dev_err(&pdev->dev, "failed to probe platform!\n");
> +               goto err_base_clk;
> +       }
> +
> +       ret = sdhci_add_host(host);
> +       if (ret) {
> +               dev_err(&pdev->dev, "error adding host\n");
> +               goto err_base_clk;
> +       }
> +
> +       dev_info(&pdev->dev, "Successfully added sdhci host\n");
> +       return 0;
> +
> +err_base_clk:
> +       clk_disable_unprepare(sdhci_pdata->base_clk);
> +err_sys_clk:
> +       clk_disable_unprepare(sdhci_pdata->sys_clk);
> +err_host:
> +       sdhci_pltfm_free(pdev);
> +err:
> +       dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret);
> +       return ret;
> +}
> +
> +static int pic32_sdhci_remove(struct platform_device *pdev)
> +{
> +       struct sdhci_host *host = platform_get_drvdata(pdev);
> +       struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host);
> +       u32 scratch;
> +
> +       scratch = readl(host->ioaddr + SDHCI_INT_STATUS);
> +       sdhci_remove_host(host, scratch == (u32)~0);
> +       clk_disable_unprepare(sdhci_pdata->base_clk);
> +       clk_disable_unprepare(sdhci_pdata->sys_clk);
> +       sdhci_pltfm_free(pdev);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id pic32_sdhci_id_table[] = {
> +       { .compatible = "microchip,pic32mzda-sdhci" },
> +       {}
> +};
> +MODULE_DEVICE_TABLE(of, pic32_sdhci_id_table);
> +
> +static struct platform_driver pic32_sdhci_driver = {
> +       .driver = {
> +               .name   = "pic32-sdhci",
> +               .owner  = THIS_MODULE,
> +               .of_match_table = of_match_ptr(pic32_sdhci_id_table),
> +       },
> +       .probe          = pic32_sdhci_probe,
> +       .remove         = pic32_sdhci_remove,
> +};
> +
> +module_platform_driver(pic32_sdhci_driver);
> +
> +MODULE_DESCRIPTION("Microchip PIC32 SDHCI driver");
> +MODULE_AUTHOR("Pistirica Sorin Andrei & Sandeep Sheriker");
> +MODULE_LICENSE("GPL v2");
> --
> 1.7.9.5
>