From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hans de Goede Subject: Re: [PATCH 0/3] mmc: sunxi: Support eMMC DDR modes Date: Sun, 31 Jan 2016 10:40:21 +0100 Message-ID: <56ADD685.1080006@redhat.com> References: <1454088108-2332-1-git-send-email-wens@csie.org> Reply-To: hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Return-path: In-Reply-To: <1454088108-2332-1-git-send-email-wens-jdAy2FN1RRM@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Chen-Yu Tsai , Ulf Hansson , Maxime Ripard Cc: linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: linux-mmc@vger.kernel.org Hi, On 01/29/2016 06:21 PM, Chen-Yu Tsai wrote: > Hi everyone, > > This was "mmc: sunxi: Support vqmmc regulator and eMMC DDR modes". vqmmc > support and DT patches were merged even though it was an RFC series, to > my suprise. > > These are the remaining patches that add eMMC HS-DDR support to sunxi. > > Patch 1 adds timing delays for MMC_DDR52 mode. > > Patch 2 adds support for 8 bit eMMC DDR52 mode. Under this mode, the > controller must run at twice the card clock, and different timing delays > are needed. > > Patch 3 enables eMMC HS-DDR for sunxi-mmc. All 3 patches look good to me: Reviewed-by: Hans de Goede Regards, Hans