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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b03ab857474sm1508366066b.89.2025.09.05.04.14.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Sep 2025 04:14:32 -0700 (PDT) Message-ID: <57ae28ea-85fd-4f8b-8e74-1efba33f0cd2@oss.qualcomm.com> Date: Fri, 5 Sep 2025 13:14:29 +0200 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration To: Dmitry Baryshkov Cc: Wasim Nazir , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Richard Cochran , kernel@oss.qualcomm.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, Monish Chunara References: <20250826-lemans-evk-bu-v1-0-08016e0d3ce5@oss.qualcomm.com> <20250826-lemans-evk-bu-v1-2-08016e0d3ce5@oss.qualcomm.com> <3b691f3a-633c-4a7f-bc38-a9c464d83fe1@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAzOCBTYWx0ZWRfXyicbjMEhkdwV TTfNfJRWnHcTp5q9VeNcplUG1q9QQj9/FrJkF5Ug4DSqon4iR1vGEwvCoHKfC9Nf1x8t5spnjfu V8MjgdVs3T6uz3SWEVxpaxdGpli9egjptFAKRVYa/Lh3nxnhTFjJv8iL+G1gtIgJSKi1HHKBsgz 0KZurDGSpjBonx3a0tOPWKubk45ASLmpO+eTzCbOv5ySC4bydxKGeoAUSyO5W1mMQRzETJVRplG JnLGl8DhjqjAsuYUFBKTZCPiKVQDF924qKC1TF+teQJjHMJW7w2I3HNiIntU4hKP4oDizwEl+QF QO6jb69sheNfTUBsRwh28i4akue7Zf/be1Tozz84ZIN8ZxmahrnqLFKl4fSAkvq3/kZHEvmi8Ol qxiDhVw+ X-Proofpoint-ORIG-GUID: orZSg0PF3w2yeOhKee9a3xgoKYdQ4a18 X-Proofpoint-GUID: orZSg0PF3w2yeOhKee9a3xgoKYdQ4a18 X-Authority-Analysis: v=2.4 cv=U7iSDfru c=1 sm=1 tr=0 ts=68bac61b cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=HgT1ff4I_b0h3GnEaV4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-05_03,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300038 On 9/4/25 7:32 PM, Dmitry Baryshkov wrote: > On Thu, Sep 04, 2025 at 04:34:05PM +0200, Konrad Dybcio wrote: >> On 9/4/25 3:35 PM, Dmitry Baryshkov wrote: >>> On Wed, Sep 03, 2025 at 09:58:33PM +0530, Wasim Nazir wrote: >>>> On Wed, Sep 03, 2025 at 06:12:59PM +0200, Konrad Dybcio wrote: >>>>> On 8/27/25 3:20 AM, Dmitry Baryshkov wrote: >>>>>> On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote: >>>>>>> From: Monish Chunara >>>>>>> >>>>>>> Introduce the SDHC v5 controller node for the Lemans platform. >>>>>>> This controller supports either eMMC or SD-card, but only one >>>>>>> can be active at a time. SD-card is the preferred configuration >>>>>>> on Lemans targets, so describe this controller. >>>>>>> >>>>>>> Define the SDC interface pins including clk, cmd, and data lines >>>>>>> to enable proper communication with the SDHC controller. >>>>>>> >>>>>>> Signed-off-by: Monish Chunara >>>>>>> Co-developed-by: Wasim Nazir >>>>>>> Signed-off-by: Wasim Nazir >>>>>>> --- >>>>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++ >>>>>>> 1 file changed, 70 insertions(+) >>>>>>> >>>>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>>> index 99a566b42ef2..a5a3cdba47f3 100644 >>>>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >>>>>>> @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint { >>>>>>> }; >>>>>>> }; >>>>>>> >>>>>>> + sdhc: mmc@87c4000 { >>>>>>> + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; >>>>>>> + reg = <0x0 0x087c4000 0x0 0x1000>; >>>>>>> + >>>>>>> + interrupts = , >>>>>>> + ; >>>>>>> + interrupt-names = "hc_irq", "pwr_irq"; >>>>>>> + >>>>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, >>>>>>> + <&gcc GCC_SDCC1_APPS_CLK>; >>>>>>> + clock-names = "iface", "core"; >>>>>>> + >>>>>>> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>, >>>>>>> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>; >>>>>>> + interconnect-names = "sdhc-ddr", "cpu-sdhc"; >>>>>>> + >>>>>>> + iommus = <&apps_smmu 0x0 0x0>; >>>>>>> + dma-coherent; >>>>>>> + >>>>>>> + resets = <&gcc GCC_SDCC1_BCR>; >>>>>>> + >>>>>>> + no-sdio; >>>>>>> + no-mmc; >>>>>>> + bus-width = <4>; >>>>>> >>>>>> This is the board configuration, it should be defined in the EVK DTS. >>>>> >>>>> Unless the controller is actually incapable of doing non-SDCards >>>>> >>>>> But from the limited information I can find, this one should be able >>>>> to do both >>>>> >>>> >>>> It’s doable, but the bus width differs when this controller is used for >>>> eMMC, which is supported on the Mezz board. So, it’s cleaner to define >>>> only what’s needed for each specific usecase on the board. >>> >>> `git grep no-sdio arch/arm64/boot/dts/qcom/` shows that we have those >>> properties inside the board DT. I don't see a reason to deviate. >> >> Just to make sure we're clear >> >> I want the author to keep bus-width in SoC dt and move the other >> properties to the board dt > > I think bus-width is also a property of the board. In the end, it's a > question of schematics whether we route 1 wire or all 4 wires. git-log > shows that bus-width is being sent in both files (and probalby we should > sort that out). Actually this is the controller capability, so if it can do 8, it should be 8 and the MMC core will do whatever it pleases (the not-super-sure docs that I have say 8 for this platform) Konrad