From: Mason <slash.tmp@free.fr>
To: linux-mmc <linux-mmc@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Rameshwar Sahu <rsahu@apm.com>,
Suman Tripathi <stripathi@apm.com>,
Heiko Stuebner <heiko@sntech.de>,
Shawn Lin <shawn.lin@rock-chips.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Jisheng Zhang <jszhang@marvell.com>,
Russell King <linux@arm.linux.org.uk>,
Anton Vorontsov <anton@enomsg.org>,
Michal Simek <michal.simek@xilinx.com>,
Soren Brinkmann <soren.brinkmann@xilinx.com>,
Linus Walleij <linus.walleij@linaro.org>,
P L Sai Krishna <lakshmis@xilinx.com>,
Zach Brown <zach.brown@ni.com>,
Sebastian Frias <sf84@laposte.net>, Arnd Bergmann <arnd@arndb.de>,
Suneel Garapati <suneel.garapati@xilinx.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Michal Simek <monstr@monstr.eu>,
Douglas Anderson <dianders@chromium.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
Xiaobo Xie <x.xie@freescale>
Subject: Re: arasan,sdhci.txt "compatibility" DT binding
Date: Thu, 1 Dec 2016 13:29:26 +0100 [thread overview]
Message-ID: <584017A6.3000301@free.fr> (raw)
In-Reply-To: <f64ea0f8-31be-c5b5-3a43-a30abd8aec30@rock-chips.com>
On 01/12/2016 05:09, Shawn Lin wrote:
> On 2016/11/28 23:44, Mason wrote:
>
>> Shawn Lin, could you take a look below and tell me exactly
>> which IP core(s) Rockchip is using in its SoCs?
>
> From the Host Controller version register (0xfe)
> bit[7:0]: 0x2 : specification version number is 3.00
> bit[15:8]: 0x10: Vendor version number is 1.0
>
> Command Queueing version register (0x200)
> bit[11:8]: 0x5 eMMC Major version number
> bit[7:4]: 0x1 eMMC manor version number
> bit[3:0]: 0x0 eMMC version suffix
>
> User guide "eMMC 5.1/SD3.0/SDIO3.0 Host Controller"
> Revision number: 1.14
> Released on Dec. 2014
Wow! Yet another HW revision I wasn't aware of :-)
For the record, I think the 0x200 register was introduced fairly
recently, as it's not documented in any of the user guides I have
access to.
To summarize the situation, Arasan has made (at least) the
following versions of the HW block:
SD_2.0_SDIO_2.0__MMC_3.31_Host_Controller
SD_3.0_SDIO_3.0_eMMC_4.4__Host_Controller
SD_3.0_SDIO_3.0_eMMC_4.41_Host_Controller
SD_3.0_SDIO_3.0_eMMC_4.5__Host_Controller
SD_3.0_SDIO_3.0_eMMC_4.51_Host_Controller
SD_3.0_SDIO_3.0_eMMC_5.1__Host Controller
SD_4.1_SDIO_4.1_eMMC_4.51_Host_Controller
SD_4.1_SDIO_4.1_eMMC_5.1__Host_Controller
Xilinx = "arasan,sdhci-8.9a" compat string
SD2.0 / SDIO2.0 / MMC3.31 (in Zynq)
SD3.0 / SDIO3.0 / eMMC4.51 (in ZynqMP)
Vendor version 0x89 (Zynq, from 8.9a) and 0x10 (ZynqMP)
Sigma = no compat string yet
SD3.0 / SDIO3.0 / eMMC4.4 (in SMP87xx)
Vendor version 0x99 (not related to document revision)
APM = "arasan,sdhci-4.9a"
SD3.0 / SDIO3.0 / eMMC4.41
Vendor version unknown
Rockchip = "arasan,sdhci-5.1"
SD3.0 / SDIO3.0 / eMMC 5.1
Vendor version 0x10
Conclusion, it doesn't look like the "Vendor version" field
contains dependable information, considering the duplicate
0x10 in different HW revisions.
Regards.
prev parent reply other threads:[~2016-12-01 12:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-02 9:49 arasan,sdhci.txt "compatibility" DT binding Mason
2016-02-03 2:33 ` Shawn Lin
2016-02-03 7:20 ` Michal Simek
2016-02-03 8:31 ` Mason
2016-02-03 9:58 ` Michal Simek
2016-02-03 15:21 ` Sören Brinkmann
2016-02-03 15:33 ` Mason
2016-11-18 10:37 ` Mason
2016-11-18 10:49 ` Rameshwar Sahu
2016-11-18 12:42 ` Mason
2016-11-18 13:22 ` Michal Simek
2016-11-28 15:44 ` Mason
2016-11-28 16:15 ` Arnd Bergmann
2016-11-28 16:52 ` Mason
2016-11-29 7:29 ` Rameshwar Sahu
2016-11-30 10:51 ` Sebastian Frias
2016-11-30 13:17 ` Michal Simek
2016-11-28 16:23 ` Sebastian Frias
2016-12-01 4:09 ` Shawn Lin
2016-12-01 12:29 ` Mason [this message]
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