From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Axe Yang <axe.yang@mediatek.com>,
Chaotian Jing <chaotian.jing@mediatek.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Wenbin Mei <wenbin.mei@mediatek.com>
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v4 2/2] mmc: mediatek: extend number of tuning steps
Date: Thu, 7 Dec 2023 13:37:57 +0100 [thread overview]
Message-ID: <6c7c65a1-1398-43fc-8036-d901e8bc0934@collabora.com> (raw)
In-Reply-To: <20231207063535.29546-3-axe.yang@mediatek.com>
Il 07/12/23 07:35, Axe Yang ha scritto:
> Previously, during the MSDC calibration process, a full clock cycle
> actually not be covered, which in some cases didn't yield the best
> results and could cause CRC errors. This problem is particularly
> evident when MSDC is used as an SDIO host. In fact, MSDC support
> tuning up to a maximum of 64 steps, but by default, the step number
> is 32. By increase the tuning step, we are more likely to cover more
> parts of a clock cycle, and get better calibration result.
>
> To illustrate, when tuning 32 steps, if the obtained window has a hole
> near the middle, like this: 0xffc07ff (hex), then the selected delay
> will be the 6 (counting from right to left).
>
> (32 <- 1)
> 1111 1111 1100 0000 0000 0111 11(1)1 1111
>
> However, if we tune 64 steps, the window obtained may look like this:
> 0xfffffffffffc07ff. The final selected delay will be 44, which is
> safer as it is further away from the hole:
>
> (64 <- 1)
> 1111 ... (1)111 1111 1111 1111 1111 1100 0000 0000 0111 1111 1111
>
> In this case, delay 6 selected through 32 steps tuning is obviously
> not optimal, and this delay is closer to the hole, using it would
> easily cause CRC problems.
>
> As per mesaurements taken on mediatek SoC platform, the tuning phase
> will take:
> eMMC - 32 steps: ~3ms
> - 64 steps: ~6ms
> SDIO - 32 steps: ~4ms
> - 64 steos: ~7ms
> Tuning more steps won't prolong boot times by any meaningful amount
> of time, so for SD/SDIO the default tuning steps will be adjust to
> 64. But for eMMC, it is still preferred to use 32 steps tuning as
> otherwise there would be performance lose when accessing the RPMB
> partition(requiring retuning each time).
>
> You can configure property "mediatek,tuning-step" in MSDC dts node
> to adjust the step number.
>
> Signed-off-by: Axe Yang <axe.yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
next prev parent reply other threads:[~2023-12-07 12:38 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 6:35 [PATCH v4 0/2] mmc: mediatek: add support for 64-steps tuning Axe Yang
2023-12-07 6:35 ` [PATCH v4 1/2] dt-bindings: mmc: mtk-sd: add tuning steps related property Axe Yang
2023-12-07 12:37 ` AngeloGioacchino Del Regno
2023-12-07 6:35 ` [PATCH v4 2/2] mmc: mediatek: extend number of tuning steps Axe Yang
2023-12-07 12:37 ` AngeloGioacchino Del Regno [this message]
2023-12-07 14:16 ` [PATCH v4 0/2] mmc: mediatek: add support for 64-steps tuning Ulf Hansson
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