From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kevin Hilman Subject: Re: [PATCH 2/3] mmc: meson-gx: add ddr-access-quirk Date: Mon, 13 May 2019 10:47:45 -0700 Message-ID: <7hd0kmckla.fsf@baylibre.com> References: <20190513091548.16674-1-narmstrong@baylibre.com> <20190513091548.16674-3-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20190513091548.16674-3-narmstrong@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org To: ulf.hansson@linaro.org Cc: baylibre-upstreaming@groups.io, Neil Armstrong , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-Id: linux-mmc@vger.kernel.org Neil Armstrong writes: > On the Amlogic G12A SoC family, (only) the SDIO controller fails to access > the data from DDR, leading to a broken controller. > > But each MMC controller has 1,5KiB of SRAM after the registers, that can > be used as bounce buffer to avoid direct DDR access from the integrated > DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized). > > The quirk is to disable the chained descriptor for this controller, and > use this SRAM memory zone as buffer for the bounce buffer fallback mode. > > The performance hit hasn't been evaluated, but the fix has been tested > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed > at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock. > > Signed-off-by: Neil Armstrong Reviewed-by: Kevin Hilman