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* [PATCH 1/1] mmc: sdhci-pci-o2micro Add SeaBird SeaEagle SD3 support
@ 2014-04-18  7:11 Peter Guo
  2014-04-18 11:55 ` Chris Ball
  0 siblings, 1 reply; 2+ messages in thread
From: Peter Guo @ 2014-04-18  7:11 UTC (permalink / raw)
  To: linux-mmc@vger.kernel.org; +Cc: Chris Ball, Ulf Hansson, Adam Lee, Samuel Guan

Add O2Micro/BayHubTech chip 8520 subversion B1 SD3.0 support.
Add O2Micro/BayHubTech chip 8620 and 8621 SD3.0 support
Enable Led function of 8520 chip.

Signed-off-by: peter.guo <peter.guo@bayhubtech.com>
---
 drivers/mmc/host/sdhci-pci-o2micro.c |   59 +++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index f49666b..82954ce 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -21,6 +21,42 @@
 #include "sdhci-pci.h"
 #include "sdhci-pci-o2micro.h"
 
+static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
+{
+	u32 scratch_32;
+	pci_read_config_dword(chip->pdev,
+			O2_SD_PLL_SETTING, &scratch_32);
+
+	scratch_32 &= 0x0000FFFF;
+	scratch_32 |= value;
+
+	pci_write_config_dword(chip->pdev,
+			O2_SD_PLL_SETTING, scratch_32);
+}
+static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
+{
+	int ret;
+	u32 scratch_32;
+
+	/* Set led of SD host */
+	ret = pci_read_config_dword(chip->pdev,
+			O2_SD_FUNC_REG0, &scratch_32);
+	if (ret)
+		return;
+	scratch_32 &= ~(1<<13);
+	pci_write_config_dword(chip->pdev,
+			O2_SD_FUNC_REG0, scratch_32);
+
+	ret = pci_read_config_dword(chip->pdev,
+			O2_SD_TEST_REG, &scratch_32);
+	if (ret)
+		return;
+	scratch_32 |= 0x40;
+	pci_write_config_dword(chip->pdev,
+			O2_SD_TEST_REG, scratch_32);
+
+}
+
 void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 {
 	u32 scratch_32;
@@ -215,6 +251,25 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 
 		scratch &= 0x7f;
 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
+		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
+			ret = pci_read_config_dword(chip->pdev,
+						O2_SD_FUNC_REG0, &scratch_32);
+			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
+			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
+				scratch_32 = 0x2c280000;
+				o2_pci_set_baseclk(chip, scratch_32);
+				ret = pci_read_config_dword(chip->pdev,
+						O2_SD_FUNC_REG4, &scratch_32);
+				scratch_32 |= BIT(22);
+				pci_write_config_dword(chip->pdev,
+					O2_SD_FUNC_REG4, scratch_32);
+
+				pci_write_config_byte(chip->pdev,
+					O2_SD_TUNING_CTRL, 0x44);
+				break;
+			}
+		}
+		o2_pci_led_enable(chip);
 
 		/* Set timeout CLK */
 		ret = pci_read_config_dword(chip->pdev,
@@ -276,7 +331,7 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 
 		ret = pci_read_config_dword(chip->pdev,
-					    O2_SD_FUNC_REG0, &scratch_32);
+					    O2_SD_PLL_SETTING, &scratch_32);
 
 		if ((scratch_32 & 0xff000000) == 0x01000000) {
 			scratch_32 &= 0x0000FFFF;
@@ -299,6 +354,8 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 					       O2_SD_FUNC_REG4, scratch_32);
 		}
 
+		pci_write_config_byte(chip->pdev,
+				O2_SD_TUNING_CTRL, 0x55);
 		/* Lock WP */
 		ret = pci_read_config_byte(chip->pdev,
 					   O2_SD_LOCK_WP, &scratch);
-- 
1.7.9.5


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH 1/1] mmc: sdhci-pci-o2micro Add SeaBird SeaEagle SD3 support
  2014-04-18  7:11 [PATCH 1/1] mmc: sdhci-pci-o2micro Add SeaBird SeaEagle SD3 support Peter Guo
@ 2014-04-18 11:55 ` Chris Ball
  0 siblings, 0 replies; 2+ messages in thread
From: Chris Ball @ 2014-04-18 11:55 UTC (permalink / raw)
  To: Peter Guo; +Cc: linux-mmc@vger.kernel.org, Ulf Hansson, Adam Lee, Samuel Guan

Hi Peter,

On Fri, Apr 18 2014, Peter Guo wrote:
> @@ -215,6 +251,25 @@ int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
>  
>  		scratch &= 0x7f;
>  		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
> +		if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
> +			ret = pci_read_config_dword(chip->pdev,
> +						O2_SD_FUNC_REG0, &scratch_32);
> +			scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
> +			if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
> +				scratch_32 = 0x2c280000;

Can we get a comment added to the code about what the purpose of the
writes below is, and why you're writing this particular value?

Please use a #defined constant for the value, too.

> +				o2_pci_set_baseclk(chip, scratch_32);
> +				ret = pci_read_config_dword(chip->pdev,
> +						O2_SD_FUNC_REG4, &scratch_32);
> +				scratch_32 |= BIT(22);

Same -- what is the purpose of the value you're reading, and what does
adding this bit to it achieve?

> +				pci_write_config_dword(chip->pdev,
> +					O2_SD_FUNC_REG4, scratch_32);

Thanks,

- Chris.
-- 
Chris Ball   <http://printf.net/>

^ permalink raw reply	[flat|nested] 2+ messages in thread

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