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From: Adrian Hunter <adrian.hunter@intel.com>
To: Prathamesh Shete <pshete@nvidia.com>,
	ulf.hansson@linaro.org, thierry.reding@gmail.com,
	jonathanh@nvidia.com, p.zabel@pengutronix.de,
	linux-mmc@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: anrao@nvidia.com, smangipudi@nvidia.com, kyarlagadda@nvidia.com
Subject: Re: [PATCH v3 2/4] mmc: sdhci-tegra: Add support to program MC stream ID
Date: Thu, 22 Sep 2022 14:37:05 +0300	[thread overview]
Message-ID: <8baa26d8-af6f-c7d2-a87a-a9803eb1f275@intel.com> (raw)
In-Reply-To: <20220920123752.21027-2-pshete@nvidia.com>

On 20/09/22 15:37, Prathamesh Shete wrote:
> SMMU clients are supposed to program stream ID from
> their respective address spaces instead of MC override.
> Define NVQUIRK_PROGRAM_STREAMID and use it to program
> SMMU stream ID from the SDMMC client address space.
> 
> Signed-off-by: Aniruddha TVS Rao <anrao@nvidia.com>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
>  drivers/mmc/host/sdhci-tegra.c | 35 ++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
> index a6c5bbae77b4..4d32b5bfc424 100644
> --- a/drivers/mmc/host/sdhci-tegra.c
> +++ b/drivers/mmc/host/sdhci-tegra.c
> @@ -25,6 +25,7 @@
>  #include <linux/mmc/slot-gpio.h>
>  #include <linux/gpio/consumer.h>
>  #include <linux/ktime.h>
> +#include <linux/iommu.h>
>  
>  #include <soc/tegra/common.h>
>  
> @@ -94,6 +95,8 @@
>  #define SDHCI_TEGRA_AUTO_CAL_STATUS			0x1ec
>  #define SDHCI_TEGRA_AUTO_CAL_ACTIVE			BIT(31)
>  
> +#define SDHCI_TEGRA_CIF2AXI_CTRL_0			0x1fc
> +
>  #define NVQUIRK_FORCE_SDHCI_SPEC_200			BIT(0)
>  #define NVQUIRK_ENABLE_BLOCK_GAP_DET			BIT(1)
>  #define NVQUIRK_ENABLE_SDHCI_SPEC_300			BIT(2)
> @@ -121,6 +124,7 @@
>  #define NVQUIRK_HAS_TMCLK				BIT(10)
>  
>  #define NVQUIRK_HAS_ANDROID_GPT_SECTOR			BIT(11)
> +#define NVQUIRK_PROGRAM_STREAMID			BIT(12)
>  
>  /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
>  #define SDHCI_TEGRA_CQE_BASE_ADDR			0xF000
> @@ -128,6 +132,8 @@
>  #define SDHCI_TEGRA_CQE_TRNS_MODE	(SDHCI_TRNS_MULTI | \
>  					 SDHCI_TRNS_BLK_CNT_EN | \
>  					 SDHCI_TRNS_DMA)
> +#define SDHCI_TEGRA_STREAMID_MASK			0xff
> +#define SDHCI_TEGRA_WRITE_STREAMID_SHIFT		0x8
>  
>  struct sdhci_tegra_soc_data {
>  	const struct sdhci_pltfm_data *pdata;
> @@ -177,6 +183,7 @@ struct sdhci_tegra {
>  	bool enable_hwcq;
>  	unsigned long curr_clk_rate;
>  	u8 tuned_tap_delay;
> +	u32 streamid;
>  };
>  
>  static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
> @@ -1564,6 +1571,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = {
>  		    NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
>  		    NVQUIRK_ENABLE_SDR50 |
>  		    NVQUIRK_ENABLE_SDR104 |
> +		    NVQUIRK_PROGRAM_STREAMID |
>  		    NVQUIRK_HAS_TMCLK,
>  	.min_tap_delay = 95,
>  	.max_tap_delay = 111,
> @@ -1636,6 +1644,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
>  	struct sdhci_host *host;
>  	struct sdhci_pltfm_host *pltfm_host;
>  	struct sdhci_tegra *tegra_host;
> +	struct iommu_fwspec *fwspec;
>  	struct clk *clk;
>  	int rc;
>  
> @@ -1775,6 +1784,23 @@ static int sdhci_tegra_probe(struct platform_device *pdev)
>  	if (rc)
>  		goto err_add_host;
>  
> +	/* Program MC streamID for DMA transfers */
> +	if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
> +		fwspec = dev_iommu_fwspec_get(&pdev->dev);
> +		if (fwspec == NULL) {
> +			dev_warn(mmc_dev(host->mmc),
> +				"iommu fwspec is NULL, continue without stream ID\n");
> +		} else {
> +			tegra_host->streamid = fwspec->ids[0] & 0xffff;

As the robot pointed out 'ids' does not necessarily exist.  Looking at
include/linux/iommu.h, it seems to depend on CONFIG_IOMMU_API

> +			tegra_sdhci_writel(host, (tegra_host->streamid &
> +						SDHCI_TEGRA_STREAMID_MASK) |
> +						((tegra_host->streamid <<
> +						SDHCI_TEGRA_WRITE_STREAMID_SHIFT)
> +						& SDHCI_TEGRA_STREAMID_MASK),
> +						SDHCI_TEGRA_CIF2AXI_CTRL_0);
> +		}
> +	}
> +
>  	return 0;
>  
>  err_add_host:
> @@ -1861,6 +1887,8 @@ static int sdhci_tegra_suspend(struct device *dev)
>  static int sdhci_tegra_resume(struct device *dev)
>  {
>  	struct sdhci_host *host = dev_get_drvdata(dev);
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
>  	int ret;
>  
>  	ret = mmc_gpio_set_cd_wake(host->mmc, false);
> @@ -1871,6 +1899,13 @@ static int sdhci_tegra_resume(struct device *dev)
>  	if (ret)
>  		return ret;
>  
> +	/* Re-program MC streamID for DMA transfers */
> +	if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
> +		tegra_sdhci_writel(host, tegra_host->streamid |
> +					(tegra_host->streamid << 8),
> +					SDHCI_TEGRA_CIF2AXI_CTRL_0);
> +	}
> +
>  	ret = sdhci_resume_host(host);
>  	if (ret)
>  		goto disable_clk;


  parent reply	other threads:[~2022-09-22 11:37 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-20 12:37 [PATCH v3 1/4] mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data Prathamesh Shete
2022-09-20 12:37 ` [PATCH v3 2/4] mmc: sdhci-tegra: Add support to program MC stream ID Prathamesh Shete
2022-09-22 10:02   ` kernel test robot
2022-09-22 11:37   ` Adrian Hunter [this message]
2022-09-20 12:37 ` [PATCH v3 3/4] mmc: sdhci-tegra: Issue CMD and DAT resets together Prathamesh Shete
2022-09-20 12:37 ` [PATCH v3 4/4] mmc: sdhci-tegra: Use actual clock rate for SW tuning correction Prathamesh Shete
2022-09-22 11:33   ` Adrian Hunter
2022-09-22 11:42 ` [PATCH v3 1/4] mmc: sdhci-tegra: Separate Tegra194 and Tegra234 SoC data Adrian Hunter
  -- strict thread matches above, loose matches on Subject: below --
2022-09-26  9:49 Prathamesh Shete
2022-09-26  9:49 ` [PATCH v3 2/4] mmc: sdhci-tegra: Add support to program MC stream ID Prathamesh Shete

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