[RFC V3 0/4] dw_mmc platform specific private data and SMU init

[RFC V3 0/4] dw_mmc platform specific private data and SMU init

[Yuvaraj Kumar C D]

changes from V2:
	1.dropped the bypass-smu quirk 
		mmc: dw_mmc: exynos: configure SMU in exynos5420.
	2.Changed the subject line for this patch
	  add a quirk for SMU -> configure SMU in exynos5420
	
	mmc: dw_mmc: exynos: configure SMU in exynos5420 
	was earlier 
	mmc: dw_mmc: exynos: add a quirk for SMU.

changes from V1:
	1.Added a new RFC patch 
		mmc: dw_mmc: socfpga: move socfpga private init
	2.Avoid code duplication in
		mmc: dw_mmc: exynos: add a quirk for SMU.

Yuvaraj Kumar C D (4):
  mmc: dw_mmc: exynos: move the exynos private init
  mmc: dw_mmc: socfpga: move socfpga private init
  mmc: dw_mmc: move the platform specific init call
  mmc: dw_mmc: exynos: configure SMU in exynos5420.

 drivers/mmc/host/dw_mmc-exynos.c  |   56 +++++++++++++++++++++++++++----------
 drivers/mmc/host/dw_mmc-pltfm.c   |    7 -----
 drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++---------
 drivers/mmc/host/dw_mmc.c         |    9 ++++++
 4 files changed, 65 insertions(+), 36 deletions(-)

-- 
1.7.9.5

[RFC V3 1/4] mmc: dw_mmc: exynos: move the exynos private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exynos_priv_init to do some actual platform
specific initialisation of SMU and etc.

changes since V2: none
changes since V1: none

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
---
 drivers/mmc/host/dw_mmc-exynos.c |   31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 9990f98..19c845b 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -72,22 +72,8 @@ static struct dw_mci_exynos_compatible {
 
 static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
-	struct dw_mci_exynos_priv_data *priv;
-	int idx;
-
-	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv) {
-		dev_err(host->dev, "mem alloc failed for private data\n");
-		return -ENOMEM;
-	}
-
-	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
-		if (of_device_is_compatible(host->dev->of_node,
-					exynos_compat[idx].compatible))
-			priv->ctrl_type = exynos_compat[idx].ctrl_type;
-	}
+	struct dw_mci_exynos_priv_data *priv = host->priv;
 
-	host->priv = priv;
 	return 0;
 }
 
@@ -177,12 +163,24 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 
 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 {
-	struct dw_mci_exynos_priv_data *priv = host->priv;
+	struct dw_mci_exynos_priv_data *priv;
 	struct device_node *np = host->dev->of_node;
 	u32 timing[2];
 	u32 div = 0;
+	int idx;
 	int ret;
 
+	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(host->dev, "mem alloc failed for private data\n");
+		return -ENOMEM;
+	}
+
+	for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
+		if (of_device_is_compatible(np, exynos_compat[idx].compatible))
+			priv->ctrl_type = exynos_compat[idx].ctrl_type;
+	}
+
 	of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
 	priv->ciu_div = div;
 
@@ -199,6 +197,7 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
 		return ret;
 
 	priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
+	host->priv = priv;
 	return 0;
 }
 
-- 
1.7.9.5

[RFC V3 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Yuvaraj Kumar C D]

Currently platform specific private data initialisation is done by
dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
separate platform specific device tree parser dw_mci_socfpga_parse_dt,
move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
We can use the dw_mci_socfpga_priv_init to do some actual platform
specific initialisation.

This patch is compile tested only.

changes since V2: none

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
---
 drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
index 14b5961..953f260 100644
--- a/drivers/mmc/host/dw_mmc-socfpga.c
+++ b/drivers/mmc/host/dw_mmc-socfpga.c
@@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
 
 static int dw_mci_socfpga_priv_init(struct dw_mci *host)
 {
-	struct dw_mci_socfpga_priv_data *priv;
-
-	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
-	if (!priv) {
-		dev_err(host->dev, "mem alloc failed for private data\n");
-		return -ENOMEM;
-	}
-
-	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
-	if (IS_ERR(priv->sysreg)) {
-		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
-		return PTR_ERR(priv->sysreg);
-	}
-	host->priv = priv;
 
 	return 0;
 }
@@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
 
 static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
 {
-	struct dw_mci_socfpga_priv_data *priv = host->priv;
+	struct dw_mci_socfpga_priv_data *priv;
 	struct device_node *np = host->dev->of_node;
 	u32 timing[2];
 	u32 div = 0;
 	int ret;
 
+	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		dev_err(host->dev, "mem alloc failed for private data\n");
+		return -ENOMEM;
+	}
+
+	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
+	if (IS_ERR(priv->sysreg)) {
+		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
+		return PTR_ERR(priv->sysreg);
+	}
+
 	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
 	if (ret)
 		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
@@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
 		return ret;
 
 	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+	host->priv = priv;
 	return 0;
 }
 
-- 
1.7.9.5

[RFC V3 3/4] mmc: dw_mmc: move the platform specific init call

[Yuvaraj Kumar C D]

Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.

changes since V2: none
changes since V1: none

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
---
 drivers/mmc/host/dw_mmc-pltfm.c |    7 -------
 drivers/mmc/host/dw_mmc.c       |    9 +++++++++
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index 2089752..5c49656 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -39,7 +39,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 {
 	struct dw_mci *host;
 	struct resource	*regs;
-	int ret;
 
 	host = devm_kzalloc(&pdev->dev, sizeof(struct dw_mci), GFP_KERNEL);
 	if (!host)
@@ -59,12 +58,6 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 	if (IS_ERR(host->regs))
 		return PTR_ERR(host->regs);
 
-	if (drv_data && drv_data->init) {
-		ret = drv_data->init(host);
-		if (ret)
-			return ret;
-	}
-
 	platform_set_drvdata(pdev, host);
 	return dw_mci_probe(host);
 }
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index beafb4c..0edec01 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2221,6 +2221,15 @@ int dw_mci_probe(struct dw_mci *host)
 		host->bus_hz = clk_get_rate(host->ciu_clk);
 	}
 
+	if (drv_data && drv_data->init) {
+		ret = drv_data->init(host);
+		if (ret) {
+			dev_err(host->dev,
+				"implementation specific init failed\n");
+			goto err_clk_ciu;
+		}
+	}
+
 	if (drv_data && drv_data->setup_clock) {
 		ret = drv_data->setup_clock(host);
 		if (ret) {
-- 
1.7.9.5

[RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar C D]

Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
SMU for exynos5420.

This patch is on top of the below patch by Doug Anderson.
mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT

changes since V2:
	1.Droppped the bypass-smu quirk.
	2.Changed the subject line for this patch
	  add a quirk for SMU -> configure SMU in exynos5420

changes since V1:
	1.avoid code duplication by calling dw_mci_exynos_priv_init in
	  resume path.

Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 19c845b..db28f10 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -35,6 +35,25 @@
 #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
 #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
 
+/* Block number in eMMC */
+#define DWMCI_BLOCK_NUM			0xFFFFFFFF
+
+#define SDMMC_EMMCP_BASE		0x1000
+#define SDMMC_MPSECURITY		(SDMMC_EMMCP_BASE + 0x0010)
+#define SDMMC_MPSBEGIN0			(SDMMC_EMMCP_BASE + 0x0200)
+#define SDMMC_MPSEND0			(SDMMC_EMMCP_BASE + 0x0204)
+#define SDMMC_MPSCTRL0			(SDMMC_EMMCP_BASE + 0x020C)
+
+/* SMU control bits */
+#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)
+#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)
+#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)
+#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)
+#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)
+#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)
+#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)
+#define DWMCI_MPSCTRL_VALID			BIT(0)
+
 /* Variations in Exynos specific dw-mshc controller */
 enum dw_mci_exynos_type {
 	DW_MCI_TYPE_EXYNOS4210,
@@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
 {
 	struct dw_mci_exynos_priv_data *priv = host->priv;
 
+	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
+		mci_writel(host, MPSBEGIN0, 0);
+		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
+		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
+			DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
+			DWMCI_MPSCTRL_VALID |
+			DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
+	}
+
 	return 0;
 }
 
@@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
 {
 	struct dw_mci *host = dev_get_drvdata(dev);
 
+	dw_mci_exynos_priv_init(host);
 	return dw_mci_resume(host);
 }
 
-- 
1.7.9.5

Re: [RFC V3 0/4] dw_mmc platform specific private data and SMU init

[Jaehoon Chung]

Hi Yuvaraj,

I have tested on Exynos4 series.
I didn't test for SMU feature. If Seungwon could test or review and confirm this patch,
then looks good to me.

With exynos4 series,
Tested-by: Jaehoon Chung <jh80.chung@samsung.com> 

Best Regards.
Jaehoon Chung

On 08/28/2013 09:08 PM, Yuvaraj Kumar C D wrote:
> changes from V2:
> 	1.dropped the bypass-smu quirk 
> 		mmc: dw_mmc: exynos: configure SMU in exynos5420.
> 	2.Changed the subject line for this patch
> 	  add a quirk for SMU -> configure SMU in exynos5420
> 	
> 	mmc: dw_mmc: exynos: configure SMU in exynos5420 
> 	was earlier 
> 	mmc: dw_mmc: exynos: add a quirk for SMU.
> 
> changes from V1:
> 	1.Added a new RFC patch 
> 		mmc: dw_mmc: socfpga: move socfpga private init
> 	2.Avoid code duplication in
> 		mmc: dw_mmc: exynos: add a quirk for SMU.
> 
> Yuvaraj Kumar C D (4):
>   mmc: dw_mmc: exynos: move the exynos private init
>   mmc: dw_mmc: socfpga: move socfpga private init
>   mmc: dw_mmc: move the platform specific init call
>   mmc: dw_mmc: exynos: configure SMU in exynos5420.
> 
>  drivers/mmc/host/dw_mmc-exynos.c  |   56 +++++++++++++++++++++++++++----------
>  drivers/mmc/host/dw_mmc-pltfm.c   |    7 -----
>  drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++---------
>  drivers/mmc/host/dw_mmc.c         |    9 ++++++
>  4 files changed, 65 insertions(+), 36 deletions(-)
> 

RE: [RFC V3 0/4] dw_mmc platform specific private data and SMU init

[Seungwon Jeon]

On Thursday, August 29, 2013, Jaehoon Chung wrote:
> Hi Yuvaraj,
> 
> I have tested on Exynos4 series.
> I didn't test for SMU feature. If Seungwon could test or review and confirm this patch,
> then looks good to me.
> 
> With exynos4 series,
> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>

Just now, this series looks good to me.
But direct access for SMU concerning (4/4, exynos: configure SMU in exynos5420') 
will be removed in driver before long.
I will sort your patches with the pending others.

Acked-by: Seungwon Jeon <tgih.jun@samsung.com>

Thanks,
Seungwon Jeon

> 
> Best Regards.
> Jaehoon Chung
> 
> On 08/28/2013 09:08 PM, Yuvaraj Kumar C D wrote:
> > changes from V2:
> > 	1.dropped the bypass-smu quirk
> > 		mmc: dw_mmc: exynos: configure SMU in exynos5420.
> > 	2.Changed the subject line for this patch
> > 	  add a quirk for SMU -> configure SMU in exynos5420
> >
> > 	mmc: dw_mmc: exynos: configure SMU in exynos5420
> > 	was earlier
> > 	mmc: dw_mmc: exynos: add a quirk for SMU.
> >
> > changes from V1:
> > 	1.Added a new RFC patch
> > 		mmc: dw_mmc: socfpga: move socfpga private init
> > 	2.Avoid code duplication in
> > 		mmc: dw_mmc: exynos: add a quirk for SMU.
> >
> > Yuvaraj Kumar C D (4):
> >   mmc: dw_mmc: exynos: move the exynos private init
> >   mmc: dw_mmc: socfpga: move socfpga private init
> >   mmc: dw_mmc: move the platform specific init call
> >   mmc: dw_mmc: exynos: configure SMU in exynos5420.
> >
> >  drivers/mmc/host/dw_mmc-exynos.c  |   56 +++++++++++++++++++++++++++----------
> >  drivers/mmc/host/dw_mmc-pltfm.c   |    7 -----
> >  drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++---------
> >  drivers/mmc/host/dw_mmc.c         |    9 ++++++
> >  4 files changed, 65 insertions(+), 36 deletions(-)
> >
> 
> --
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> the body of a message to majordomo@vger.kernel.org
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RE: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Seungwon Jeon]

On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> Exynos5420 Mobile Storage Host controller has Security Management Unit
> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
> SMU for exynos5420.
> 
> This patch is on top of the below patch by Doug Anderson.
> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> 
> changes since V2:
> 	1.Droppped the bypass-smu quirk.
> 	2.Changed the subject line for this patch
> 	  add a quirk for SMU -> configure SMU in exynos5420
> 
> changes since V1:
> 	1.avoid code duplication by calling dw_mci_exynos_priv_init in
> 	  resume path.
> 
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index 19c845b..db28f10 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -35,6 +35,25 @@
>  #define EXYNOS4210_FIXED_CIU_CLK_DIV	2
>  #define EXYNOS4412_FIXED_CIU_CLK_DIV	4
> 
> +/* Block number in eMMC */
> +#define DWMCI_BLOCK_NUM			0xFFFFFFFF
> +
> +#define SDMMC_EMMCP_BASE		0x1000
> +#define SDMMC_MPSECURITY		(SDMMC_EMMCP_BASE + 0x0010)
> +#define SDMMC_MPSBEGIN0			(SDMMC_EMMCP_BASE + 0x0200)
> +#define SDMMC_MPSEND0			(SDMMC_EMMCP_BASE + 0x0204)
> +#define SDMMC_MPSCTRL0			(SDMMC_EMMCP_BASE + 0x020C)
> +
> +/* SMU control bits */
> +#define DWMCI_MPSCTRL_SECURE_READ_BIT		BIT(7)
> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT		BIT(6)
> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT	BIT(5)
> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT	BIT(4)
> +#define DWMCI_MPSCTRL_USE_FUSE_KEY		BIT(3)
> +#define DWMCI_MPSCTRL_ECB_MODE			BIT(2)
> +#define DWMCI_MPSCTRL_ENCRYPTION		BIT(1)
> +#define DWMCI_MPSCTRL_VALID			BIT(0)
> +
>  /* Variations in Exynos specific dw-mshc controller */
>  enum dw_mci_exynos_type {
>  	DW_MCI_TYPE_EXYNOS4210,
> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>  {
>  	struct dw_mci_exynos_priv_data *priv = host->priv;
> 
> +	if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> +		mci_writel(host, MPSBEGIN0, 0);
> +		mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> +		mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
> +			DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> +			DWMCI_MPSCTRL_VALID |
> +			DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
Yuvaraj,

Just one thing to check.
ch#0 and #1 of three hosts are only valid for SMU control.
Did you consider #2 host?
It seems not.

Thanks,
Seungwon Jeon

> +	}
> +
>  	return 0;
>  }
> 
> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>  {
>  	struct dw_mci *host = dev_get_drvdata(dev);
> 
> +	dw_mci_exynos_priv_init(host);
>  	return dw_mci_resume(host);
>  }
> 
> --
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Alim Akhtar]

Hi Seungwon,

On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> SMU for exynos5420.
>>
>> This patch is on top of the below patch by Doug Anderson.
>> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>
>> changes since V2:
>>       1.Droppped the bypass-smu quirk.
>>       2.Changed the subject line for this patch
>>         add a quirk for SMU -> configure SMU in exynos5420
>>
>> changes since V1:
>>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>         resume path.
>>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index 19c845b..db28f10 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -35,6 +35,25 @@
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>
>> +/* Block number in eMMC */
>> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>> +
>> +#define SDMMC_EMMCP_BASE             0x1000
>> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>> +
>> +/* SMU control bits */
>> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>> +
>>  /* Variations in Exynos specific dw-mshc controller */
>>  enum dw_mci_exynos_type {
>>       DW_MCI_TYPE_EXYNOS4210,
>> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>>       struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> +             mci_writel(host, MPSBEGIN0, 0);
>> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> +                     DWMCI_MPSCTRL_VALID |
>> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> Yuvaraj,
>
> Just one thing to check.
> ch#0 and #1 of three hosts are only valid for SMU control.
> Did you consider #2 host?
> It seems not.
>

Only host#0 and host#1 has SMU (On exynos5420).
Host #2 does not contain SMU.

> Thanks,
> Seungwon Jeon
>
>> +     }
>> +
>>       return 0;
>>  }
>>
>> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>>  {
>>       struct dw_mci *host = dev_get_drvdata(dev);
>>
>> +     dw_mci_exynos_priv_init(host);
>>       return dw_mci_resume(host);
>>  }
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Regards,
Alim

Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar]

On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> SMU for exynos5420.
>>
>> This patch is on top of the below patch by Doug Anderson.
>> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>
>> changes since V2:
>>       1.Droppped the bypass-smu quirk.
>>       2.Changed the subject line for this patch
>>         add a quirk for SMU -> configure SMU in exynos5420
>>
>> changes since V1:
>>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>         resume path.
>>
>> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> ---
>>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> index 19c845b..db28f10 100644
>> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> @@ -35,6 +35,25 @@
>>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>
>> +/* Block number in eMMC */
>> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>> +
>> +#define SDMMC_EMMCP_BASE             0x1000
>> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>> +
>> +/* SMU control bits */
>> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>> +
>>  /* Variations in Exynos specific dw-mshc controller */
>>  enum dw_mci_exynos_type {
>>       DW_MCI_TYPE_EXYNOS4210,
>> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>  {
>>       struct dw_mci_exynos_priv_data *priv = host->priv;
>>
>> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> +             mci_writel(host, MPSBEGIN0, 0);
>> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> +                     DWMCI_MPSCTRL_VALID |
>> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> Yuvaraj,
>
> Just one thing to check.
> ch#0 and #1 of three hosts are only valid for SMU control.
> Did you consider #2 host?
> It seems not.
Yes.AFAIK, host#2 doesn't have SMU.
>
> Thanks,
> Seungwon Jeon
>
>> +     }
>> +
>>       return 0;
>>  }
>>
>> @@ -107,6 +135,7 @@ static int dw_mci_exynos_resume(struct device *dev)
>>  {
>>       struct dw_mci *host = dev_get_drvdata(dev);
>>
>> +     dw_mci_exynos_priv_init(host);
>>       return dw_mci_resume(host);
>>  }
>>
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

RE: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Seungwon Jeon]

On Thu, August 29, 2013, Alim Akhtar wrote:
> Hi Seungwon,
> 
> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
> >> SMU for exynos5420.
> >>
> >> This patch is on top of the below patch by Doug Anderson.
> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> >>
> >> changes since V2:
> >>       1.Droppped the bypass-smu quirk.
> >>       2.Changed the subject line for this patch
> >>         add a quirk for SMU -> configure SMU in exynos5420
> >>
> >> changes since V1:
> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
> >>         resume path.
> >>
> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> >> ---
> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
> >>  1 file changed, 29 insertions(+)
> >>
> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> >> index 19c845b..db28f10 100644
> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> >> @@ -35,6 +35,25 @@
> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> >>
> >> +/* Block number in eMMC */
> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> >> +
> >> +#define SDMMC_EMMCP_BASE             0x1000
> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
> >> +
> >> +/* SMU control bits */
> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> >> +
> >>  /* Variations in Exynos specific dw-mshc controller */
> >>  enum dw_mci_exynos_type {
> >>       DW_MCI_TYPE_EXYNOS4210,
> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
> >>  {
> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> >>
> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> >> +             mci_writel(host, MPSBEGIN0, 0);
> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> >> +                     DWMCI_MPSCTRL_VALID |
> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> > Yuvaraj,
> >
> > Just one thing to check.
> > ch#0 and #1 of three hosts are only valid for SMU control.
> > Did you consider #2 host?
> > It seems not.
> >
> 
> Only host#0 and host#1 has SMU (On exynos5420).
> Host #2 does not contain SMU.
Let me clear it.
I mean that current change allows for ch2 to access registers related to SMU,
even though ch2 doesn't actually has SMU. It's not valid IO area.

Thanks,
Seungwon Jeon

Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar]

On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> On Thu, August 29, 2013, Alim Akhtar wrote:
>> Hi Seungwon,
>>
>> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
>> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
>> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>> >> SMU for exynos5420.
>> >>
>> >> This patch is on top of the below patch by Doug Anderson.
>> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>> >>
>> >> changes since V2:
>> >>       1.Droppped the bypass-smu quirk.
>> >>       2.Changed the subject line for this patch
>> >>         add a quirk for SMU -> configure SMU in exynos5420
>> >>
>> >> changes since V1:
>> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>> >>         resume path.
>> >>
>> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>> >> ---
>> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>> >>  1 file changed, 29 insertions(+)
>> >>
>> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>> >> index 19c845b..db28f10 100644
>> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
>> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>> >> @@ -35,6 +35,25 @@
>> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>> >>
>> >> +/* Block number in eMMC */
>> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>> >> +
>> >> +#define SDMMC_EMMCP_BASE             0x1000
>> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>> >> +
>> >> +/* SMU control bits */
>> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>> >> +
>> >>  /* Variations in Exynos specific dw-mshc controller */
>> >>  enum dw_mci_exynos_type {
>> >>       DW_MCI_TYPE_EXYNOS4210,
>> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>> >>  {
>> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
>> >>
>> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>> >> +             mci_writel(host, MPSBEGIN0, 0);
>> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>> >> +                     DWMCI_MPSCTRL_VALID |
>> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>> > Yuvaraj,
>> >
>> > Just one thing to check.
>> > ch#0 and #1 of three hosts are only valid for SMU control.
>> > Did you consider #2 host?
>> > It seems not.
>> >
>>
>> Only host#0 and host#1 has SMU (On exynos5420).
>> Host #2 does not contain SMU.
> Let me clear it.
> I mean that current change allows for ch2 to access registers related to SMU,
> even though ch2 doesn't actually has SMU. It's not valid IO area.
No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
Below is the DT patch posted in another thread.
[1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.html
I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for host#2.

>
> Thanks,
> Seungwon Jeon
>

Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Yuvaraj Kumar]

On Thu, Aug 29, 2013 at 3:34 PM, Yuvaraj Kumar <yuvaraj.cd@gmail.com> wrote:
> On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
>> On Thu, August 29, 2013, Alim Akhtar wrote:
>>> Hi Seungwon,
>>>
>>> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
>>> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>>> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
>>> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
>>> >> SMU for exynos5420.
>>> >>
>>> >> This patch is on top of the below patch by Doug Anderson.
>>> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
>>> >>
>>> >> changes since V2:
>>> >>       1.Droppped the bypass-smu quirk.
>>> >>       2.Changed the subject line for this patch
>>> >>         add a quirk for SMU -> configure SMU in exynos5420
>>> >>
>>> >> changes since V1:
>>> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
>>> >>         resume path.
>>> >>
>>> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>>> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
>>> >> ---
>>> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
>>> >>  1 file changed, 29 insertions(+)
>>> >>
>>> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
>>> >> index 19c845b..db28f10 100644
>>> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
>>> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
>>> >> @@ -35,6 +35,25 @@
>>> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
>>> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
>>> >>
>>> >> +/* Block number in eMMC */
>>> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
>>> >> +
>>> >> +#define SDMMC_EMMCP_BASE             0x1000
>>> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
>>> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
>>> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
>>> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
>>> >> +
>>> >> +/* SMU control bits */
>>> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
>>> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
>>> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
>>> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
>>> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
>>> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
>>> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
>>> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
>>> >> +
>>> >>  /* Variations in Exynos specific dw-mshc controller */
>>> >>  enum dw_mci_exynos_type {
>>> >>       DW_MCI_TYPE_EXYNOS4210,
>>> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
>>> >>  {
>>> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
>>> >>
>>> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
>>> >> +             mci_writel(host, MPSBEGIN0, 0);
>>> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
>>> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
>>> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
>>> >> +                     DWMCI_MPSCTRL_VALID |
>>> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
>>> > Yuvaraj,
>>> >
>>> > Just one thing to check.
>>> > ch#0 and #1 of three hosts are only valid for SMU control.
>>> > Did you consider #2 host?
>>> > It seems not.
>>> >
>>>
>>> Only host#0 and host#1 has SMU (On exynos5420).
>>> Host #2 does not contain SMU.
>> Let me clear it.
>> I mean that current change allows for ch2 to access registers related to SMU,
>> even though ch2 doesn't actually has SMU. It's not valid IO area.
> No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
 Below is the DT patch posted in another thread.(Sorry,earlier link
was bit older).
[PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg22074.html
I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for host#2.
>
>>
>> Thanks,
>> Seungwon Jeon
>>

RE: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Seungwon Jeon]

Yuvaraj Kumar wrote:
> On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> > On Thu, August 29, 2013, Alim Akhtar wrote:
> >> Hi Seungwon,
> >>
> >> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon <tgih.jun@samsung.com> wrote:
> >> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> >> >> Exynos5420 Mobile Storage Host controller has Security Management Unit
> >> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
> >> >> SMU for exynos5420.
> >> >>
> >> >> This patch is on top of the below patch by Doug Anderson.
> >> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> >> >>
> >> >> changes since V2:
> >> >>       1.Droppped the bypass-smu quirk.
> >> >>       2.Changed the subject line for this patch
> >> >>         add a quirk for SMU -> configure SMU in exynos5420
> >> >>
> >> >> changes since V1:
> >> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init in
> >> >>         resume path.
> >> >>
> >> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> >> >> ---
> >> >>  drivers/mmc/host/dw_mmc-exynos.c |   29 +++++++++++++++++++++++++++++
> >> >>  1 file changed, 29 insertions(+)
> >> >>
> >> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> >> >> index 19c845b..db28f10 100644
> >> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> >> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> >> >> @@ -35,6 +35,25 @@
> >> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> >> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> >> >>
> >> >> +/* Block number in eMMC */
> >> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> >> >> +
> >> >> +#define SDMMC_EMMCP_BASE             0x1000
> >> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> >> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE + 0x0200)
> >> >> +#define SDMMC_MPSEND0                        (SDMMC_EMMCP_BASE + 0x0204)
> >> >> +#define SDMMC_MPSCTRL0                       (SDMMC_EMMCP_BASE + 0x020C)
> >> >> +
> >> >> +/* SMU control bits */
> >> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> >> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> >> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> >> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> >> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> >> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> >> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> >> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> >> >> +
> >> >>  /* Variations in Exynos specific dw-mshc controller */
> >> >>  enum dw_mci_exynos_type {
> >> >>       DW_MCI_TYPE_EXYNOS4210,
> >> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
> >> >>  {
> >> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> >> >>
> >> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> >> >> +             mci_writel(host, MPSBEGIN0, 0);
> >> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> >> >> +             mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT |
> >> >> +                     DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> >> >> +                     DWMCI_MPSCTRL_VALID |
> >> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> >> > Yuvaraj,
> >> >
> >> > Just one thing to check.
> >> > ch#0 and #1 of three hosts are only valid for SMU control.
> >> > Did you consider #2 host?
> >> > It seems not.
> >> >
> >>
> >> Only host#0 and host#1 has SMU (On exynos5420).
> >> Host #2 does not contain SMU.
> > Let me clear it.
> > I mean that current change allows for ch2 to access registers related to SMU,
> > even though ch2 doesn't actually has SMU. It's not valid IO area.
> No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
> Below is the DT patch posted in another thread.
> [1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.html
> I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for host#2.

Hmm. If we notice exynos5420's other newly added registers apart from SMU, 
it is difficult to say exynos5420 is compatible with exynos5250 fully for #2.
But because there is no use case for new registers, it could be acceptable.
Ok, we should be careful to configure DT file though.

Thanks,
Seungwon Jeon

Re: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Tomasz Figa]

Hi Seungwon,

On Thursday 29 of August 2013 19:36:28 Seungwon Jeon wrote:
> Yuvaraj Kumar wrote:
> > On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com> 
wrote:
> > > On Thu, August 29, 2013, Alim Akhtar wrote:
> > >> Hi Seungwon,
> > >> 
> > >> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon 
<tgih.jun@samsung.com> wrote:
> > >> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> > >> >> Exynos5420 Mobile Storage Host controller has Security Management
> > >> >> Unit
> > >> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch
> > >> >> configures SMU for exynos5420.
> > >> >> 
> > >> >> This patch is on top of the below patch by Doug Anderson.
> > >> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> > >> >> 
> > >> >> changes since V2:
> > >> >>       1.Droppped the bypass-smu quirk.
> > >> >>       2.Changed the subject line for this patch
> > >> >>       
> > >> >>         add a quirk for SMU -> configure SMU in exynos5420
> > >> >> 
> > >> >> changes since V1:
> > >> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init
> > >> >>       in
> > >> >>       
> > >> >>         resume path.
> > >> >> 
> > >> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> > >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > >> >> ---
> > >> >> 
> > >> >>  drivers/mmc/host/dw_mmc-exynos.c |   29
> > >> >>  +++++++++++++++++++++++++++++
> > >> >>  1 file changed, 29 insertions(+)
> > >> >> 
> > >> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c
> > >> >> b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..db28f10 100644
> > >> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> > >> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> > >> >> @@ -35,6 +35,25 @@
> > >> >> 
> > >> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> > >> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> > >> >> 
> > >> >> +/* Block number in eMMC */
> > >> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> > >> >> +
> > >> >> +#define SDMMC_EMMCP_BASE             0x1000
> > >> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> > >> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE +
> > >> >> 0x0200) +#define SDMMC_MPSEND0                       
> > >> >> (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0             
> > >> >>          (SDMMC_EMMCP_BASE + 0x020C) +
> > >> >> +/* SMU control bits */
> > >> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> > >> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> > >> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> > >> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> > >> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> > >> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> > >> >> +
> > >> >> 
> > >> >>  /* Variations in Exynos specific dw-mshc controller */
> > >> >>  enum dw_mci_exynos_type {
> > >> >>  
> > >> >>       DW_MCI_TYPE_EXYNOS4210,
> > >> >> 
> > >> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct
> > >> >> dw_mci *host)> >> >> 
> > >> >>  {
> > >> >>  
> > >> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> > >> >> 
> > >> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> > >> >> +             mci_writel(host, MPSBEGIN0, 0);
> > >> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> > >> >> +             mci_writel(host, MPSCTRL0,
> > >> >> DWMCI_MPSCTRL_SECURE_WRITE_BIT | +                    
> > >> >> DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> > >> >> +                     DWMCI_MPSCTRL_VALID |
> > >> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> > >> > 
> > >> > Yuvaraj,
> > >> > 
> > >> > Just one thing to check.
> > >> > ch#0 and #1 of three hosts are only valid for SMU control.
> > >> > Did you consider #2 host?
> > >> > It seems not.
> > >> 
> > >> Only host#0 and host#1 has SMU (On exynos5420).
> > >> Host #2 does not contain SMU.
> > > 
> > > Let me clear it.
> > > I mean that current change allows for ch2 to access registers related
> > > to SMU, even though ch2 doesn't actually has SMU. It's not valid IO
> > > area.> 
> > No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> > but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
> > Below is the DT patch posted in another thread.
> > [1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
> > http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.
> > html I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for
> > host#2.
> Hmm. If we notice exynos5420's other newly added registers apart from
> SMU, it is difficult to say exynos5420 is compatible with exynos5250
> fully for #2. But because there is no use case for new registers, it
> could be acceptable. Ok, we should be careful to configure DT file
> though.

Could you elaborate a bit more on the differences in DW MMC IP between 
Exynos5250 and Exynos5420? If the differences are significant, then it 
might be necessary to use different compatible value, as it should not 
depend on any use case (or lack of).

If the DW MMC version used in Exynos 5420 provides the whole set of 
functionality of the version used in Exynos 5250 and some extra extensions, 
then it can be called "compatible with Exynos 5250", but if you ever need 
to support those extra extensions, you will have to add a separate 
compatible string for it.

With regard to SMU that is present only on selected instances, you can as 
well create two compatible values for the DW MMC IP on Exynos 5420, e.g. 
"samsung,exynos5420-dw-mshc" and "samsung,exynos5420-dw-mshc-smu".

[Adding devicetree ML and DT maintainers on CC, as this is something they 
should be able to comment on.]

Best regards,
Tomasz

RE: [RFC V3 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Seungwon Jeon]

On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> Currently platform specific private data initialisation is done by
> dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
> separate platform specific device tree parser dw_mci_socfpga_parse_dt,
> move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
> We can use the dw_mci_socfpga_priv_init to do some actual platform
> specific initialisation.
> 
> This patch is compile tested only.
CC'ed Dinh Nguyen

Thanks,
Seungwon Jeon

> 
> changes since V2: none
> 
> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> ---
>  drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++++++---------------
>  1 file changed, 14 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> index 14b5961..953f260 100644
> --- a/drivers/mmc/host/dw_mmc-socfpga.c
> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> @@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
> 
>  static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>  {
> -	struct dw_mci_socfpga_priv_data *priv;
> -
> -	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> -	if (!priv) {
> -		dev_err(host->dev, "mem alloc failed for private data\n");
> -		return -ENOMEM;
> -	}
> -
> -	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> -	if (IS_ERR(priv->sysreg)) {
> -		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> -		return PTR_ERR(priv->sysreg);
> -	}
> -	host->priv = priv;
> 
>  	return 0;
>  }
> @@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> 
>  static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>  {
> -	struct dw_mci_socfpga_priv_data *priv = host->priv;
> +	struct dw_mci_socfpga_priv_data *priv;
>  	struct device_node *np = host->dev->of_node;
>  	u32 timing[2];
>  	u32 div = 0;
>  	int ret;
> 
> +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv) {
> +		dev_err(host->dev, "mem alloc failed for private data\n");
> +		return -ENOMEM;
> +	}
> +
> +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> +	if (IS_ERR(priv->sysreg)) {
> +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> +		return PTR_ERR(priv->sysreg);
> +	}
> +
>  	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
>  	if (ret)
>  		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
> @@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>  		return ret;
> 
>  	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> +	host->priv = priv;
>  	return 0;
>  }
> 
> --
> 1.7.9.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [RFC V3 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420.

[Seungwon Jeon]

On Thu, August 29, 2013, Tomasz Figa wrote:
> Hi Seungwon,
> 
> On Thursday 29 of August 2013 19:36:28 Seungwon Jeon wrote:
> > Yuvaraj Kumar wrote:
> > > On Thu, Aug 29, 2013 at 3:14 PM, Seungwon Jeon <tgih.jun@samsung.com>
> wrote:
> > > > On Thu, August 29, 2013, Alim Akhtar wrote:
> > > >> Hi Seungwon,
> > > >>
> > > >> On Thu, Aug 29, 2013 at 1:53 PM, Seungwon Jeon
> <tgih.jun@samsung.com> wrote:
> > > >> > On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> > > >> >> Exynos5420 Mobile Storage Host controller has Security Management
> > > >> >> Unit
> > > >> >> (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch
> > > >> >> configures SMU for exynos5420.
> > > >> >>
> > > >> >> This patch is on top of the below patch by Doug Anderson.
> > > >> >> mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT
> > > >> >>
> > > >> >> changes since V2:
> > > >> >>       1.Droppped the bypass-smu quirk.
> > > >> >>       2.Changed the subject line for this patch
> > > >> >>
> > > >> >>         add a quirk for SMU -> configure SMU in exynos5420
> > > >> >>
> > > >> >> changes since V1:
> > > >> >>       1.avoid code duplication by calling dw_mci_exynos_priv_init
> > > >> >>       in
> > > >> >>
> > > >> >>         resume path.
> > > >> >>
> > > >> >> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> > > >> >> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> > > >> >> ---
> > > >> >>
> > > >> >>  drivers/mmc/host/dw_mmc-exynos.c |   29
> > > >> >>  +++++++++++++++++++++++++++++
> > > >> >>  1 file changed, 29 insertions(+)
> > > >> >>
> > > >> >> diff --git a/drivers/mmc/host/dw_mmc-exynos.c
> > > >> >> b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..db28f10 100644
> > > >> >> --- a/drivers/mmc/host/dw_mmc-exynos.c
> > > >> >> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> > > >> >> @@ -35,6 +35,25 @@
> > > >> >>
> > > >> >>  #define EXYNOS4210_FIXED_CIU_CLK_DIV 2
> > > >> >>  #define EXYNOS4412_FIXED_CIU_CLK_DIV 4
> > > >> >>
> > > >> >> +/* Block number in eMMC */
> > > >> >> +#define DWMCI_BLOCK_NUM                      0xFFFFFFFF
> > > >> >> +
> > > >> >> +#define SDMMC_EMMCP_BASE             0x1000
> > > >> >> +#define SDMMC_MPSECURITY             (SDMMC_EMMCP_BASE + 0x0010)
> > > >> >> +#define SDMMC_MPSBEGIN0                      (SDMMC_EMMCP_BASE +
> > > >> >> 0x0200) +#define SDMMC_MPSEND0
> > > >> >> (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0
> > > >> >>          (SDMMC_EMMCP_BASE + 0x020C) +
> > > >> >> +/* SMU control bits */
> > > >> >> +#define DWMCI_MPSCTRL_SECURE_READ_BIT                BIT(7)
> > > >> >> +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT               BIT(6)
> > > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT    BIT(5)
> > > >> >> +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT   BIT(4)
> > > >> >> +#define DWMCI_MPSCTRL_USE_FUSE_KEY           BIT(3)
> > > >> >> +#define DWMCI_MPSCTRL_ECB_MODE                       BIT(2)
> > > >> >> +#define DWMCI_MPSCTRL_ENCRYPTION             BIT(1)
> > > >> >> +#define DWMCI_MPSCTRL_VALID                  BIT(0)
> > > >> >> +
> > > >> >>
> > > >> >>  /* Variations in Exynos specific dw-mshc controller */
> > > >> >>  enum dw_mci_exynos_type {
> > > >> >>
> > > >> >>       DW_MCI_TYPE_EXYNOS4210,
> > > >> >>
> > > >> >> @@ -74,6 +93,15 @@ static int dw_mci_exynos_priv_init(struct
> > > >> >> dw_mci *host)> >> >>
> > > >> >>  {
> > > >> >>
> > > >> >>       struct dw_mci_exynos_priv_data *priv = host->priv;
> > > >> >>
> > > >> >> +     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) {
> > > >> >> +             mci_writel(host, MPSBEGIN0, 0);
> > > >> >> +             mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM);
> > > >> >> +             mci_writel(host, MPSCTRL0,
> > > >> >> DWMCI_MPSCTRL_SECURE_WRITE_BIT | +
> > > >> >> DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
> > > >> >> +                     DWMCI_MPSCTRL_VALID |
> > > >> >> +                     DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT);
> > > >> >
> > > >> > Yuvaraj,
> > > >> >
> > > >> > Just one thing to check.
> > > >> > ch#0 and #1 of three hosts are only valid for SMU control.
> > > >> > Did you consider #2 host?
> > > >> > It seems not.
> > > >>
> > > >> Only host#0 and host#1 has SMU (On exynos5420).
> > > >> Host #2 does not contain SMU.
> > > >
> > > > Let me clear it.
> > > > I mean that current change allows for ch2 to access registers related
> > > > to SMU, even though ch2 doesn't actually has SMU. It's not valid IO
> > > > area.>
> > > No,host#0 and host#1 are compatible with "samsung,exynos5420-dw-mshc"
> > > but host#2 is compatible with the "samsung,exynos5250-dw-mshc".
> > > Below is the DT patch posted in another thread.
> > > [1] [PATCH V4] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
> > > http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg21985.
> > > html I will resubmit the DT patch[1] with reg = <0x12220000 0x1000> for
> > > host#2.
> > Hmm. If we notice exynos5420's other newly added registers apart from
> > SMU, it is difficult to say exynos5420 is compatible with exynos5250
> > fully for #2. But because there is no use case for new registers, it
> > could be acceptable. Ok, we should be careful to configure DT file
> > though.
> 
> Could you elaborate a bit more on the differences in DW MMC IP between
> Exynos5250 and Exynos5420? If the differences are significant, then it
> might be necessary to use different compatible value, as it should not
> depend on any use case (or lack of).
Actually the reason is  that extended register of ch2 doesn't work rather than none of use case.
Ch2 is targeted for removable card type.

> 
> If the DW MMC version used in Exynos 5420 provides the whole set of
> functionality of the version used in Exynos 5250 and some extra extensions,
> then it can be called "compatible with Exynos 5250", but if you ever need
> to support those extra extensions, you will have to add a separate
> compatible string for it.
> 
> With regard to SMU that is present only on selected instances, you can as
> well create two compatible values for the DW MMC IP on Exynos 5420, e.g.
> "samsung,exynos5420-dw-mshc" and "samsung,exynos5420-dw-mshc-smu".
I think your suggestion is a nice thing. It makes sense.
And I missed one thing.
Apart from added register, Exynos5420 ch2 is designed for I/O of 1.2V voltage unlike Exynos5250.
So it is worthy to be distinguished.

Yuvaraj,
Could you apply Tomasz's suggestion ("samsung,exynos5420-dw-mshc" and "samsung,exynos5420-dw-mshc-smu") and resend it?

Thanks,
Seungwon Jeon

> 
> [Adding devicetree ML and DT maintainers on CC, as this is something they
> should be able to comment on.]
> 
> Best regards,
> Tomasz
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

RE: [RFC V3 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Dinh Nguyen]

On Thu, 2013-08-29 at 20:59 +0900, Seungwon Jeon wrote:
> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
> > Currently platform specific private data initialisation is done by
> > dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
> > separate platform specific device tree parser dw_mci_socfpga_parse_dt,
> > move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
> > We can use the dw_mci_socfpga_priv_init to do some actual platform
> > specific initialisation.

I am looking to remove all of dw_mmc-socfpga file. The only reason for
this file is to set the sdr timing values. But since the register that
controls these SDR values are located out of the IP, it is probably best
to implement the settings in platform specific code.

Dinh
> > 
> > This patch is compile tested only.
> CC'ed Dinh Nguyen
> 
> Thanks,
> Seungwon Jeon
> 
> > 
> > changes since V2: none
> > 
> > Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
> > ---
> >  drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++++++---------------
> >  1 file changed, 14 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
> > index 14b5961..953f260 100644
> > --- a/drivers/mmc/host/dw_mmc-socfpga.c
> > +++ b/drivers/mmc/host/dw_mmc-socfpga.c
> > @@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
> > 
> >  static int dw_mci_socfpga_priv_init(struct dw_mci *host)
> >  {
> > -	struct dw_mci_socfpga_priv_data *priv;
> > -
> > -	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> > -	if (!priv) {
> > -		dev_err(host->dev, "mem alloc failed for private data\n");
> > -		return -ENOMEM;
> > -	}
> > -
> > -	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> > -	if (IS_ERR(priv->sysreg)) {
> > -		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> > -		return PTR_ERR(priv->sysreg);
> > -	}
> > -	host->priv = priv;
> > 
> >  	return 0;
> >  }
> > @@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
> > 
> >  static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> >  {
> > -	struct dw_mci_socfpga_priv_data *priv = host->priv;
> > +	struct dw_mci_socfpga_priv_data *priv;
> >  	struct device_node *np = host->dev->of_node;
> >  	u32 timing[2];
> >  	u32 div = 0;
> >  	int ret;
> > 
> > +	priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
> > +	if (!priv) {
> > +		dev_err(host->dev, "mem alloc failed for private data\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
> > +	if (IS_ERR(priv->sysreg)) {
> > +		dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
> > +		return PTR_ERR(priv->sysreg);
> > +	}
> > +
> >  	ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
> >  	if (ret)
> >  		dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
> > @@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
> >  		return ret;
> > 
> >  	priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
> > +	host->priv = priv;
> >  	return 0;
> >  }
> > 
> > --
> > 1.7.9.5
> > 
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

Re: [RFC V3 2/4] mmc: dw_mmc: socfpga: move socfpga private init

[Yuvaraj Kumar]

On Thu, Sep 5, 2013 at 1:01 AM, Dinh Nguyen <dinguyen@altera.com> wrote:
> On Thu, 2013-08-29 at 20:59 +0900, Seungwon Jeon wrote:
>> On Wed, August 28, 2013, Yuvaraj Kumar C D wrote:
>> > Currently platform specific private data initialisation is done by
>> > dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
>> > separate platform specific device tree parser dw_mci_socfpga_parse_dt,
>> > move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
>> > We can use the dw_mci_socfpga_priv_init to do some actual platform
>> > specific initialisation.
>
> I am looking to remove all of dw_mmc-socfpga file. The only reason for
> this file is to set the sdr timing values. But since the register that
> controls these SDR values are located out of the IP, it is probably best
> to implement the settings in platform specific code.
Well,This patch is included in this series becuase PATCHV4 3/4 of this
sereis will affect
dw_mmc-socfpga driver. However, if you are planning to remove the
whole file,still you can do
on top of this patch. :)
>
> Dinh
>> >
>> > This patch is compile tested only.
>> CC'ed Dinh Nguyen
>>
>> Thanks,
>> Seungwon Jeon
>>
>> >
>> > changes since V2: none
>> >
>> > Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
>> > ---
>> >  drivers/mmc/host/dw_mmc-socfpga.c |   29 ++++++++++++++---------------
>> >  1 file changed, 14 insertions(+), 15 deletions(-)
>> >
>> > diff --git a/drivers/mmc/host/dw_mmc-socfpga.c b/drivers/mmc/host/dw_mmc-socfpga.c
>> > index 14b5961..953f260 100644
>> > --- a/drivers/mmc/host/dw_mmc-socfpga.c
>> > +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> > @@ -38,20 +38,6 @@ struct dw_mci_socfpga_priv_data {
>> >
>> >  static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> >  {
>> > -   struct dw_mci_socfpga_priv_data *priv;
>> > -
>> > -   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> > -   if (!priv) {
>> > -           dev_err(host->dev, "mem alloc failed for private data\n");
>> > -           return -ENOMEM;
>> > -   }
>> > -
>> > -   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> > -   if (IS_ERR(priv->sysreg)) {
>> > -           dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
>> > -           return PTR_ERR(priv->sysreg);
>> > -   }
>> > -   host->priv = priv;
>> >
>> >     return 0;
>> >  }
>> > @@ -79,12 +65,24 @@ static void dw_mci_socfpga_prepare_command(struct dw_mci *host, u32 *cmdr)
>> >
>> >  static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> >  {
>> > -   struct dw_mci_socfpga_priv_data *priv = host->priv;
>> > +   struct dw_mci_socfpga_priv_data *priv;
>> >     struct device_node *np = host->dev->of_node;
>> >     u32 timing[2];
>> >     u32 div = 0;
>> >     int ret;
>> >
>> > +   priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
>> > +   if (!priv) {
>> > +           dev_err(host->dev, "mem alloc failed for private data\n");
>> > +           return -ENOMEM;
>> > +   }
>> > +
>> > +   priv->sysreg = syscon_regmap_lookup_by_compatible("altr,sys-mgr");
>> > +   if (IS_ERR(priv->sysreg)) {
>> > +           dev_err(host->dev, "regmap for altr,sys-mgr lookup failed.\n");
>> > +           return PTR_ERR(priv->sysreg);
>> > +   }
>> > +
>> >     ret = of_property_read_u32(np, "altr,dw-mshc-ciu-div", &div);
>> >     if (ret)
>> >             dev_info(host->dev, "No dw-mshc-ciu-div specified, assuming 1");
>> > @@ -96,6 +94,7 @@ static int dw_mci_socfpga_parse_dt(struct dw_mci *host)
>> >             return ret;
>> >
>> >     priv->hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
>> > +   host->priv = priv;
>> >     return 0;
>> >  }
>> >
>> > --
>> > 1.7.9.5
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
>> > the body of a message to majordomo@vger.kernel.org
>> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>>
>
>
>