From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7123C5519F for ; Wed, 25 Nov 2020 09:57:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5834B206B7 for ; Wed, 25 Nov 2020 09:57:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Y1MuhRmq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727126AbgKYJ5g (ORCPT ); Wed, 25 Nov 2020 04:57:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726250AbgKYJ5g (ORCPT ); Wed, 25 Nov 2020 04:57:36 -0500 Received: from mail-vs1-xe41.google.com (mail-vs1-xe41.google.com [IPv6:2607:f8b0:4864:20::e41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6370C0613D4 for ; Wed, 25 Nov 2020 01:57:19 -0800 (PST) Received: by mail-vs1-xe41.google.com with SMTP id l22so898448vsa.4 for ; Wed, 25 Nov 2020 01:57:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=t0REdB3olCexNERcSHnzJwkFu42mj1xmlom0KLliQ/I=; b=Y1MuhRmqz4Ac5OM43sgbecc7Bv0lPYZlg6hUu79nriANbuJ7cc3DV+kbp7m1OHR8rB BN4fs6A3GfeN5ImPMKR0alrZMeCFRUrn7ErNv424xjNVe4MtBMQ4NXvleHyLoO3REg8r QeP0Yg57+0ikm3CRLXyclKSiJe/0Lf1nuzOBmOE/1ozh85a6VxBmaxQO2BLqKw4pshe8 ew0/TQ9zLUeXlszjngC0w6Unskivab/rbt8kLsO9DPYTd4fgwFWEtTCzxw6PrldRrYtD ypJBfBmWNKMfJo2FmB5PEso5RNtN+gZzIjVFDBzKa1p+EYysVkvHUFLfvG9SfA4Jdj+n S4Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=t0REdB3olCexNERcSHnzJwkFu42mj1xmlom0KLliQ/I=; b=ppE1po0xZObAvlNnL0cR9UUF83BOf3G2lxhZtX6MPkds0LQQNczWpZUXigm28djK+C oijPQeg3N9n6vLl/QBjKJ78LF7SUWQcp5bYCZ/0smXnlJNhbA5krHXVW5yJLP54F+mS0 FWD5gxB+RsErvBqzbQ2IEEgqyf093taB+yl9Khofi8HYaM78WbUfmfiSwgUdQTGkwnut Q/cyIRMYs5fNBYySeehoiaUnU2QLYrs1xfIzaUDohZRYilnPTvVbwQM0DvnwhnTVTV5W ngfBoKhECuj/2JAvS5l19OTljILENG+qcX/O/bfHbPZRrlH3hHbfm0GbUoxKzJ6S2oRh CxLA== X-Gm-Message-State: AOAM5301C5jt6P/crPz9QqTrH77XRbXLKYHtosO0hmr0KUPG70sYDiHP ww4D5k5fJbaOFcQadpmoFhv1JP8APcP7Q9DM/uj4WQ== X-Google-Smtp-Source: ABdhPJzwbR3dPmM+DDvpmCIiGlOOwtZSknMvs/ZVop/d6QS3ZX9tdcZ8DRnaSlHSuFaOAu8Ffbe8WFpIzV7zBj+q5kU= X-Received: by 2002:a05:6102:322a:: with SMTP id x10mr473721vsf.19.1606298239005; Wed, 25 Nov 2020 01:57:19 -0800 (PST) MIME-Version: 1.0 References: <20201112194011.103774-1-ebiggers@kernel.org> In-Reply-To: From: Ulf Hansson Date: Wed, 25 Nov 2020 10:56:42 +0100 Message-ID: Subject: Re: [PATCH 0/8] eMMC inline encryption support To: Eric Biggers Cc: "linux-mmc@vger.kernel.org" , linux-arm-msm , DTML , linux-fscrypt@vger.kernel.org, Satya Tangirala , Andy Gross , Bjorn Andersson , Adrian Hunter , Ritesh Harjani , Asutosh Das , Rob Herring , Neeraj Soni , Barani Muthukumaran , Peng Zhou , Stanley Chu , Konrad Dybcio Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On Fri, 20 Nov 2020 at 19:54, Eric Biggers wrote: > > On Thu, Nov 12, 2020 at 11:40:03AM -0800, Eric Biggers wrote: > > Hello, > > > > This patchset adds support for eMMC inline encryption, as specified by > > the upcoming version of the eMMC specification and as already > > implemented and used on many devices. Building on that, it then adds > > Qualcomm ICE support and wires it up for the Snapdragon 630 SoC. > > > > Inline encryption hardware improves the performance of storage > > encryption and reduces power usage. See > > Documentation/block/inline-encryption.rst for more information about > > inline encryption and the blk-crypto framework (upstreamed in v5.8) > > which supports it. Most mobile devices already use UFS or eMMC inline > > encryption hardware; UFS support was already upstreamed in v5.9. > > > > Patches 1-3 add support for the standard eMMC inline encryption. > > > > However, as with UFS, host controller-specific patches are needed on top > > of the standard support. Therefore, patches 4-8 add Qualcomm ICE > > (Inline Crypto Engine) support and wire it up on the Snapdragon 630 SoC. > > > > To test this I took advantage of the recently upstreamed support for the > > Snapdragon 630 SoC, plus work-in-progress patches from the SoMainline > > project (https://github.com/SoMainline/linux/tree/konrad/v5.10-rc3). In > > particular, I was able to run the fscrypt xfstests for ext4 and f2fs in > > a Debian chroot. Among other things, these tests verified that the > > correct ciphertext is written to disk (the same as software encryption). > > > > It will also be possible to add support for Mediatek eMMC inline > > encryption hardware in mtk-sd, and it should be easier than the Qualcomm > > hardware since the Mediatek hardware follows the standard more closely. > > I.e., patches 1-3 should be almost enough for the Mediatek hardware. > > However, I don't have the hardware to do this yet. > > > > This patchset is based on v5.10-rc3, and it can also be retrieved from > > tag "mmc-crypto-v1" of > > https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git > > > > Note: the fscrypt inline encryption support is partially broken in > > v5.10-rc3, so for testing a fscrypt fix needs to be applied too: > > https://lkml.kernel.org/r/20201111015224.303073-1-ebiggers@kernel.org > > > > Eric Biggers (8): > > mmc: add basic support for inline encryption > > mmc: cqhci: rename cqhci.c to cqhci-core.c > > mmc: cqhci: add support for inline encryption > > mmc: cqhci: add cqhci_host_ops::program_key > > firmware: qcom_scm: update comment for ICE-related functions > > dt-bindings: mmc: sdhci-msm: add ICE registers and clock > > arm64: dts: qcom: sdm630: add ICE registers and clocks > > mmc: sdhci-msm: add Inline Crypto Engine support > > Any comments on this patchset? I have been busy, but just wanted to let you know that I am moving to start reviewing this series shortly. I also need to catch up on the eMMC spec a bit, before I can provide you with comments. Kind regards Uffe