From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF679ECDFA1 for ; Tue, 25 Oct 2022 22:27:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232883AbiJYW1J (ORCPT ); Tue, 25 Oct 2022 18:27:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232620AbiJYW0z (ORCPT ); Tue, 25 Oct 2022 18:26:55 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88504FB707 for ; Tue, 25 Oct 2022 15:26:14 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id v13-20020a17090a6b0d00b0021332e5388fso367584pjj.1 for ; Tue, 25 Oct 2022 15:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=kVEPqaLVudNuaFpxbKtyRoGGYaYZMen60jyTQDmJ0k0=; b=K+FHUN+DhmHFK1V/WuSfv6mwiiQHXJjg1sZf/h/3SDbpDj6pyeIVX+ifv9e5rbB4nn 7xwJgy2i0vtw4aKv/75RDvV95Tm2r1nRElNfDSCBSRJz82TaTUVW5e8ZwdKDcbon4eQ0 SDWFUUlX1tMUlzGfAU+nySGlIs39X+hE7DUCw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=kVEPqaLVudNuaFpxbKtyRoGGYaYZMen60jyTQDmJ0k0=; b=WsDV3thb93kgm+wsKwjWCOZrp6RhNELZaURyThaPyar04RXLSjuj4MYBOdJ0CFrw+u 0ScI00enbyrwCQBgB4gGNL5YJByEsSC26szEJKe35nInakOd8zAm62uCNGFblOYs0fy7 xPkGKHj2tmJtcjRFfZej+FK0areJSNVUr+SzHufn4bZ+QN+kGxPrvvIPOGXqanQiPBEc 3o82s9HNjnSupf+IFaQFpQgb1Clkq8/m5QYjgCGKLfy/E+SCGUd931iBtEfpCvQp+oHb cCt5fnGQXKfBsq4sa1lPrb43VtuwLQYcpR+2Nsjm+rbEW7VENvRwlbVo/XBzL9lk9rhk b6og== X-Gm-Message-State: ACrzQf1w+A5pmD1SGhFJHmp6+KhaSo8jg/fjtI+b4CUYeC2+ZjO5BkBU zND8pOSzkptlvOdwJ0+NrpHJEg== X-Google-Smtp-Source: AMsMyM6gD0CPcY0vG7fGXAk8rMs0hZe+/EtLUVVDC9aYXK3R4Doan2SbfHHxcEtilRi8tbarYUldfA== X-Received: by 2002:a17:90a:9a8f:b0:212:ea8d:dc34 with SMTP id e15-20020a17090a9a8f00b00212ea8ddc34mr624038pjp.30.1666736774027; Tue, 25 Oct 2022 15:26:14 -0700 (PDT) Received: from google.com ([2620:15c:9d:2:efef:6660:5e20:5f6b]) by smtp.gmail.com with ESMTPSA id g9-20020a1709026b4900b001752216ca51sm1653302plt.39.2022.10.25.15.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 15:26:13 -0700 (PDT) Date: Tue, 25 Oct 2022 15:26:10 -0700 From: Brian Norris To: Florian Fainelli Cc: Adrian Hunter , Ulf Hansson , Shawn Lin , linux-mmc@vger.kernel.org, Al Cooper , Bjorn Andersson , Sowjanya Komatineni , Broadcom internal kernel review list , Sascha Hauer , Konrad Dybcio , NXP Linux Team , Thierry Reding , Fabio Estevam , Michal Simek , linux-kernel@vger.kernel.org, Shawn Guo , Pengutronix Kernel Team , linux-arm-msm@vger.kernel.org, Haibo Chen , Andy Gross , linux-arm-kernel@lists.infradead.org, Faiz Abbas , Jonathan Hunter Subject: Re: [PATCH v3 6/7] mmc: sdhci_am654: Fix SDHCI_RESET_ALL for CQHCI Message-ID: References: <20221024175501.2265400-1-briannorris@chromium.org> <20221024105229.v3.6.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid> <5b91c0eb-52aa-8431-c286-81b7feae84ce@intel.com> <6268199c-78ca-8f55-0377-c14bb0299443@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6268199c-78ca-8f55-0377-c14bb0299443@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On Tue, Oct 25, 2022 at 02:53:46PM -0700, Florian Fainelli wrote: > On 10/25/22 14:45, Brian Norris wrote: > > On Tue, Oct 25, 2022 at 04:10:44PM +0300, Adrian Hunter wrote: > > > On 24/10/22 20:55, Brian Norris wrote: > > > > diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c > > > > index 8f1023480e12..6a282c7a221e 100644 > > > > --- a/drivers/mmc/host/sdhci_am654.c > > > > +++ b/drivers/mmc/host/sdhci_am654.c > > > > > > @@ -378,7 +379,7 @@ static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) > > > > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > > > > struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); > > > > - sdhci_reset(host, mask); > > > > + sdhci_and_cqhci_reset(host, mask); > > > > if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { > > > > ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); > > > > > > What about sdhci_reset in sdhci_am654_ops ? > > > > Oops, I think you caught a big fallacy in some of my patches: I assumed > > there was a single reset() implementation in a given driver (an unwise > > assumption, I realize). I see at least sdhci-brcmstb.c also has several > > variant ops that call sdhci_reset(), and I should probably convert them > > too. > > You got it right for sdhci-brcmstb.c because "supports-cqe" which gates the > enabling of CQE can only be found with the "brcm,bcm7216-sdhci" compatible > which implies using brcmstb_reset(). I don't see any in-tree device trees for these chips (which is OK), and that's not what the Documentation/ says, and AFAICT nothing in the driver is limiting other variants from specifying the "supports-cqe" flag in their (out-of-tree) device tree. The closest thing I see is that an *example* in brcm,sdhci-brcmstb.yaml shows "supports-cqe" only on brcm,bcm7216-sdhci -- but an example is not a binding agreement. Am I missing something? Now of course, you probably know behind the scenes that there are no other sdhci-brcmstb-relevant controllers that "support cqe", but AFAICT I have no way of knowing that a priori. The driver and bindings give (too much?) flexibility. Poking around, I think the only other one I might have missed would be gl9763e in sdhci-pci-gli.c. That also calls cqhci_init() but is otherwise relying on the default sdhci_pci_ops. So I'd either have to change the common sdhci_pci_ops, or else start a new copy/paste/modify 'struct sdhci_ops' for it... This really does start to get messy when poking around on drivers I can't test. As in, it shouldn't be harmful to change most sdhci_reset() to sdhci_and_cqhci_reset() (as long as they aren't using some other CQE implementation), but the more invasive it gets (say, rewriting a bunch of other ops), the easier it is to get something wrong. Thoughts welcome. Brian