[PATCH v2 2/4] mmc: Mediatek: enable crypto hardware engine

Peng Zhou
2021-03-09T02:06:53Z

Use SMC call enable hardware crypto engine
due to it only be changed in ATF(EL3).

Signed-off-by: Peng Zhou <peng.zhou@mediatek.com>
---
drivers/mmc/host/mtk-sd.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 1c90360d6cf2..225ef5519161 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -4,6 +4,7 @@
* Author: Chaotian.Jing <chaotian.jing@mediatek.com>
*/

+#include <linux/arm-smccc.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/delay.h>
@@ -20,6 +21,7 @@
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/reset.h>
@@ -319,6 +321,12 @@
#define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */

#define PAD_DELAY_MAX 32 /* PAD delay cells */
+
+/*--------------------------------------------------------------------------*/
+/* SiP commands which used for crypto */
+/*--------------------------------------------------------------------------*/
+#define MTK_SIP_MMC_CONTROL MTK_SIP_SMC_CMD(0x273)
+
/*--------------------------------------------------------------------------*/
/* Descriptor Structure */
/*--------------------------------------------------------------------------*/
@@ -2467,6 +2475,7 @@ static int msdc_of_clock_parse(struct platform_device *pdev,

static int msdc_drv_probe(struct platform_device *pdev)
{
+ struct arm_smccc_res smccc_res;
struct mmc_host *mmc;
struct msdc_host *host;
struct resource *res;
@@ -2616,6 +2625,15 @@ static int msdc_drv_probe(struct platform_device *pdev)
mmc->max_seg_size = 64 * 1024;
}

+ /*
+ * 1: MSDC_AES_CTL_INIT
+ * 4: cap_id, no-meaning now
+ * 1: cfg_id, we choose the second cfg group
+ */
+ if (mmc->caps2 & MMC_CAP2_CRYPTO)
+ arm_smccc_smc(MTK_SIP_MMC_CONTROL,
+ 1, 4, 1, 0, 0, 0, 0, &smccc_res);
+
host->timeout_clks = 3 * 1048576;
host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2 * sizeof(struct mt_gpdma_desc),
@@ -2770,9 +2788,18 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev)
{
struct mmc_host *mmc = dev_get_drvdata(dev);
struct msdc_host *host = mmc_priv(mmc);
+ struct arm_smccc_res smccc_res;

msdc_ungate_clock(host);
msdc_restore_reg(host);
+ /*
+ * 1: MSDC_AES_CTL_INIT
+ * 4: cap_id, no-meaning now
+ * 1: cfg_id, we choose the second cfg group
+ */
+ if (mmc->caps2 & MMC_CAP2_CRYPTO)
+ arm_smccc_smc(MTK_SIP_MMC_CONTROL,
+ 1, 4, 1, 0, 0, 0, 0, &smccc_res);
return 0;
}

--
2.18.0