From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Biju Das <biju.das.jz@bp.renesas.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Biju Das <biju.das.au@gmail.com>
Subject: Re: [PATCH v5 2/2] mmc: renesas_sdhi: Add support for RZ/G3E SoC
Date: Mon, 3 Mar 2025 22:14:02 +0100 [thread overview]
Message-ID: <Z8Ybmol4j8wn1ARl@shikoro> (raw)
In-Reply-To: <20250303113812.88014-3-biju.das.jz@bp.renesas.com>
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On Mon, Mar 03, 2025 at 11:38:08AM +0000, Biju Das wrote:
> The SDHI/eMMC IPs in the RZ/G3E SoC are similar to those in R-Car Gen3.
> However, the RZ/G3E SD0 channel has Voltage level control and PWEN pin
> support via SD_STATUS register.
>
> internal regulator support is added to control the voltage levels of
> the SD pins via sd_iovs/sd_pwen bits in SD_STATUS register by populating
> vqmmc-regulator child node.
>
> SD1 and SD2 channels have gpio regulator support and internal regulator
> support. Selection of the regulator is based on the regulator phandle.
> Similar case for SD0 fixed voltage (eMMC) that uses fixed regulator and
> SD0 non-fixed voltage (SD0) that uses internal regulator.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks!
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prev parent reply other threads:[~2025-03-03 21:14 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-03 11:38 [PATCH v5 0/2] Add RZ/G3E SDHI support Biju Das
2025-03-03 11:38 ` [PATCH v5 1/2] dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support Biju Das
2025-03-03 11:38 ` [PATCH v5 2/2] mmc: renesas_sdhi: Add support for RZ/G3E SoC Biju Das
2025-03-03 16:49 ` Biju Das
2025-03-03 21:14 ` Wolfram Sang [this message]
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