From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adrian Hunter Subject: Re: [RESEND PATCHv1 5/8] mmc: sdhci-msm: configure CORE_CSR_CDC_DELAY_CFG to recommended value Date: Thu, 19 Jan 2017 12:05:39 +0200 Message-ID: References: <1484031652-12059-1-git-send-email-riteshh@codeaurora.org> <1484031652-12059-6-git-send-email-riteshh@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: Received: from mga04.intel.com ([192.55.52.120]:19129 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751375AbdASKLn (ORCPT ); Thu, 19 Jan 2017 05:11:43 -0500 In-Reply-To: <1484031652-12059-6-git-send-email-riteshh@codeaurora.org> Sender: linux-mmc-owner@vger.kernel.org List-Id: linux-mmc@vger.kernel.org To: Ritesh Harjani , ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org, asutoshd@codeaurora.org, stummala@codeaurora.org, venkatg@codeaurora.org, pramod.gurav@linaro.org, jeremymc@redhat.com, git@kchr.de, Subhash Jadavani On 10/01/17 09:00, Ritesh Harjani wrote: > From: Subhash Jadavani > > Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay. > We may see data CRC errors if it's programmed for any other delay > value. > > Signed-off-by: Subhash Jadavani > Signed-off-by: Ritesh Harjani Acked-by: Adrian Hunter > --- > drivers/mmc/host/sdhci-msm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index a028568..84d29dd 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -679,7 +679,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) > writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); > writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); > writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); > - writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); > + writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); > writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); > writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG); > >