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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae353c01980sm810958466b.81.2025.07.01.02.04.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Jul 2025 02:04:48 -0700 (PDT) Message-ID: Date: Tue, 1 Jul 2025 11:04:45 +0200 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 2/4] dt-bindings: mmc: controller: Add max-sd-hs-frequency property To: Krzysztof Kozlowski , Sarthak Garg , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250618072818.1667097-1-quic_sartgarg@quicinc.com> <20250618072818.1667097-3-quic_sartgarg@quicinc.com> <6040afd9-a2a8-49f0-85e9-95257b938156@kernel.org> <9627ed6f-2bb8-40b0-b647-5f659d87f2f9@oss.qualcomm.com> <5bdae07b-a7b1-49be-b843-1704981bc63b@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: -glCy7N-jPRFTlTB_wxhFvX0uuPNuATn X-Proofpoint-ORIG-GUID: -glCy7N-jPRFTlTB_wxhFvX0uuPNuATn X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAxMDA1MiBTYWx0ZWRfXzLtxsqeLjAES +mc+kvYM5nO9YsNzUbkvGhJu0aX7/XejmbqYUCrAY2PfDP5Z7CkMIyF4D49po4BbfVuyjqFC3YC gLLLmXr+SJPtxF5RFK19ITVF9LqThimQt/XRzmjl4ss/SM2UKaRTJzgxQ98R5C7Xi7ddyhulWlB pNHdR8usYPadgTqzHeLxW4RYLBIZPnhijfRuO2I5y0Ho/ZSdwCydgRdGBtNx4fd6yU4GQNk+Hoo gd11cCTHR+/1Hjdn1ouCIoAEvsxjdZGLbN6V+2+CTXLN23N1N5m4s57XtaQtLz/cjLRKOzxUrho R8MxgdDNOrzWFV80hutMkBuPrsUwO6vBEoALhKdi2mvQKaa60lH7YNspXdAE+E4/0+zpoqwHhbv qdJqUdXWZ9gc7xCAoToVqP+nHTgwuyQ7QfayZ8z99J58GOjE6CpiEo1I5eLTmlzldAT4M3mk X-Authority-Analysis: v=2.4 cv=QMFoRhLL c=1 sm=1 tr=0 ts=6863a4b3 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=fKQzr7EGRj+VoE0XNsDNvQ==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=Nx1jMUExMGuVGuT9j-gA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-01_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507010052 On 24-Jun-25 08:06, Krzysztof Kozlowski wrote: > On 23/06/2025 14:31, Konrad Dybcio wrote: >> On 6/23/25 2:16 PM, Krzysztof Kozlowski wrote: >>> On 23/06/2025 14:08, Konrad Dybcio wrote: >>>>>>> >>>>>>> This might be fine, but your DTS suggests clearly this is SoC compatible >>>>>>> deducible, which I already said at v1. >>>>>> >>>>>> I don't understand why you're rejecting a common solution to a problem >>>>>> that surely exists outside this one specific chip from one specific >>>>>> vendor, which may be caused by a multitude of design choices, including >>>>>> erratic board (not SoC) electrical design >>>>> >>>>> No one brought any arguments so far that common solution is needed. The >>>>> only argument provided - sm8550 - is showing this is soc design. >>>>> >>>>> I don't reject common solution. I provided review at v1 to which no one >>>>> responded, no one argued, no one provided other arguments. >>>> >>>> Okay, so the specific problem that causes this observable limitation >>>> exists on SM8550 and at least one more platform which is not upstream >>>> today. It can be caused by various electrical issues, in our specific >>>> case by something internal to the SoC (but external factors may apply >>>> too) >>>> >>>> Looking at the docs, a number of platforms have various limitations >>>> with regards to frequency at specific speed-modes, some of which seem >>>> to be handled implicitly by rounding in the clock framework's >>>> round/set_rate(). >>>> >>>> I can very easily imagine there are either boards or platforms in the >>>> wild, where the speed must be limited for various reasons, maybe some >>>> of them currently don't advertise it (like sm8550 on next/master) to >>>> hide that >>> >>> But there are no such now. The only argument (fact) provided in this >>> patchset is: this is issue specific to SM8550 SoC, not the board. See >>> last patch. Therefore this is compatible-deducible and this makes >>> property without any upstream user. >> >> When one appears, we will have to carry code to repeat what the property >> does, based on a specific compatible.. And all OS implementations will >> have to do the same, instead of parsing the explicit information > > Adding new property in such case will be trivial and simple, unlike > having to maintain unused ABI. > > And it will be unused, because last patch DTS should be rejected on that > basis: adding redundant properties which are already defined by the > compatible. Got some more fresh information.. This apparently *does* vary across boards, as there is a recommended hardware workaround to this rate limitation (requiring an external clock source, which is up to the OEM to implement or not) Konrad