[PATCH 3/9] dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl

Kathiravan Thirumoorthy
2026-03-11T09:46:13Z

Add device tree bindings for IPQ5210 TLMM block.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
.../bindings/pinctrl/qcom,ipq5210-tlmm.yaml | 141 +++++++++++++++++++++
1 file changed, 141 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..3e5a46638385cf7925963c7e4b615c67e642152c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5210 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
+
+description: |
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5210-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 27
+
+ gpio-line-names:
+ maxItems: 54
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5210-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5210-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5210-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char_start, atest_char_status0, atest_char_status1,
+ atest_char_status2, atest_char_status3, atest_tic_en, audio_pri0,
+ audio_pri1, audio_pri2, audio_pri3, audio_pri_d0, audio_pri_d1,
+ audio_pri_fsync, audio_pri_pclk, audio_sec0, audio_sec1,
+ audio_sec2, audio_sec3, audio_sec_d0, audio_sec_d1,
+ audio_sec_fsync, audio_sec_pclk, core_voltage_0, cri_trng0,
+ cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out,
+ gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, Led00,
+ led01, led02, led10, led11, led12, led20, led21, led22,
+ mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, mdio_slv0,
+ mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, pcie0_wake,
+ pcie1_clk_req_n, pcie1_wake, pll_test, pon_active_led,
+ pon_mux_sel, pon_rx, pon_rx_los, pon_tx, pon_tx_burst,
+ pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, gpn_tx_burst,
+ gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm_out00, pwm_out01,
+ pwm_out02, pwm_out03, pwm_out10, pwm_out11, pwm_out12,
+ pwm_out20, pwm_out21, pwm_out22, pwm_out30, pwm_out31,
+ pwm_out32, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
+ qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
+ qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
+ qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2,
+ qspi_data, qspi_clk, qspi_cs_n, qup_se0_l0, qup_se0_l1,
+ qup_se0_l2, qup_se0_l3, qup_se0_l4, qup_se0_l5, qup_se1_l0,
+ qup_se1_l1, qup_se1_l2, qup_se1_l3, qup_se2_l00, qup_se2_l01,
+ qup_se2_l10, qup_se2_l11, qup_se2_l2, qup_se2_l3, qup_se3_l0,
+ qup_se3_l1, qup_se3_l2, qup_se3_l3, qup_se4_l0, qup_se4_l1,
+ qup_se4_l2, qup_se4_l3, qup_se4_l4, qup_se4_l5, qup_se5_l00,
+ qup_se5_l01, qup_se5_l10, qup_se5_l11, qup_se5_l2, qup_se5_l3,
+ qup_se5_l4, qup_se5_l5, resout, rx_los00, rx_los01, rx_los10,
+ rx_los11, rx_los20, rx_los21, sdc_clk, sdc_cmd, sdc_data,
+ tsens_max ]
+
+ required:
+ - pins
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5210-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ gpio-ranges = <&tlmm 0 0 54>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+ qup-uart1-default-state {
+ tx-pins {
+ pins = "gpio39";
+ function = "qup_se1_l2";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ rx-pins {
+ pins = "gpio38";
+ function = "qup_se1_l3";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+ };
+
+ };

--
2.34.1