From: Adrian Hunter <adrian.hunter@intel.com>
To: Vadym Kochan <vadym.kochan@plvision.eu>
Cc: Robin Murphy <robin.murphy@arm.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Hu Ziji <huziji@marvell.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
Elad Nachman <enachman@marvell.com>,
iommu@lists.linux.dev, Mickey Rachamim <mickeyr@marvell.com>,
Christoph Hellwig <hch@infradead.org>
Subject: Re: [PATCH] mmc: sdhci-xenon: Fix 2G limitation on AC5 SoC
Date: Wed, 9 Nov 2022 09:50:06 +0200 [thread overview]
Message-ID: <a9605f47-2f11-0ed3-d513-717c1935b83d@intel.com> (raw)
In-Reply-To: <VI1P190MB0317DC34760DFDE69F69A700953F9@VI1P190MB0317.EURP190.PROD.OUTLOOK.COM>
On 8/11/22 21:05, Vadym Kochan wrote:
> Hi Adrian,
>
> On Thu, 13 Oct 2022 09:40:00 +0300, Vadym Kochan <vadym.kochan@plvision.eu> wrote:
>> Hi Robin,
>>
>> On Mon, 22 Aug 2022 11:06:43 +0100, Robin Murphy <robin.murphy@arm.com> wrote:
>>> On 2022-08-21 07:17, Christoph Hellwig wrote:
>>>> On Thu, Aug 18, 2022 at 03:07:40PM +0300, Vadym Kochan wrote:
>>>>> It works with the following changes:
>>>>>
>>>>> #1 dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>;
>>>>>
>>>>> #3 swiotlb="force"
>>>>>
>>>>> Is it OK to force the memory allocation from the start for the swiotlb ?
>>>>
>>>> It should be ok, but isn't really optimal.
>>>>
>>>> I wonder if we should just allow DT to specify the swiotlb buffer
>>>> location. Basically have yet another RESERVEDMEM_OF_DECLARE variant
>>>> for it, which shouldn't be all that much work except for figuring
>>>> out the interaction with the various kernel command line options.
>>>
>>> We already have all the information we need in the DT (and ACPI), the
>>> arm64 init code just needs to do a better job of interpreting it
>>> properly. I'll see what I can come up with once I've finished what I'm
>>> currently tied up in.
>>>
>>> Thanks,
>>> Robin.
>>
>> Sorry to disturb you, I just 'd like to know if you have
>> some ideas to share or patches to test ?
>>
>> Thank you!
>>
>
> Since AC5X eMMC controller can fail to work on boards with >2GB memory,
> and considering that the best fix may not be easy (as it requires arm64 infra changes),
> so would it be OK to use PIO mode as temporary solution ?
>
> I understand that arm64 changes might not be trivial and it might take significant
> amount of time to implement considering this unusual case, I just think that better
> to make eMMC working even if it will be slow.
You can disable DMA if you wish:
SDHCI_QUIRK_BROKEN_DMA | SDHCI_QUIRK_BROKEN_ADMA
however did you consider SDMA:
SDHCI_QUIRK_BROKEN_ADMA
which uses a bounce buffer allocated by SDHCI?
In any case, you need to add comments to the code
and commit message explaining the swiotlb issue.
next prev parent reply other threads:[~2022-11-09 7:50 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 17:07 [PATCH] mmc: sdhci-xenon: Fix 2G limitation on AC5 SoC Vadym Kochan
2022-07-26 17:37 ` Florian Fainelli
2022-07-27 16:45 ` Vadym Kochan
2022-08-01 9:30 ` Vadym Kochan
2022-08-08 9:19 ` Adrian Hunter
2022-08-08 9:52 ` Vadym Kochan
2022-08-08 10:29 ` Vadym Kochan
2022-08-08 11:40 ` Adrian Hunter
2022-08-08 12:26 ` Vadym Kochan
2022-08-08 12:58 ` Adrian Hunter
2022-08-08 14:06 ` Robin Murphy
2022-08-16 20:51 ` Vadym Kochan
2022-08-17 13:43 ` Robin Murphy
2022-08-17 16:07 ` Vadym Kochan
2022-08-17 17:23 ` Robin Murphy
2022-08-18 12:07 ` Vadym Kochan
2022-08-21 6:17 ` Christoph Hellwig
2022-08-22 10:06 ` Robin Murphy
2022-09-06 9:22 ` Vadym Kochan
2022-10-13 6:40 ` Vadym Kochan
2022-11-08 19:05 ` Vadym Kochan
2022-11-09 7:50 ` Adrian Hunter [this message]
2022-11-09 8:40 ` Vadym Kochan
2022-11-09 9:29 ` Adrian Hunter
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