[PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Biju Das]

Wrong actual clock reported, if the SD clock division ratio is other
than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111).

On high speed mode, cat /sys/kernel/debug/mmc1/ios
Without the patch:
clock:          50000000 Hz
actual clock:   200000000 Hz

After the fix:
clock:          50000000 Hz
actual clock:   50000000 Hz

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Note:
For HS400, the division ratio is 0. I don't have a board with HS400 mode
to verify the fix.

I believe for HS400 Mode,
SDnH = 800MHz
Divider 2 = 400MHz
Division ratio 0 = 400 / 2 = 200MHz

and for HS200/SDR-104
SDnH = 800 MHz
Divider 4 = 200 MHz
Division ratio 1:1 = 200MHz

Please correct me, if it is wrong.
---
 drivers/mmc/host/renesas_sdhi_core.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index fb8ca03f661d..a41291a28e9b 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -222,7 +222,11 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 			clk &= ~0xff;
 	}
 
-	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
+	clock = clk & CLK_CTL_DIV_MASK;
+	if (clock != 0xff)
+		host->mmc->actual_clock /= (1 << (ffs(clock) + 1));
+
+	sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock);
 	if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 		usleep_range(10000, 11000);
 
-- 
2.43.0

Re: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Ulf Hansson]

On Sun, 29 Jun 2025 at 22:39, Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Wrong actual clock reported, if the SD clock division ratio is other
> than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111).
>
> On high speed mode, cat /sys/kernel/debug/mmc1/ios
> Without the patch:
> clock:          50000000 Hz
> actual clock:   200000000 Hz
>
> After the fix:
> clock:          50000000 Hz
> actual clock:   50000000 Hz
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
> Note:
> For HS400, the division ratio is 0. I don't have a board with HS400 mode
> to verify the fix.
>
> I believe for HS400 Mode,
> SDnH = 800MHz
> Divider 2 = 400MHz
> Division ratio 0 = 400 / 2 = 200MHz
>
> and for HS200/SDR-104
> SDnH = 800 MHz
> Divider 4 = 200 MHz
> Division ratio 1:1 = 200MHz
>
> Please correct me, if it is wrong.
> ---
>  drivers/mmc/host/renesas_sdhi_core.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
> index fb8ca03f661d..a41291a28e9b 100644
> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -222,7 +222,11 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
>                         clk &= ~0xff;
>         }
>
> -       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
> +       clock = clk & CLK_CTL_DIV_MASK;
> +       if (clock != 0xff)
> +               host->mmc->actual_clock /= (1 << (ffs(clock) + 1));
> +
> +       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock);
>         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
>                 usleep_range(10000, 11000);
>
> --
> 2.43.0
>

Re: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Geert Uytterhoeven]

Hi Biju,

On Sun, 29 Jun 2025 at 22:39, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Wrong actual clock reported, if the SD clock division ratio is other
> than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111).
>
> On high speed mode, cat /sys/kernel/debug/mmc1/ios
> Without the patch:
> clock:          50000000 Hz
> actual clock:   200000000 Hz
>
> After the fix:
> clock:          50000000 Hz
> actual clock:   50000000 Hz
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -222,7 +222,11 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
>                         clk &= ~0xff;
>         }
>
> -       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
> +       clock = clk & CLK_CTL_DIV_MASK;
> +       if (clock != 0xff)

Perhaps CLK_CTL_DIV_MASK?

> +               host->mmc->actual_clock /= (1 << (ffs(clock) + 1));
> +
> +       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock);
>         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
>                 usleep_range(10000, 11000);

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 18 August 2025 12:00
> Subject: Re: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock
> 
> Hi Biju,
> 
> On Sun, 29 Jun 2025 at 22:39, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Wrong actual clock reported, if the SD clock division ratio is other
> > than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111).
> >
> > On high speed mode, cat /sys/kernel/debug/mmc1/ios Without the patch:
> > clock:          50000000 Hz
> > actual clock:   200000000 Hz
> >
> > After the fix:
> > clock:          50000000 Hz
> > actual clock:   50000000 Hz
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/drivers/mmc/host/renesas_sdhi_core.c
> > +++ b/drivers/mmc/host/renesas_sdhi_core.c
> > @@ -222,7 +222,11 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
> >                         clk &= ~0xff;
> >         }
> >
> > -       sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
> > +       clock = clk & CLK_CTL_DIV_MASK;
> > +       if (clock != 0xff)
> 
> Perhaps CLK_CTL_DIV_MASK?

I will send a new patch for replacing magic number with the 
CLK_CTL_DIV_MASK macro as this patch is applied to mmc/next.

Cheers,
Biju

Re: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Wolfram Sang]

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> Note:
> For HS400, the division ratio is 0. I don't have a board with HS400 mode
> to verify the fix.

I can only test remote this week. I tried this on a HS400 enabled board.

cat /sys/kernel/debug/mmc0/ios

and

cat /sys/kernel/debug/clk/clk_summary | grep sd

both report clocks of 200MHz with HS400 enabled.

Seems good to me?


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RE: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Biju Das]

Hi Wolfram Sang,

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: 21 August 2025 10:42
> Subject: Re: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock
> 
> 
> > Note:
> > For HS400, the division ratio is 0. I don't have a board with HS400
> > mode to verify the fix.
> 
> I can only test remote this week. I tried this on a HS400 enabled board.
> 
> cat /sys/kernel/debug/mmc0/ios
> 
> and
> 
> cat /sys/kernel/debug/clk/clk_summary | grep sd
> 
> both report clocks of 200MHz with HS400 enabled.

Thanks for testing.

> 
> Seems good to me?

Good to me as well, as it transmit data on both edges.

Cheers,
Biju

Re: [PATCH RFT] mmc: host: renesas_sdhi: Fix the actual clock

[Wolfram Sang]

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On Sun, Jun 29, 2025 at 09:38:56PM +0100, Biju Das wrote:
> Wrong actual clock reported, if the SD clock division ratio is other
> than 1:1(bits DIV[7:0] in SD_CLK_CTRL are set to 11111111).
> 
> On high speed mode, cat /sys/kernel/debug/mmc1/ios
> Without the patch:
> clock:          50000000 Hz
> actual clock:   200000000 Hz
> 
> After the fix:
> clock:          50000000 Hz
> actual clock:   50000000 Hz
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>


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