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Thu, 28 Aug 2025 14:57:27 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57SEvQKZ013741 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Aug 2025 14:57:26 GMT Received: from hu-mchunara-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Thu, 28 Aug 2025 07:57:22 -0700 Date: Thu, 28 Aug 2025 20:27:18 +0530 From: Monish Chunara To: Dmitry Baryshkov CC: Wasim Nazir , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , "Richard Cochran" , , , , , , Subject: Re: [PATCH 2/5] arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration Message-ID: References: <20250826-lemans-evk-bu-v1-0-08016e0d3ce5@oss.qualcomm.com> <20250826-lemans-evk-bu-v1-2-08016e0d3ce5@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=VtIjA/2n c=1 sm=1 tr=0 ts=68b06e57 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=kj9zAlcOel0A:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=lhZC9SOiX4wXll4ciBUA:9 a=CjuIK1q_8ugA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMiBTYWx0ZWRfX7pe+JznnpXVr QhhnFqgvImiOdeUzmtbA7coV87Zc2IbyccV06dtQk22h8I94EsiJidg9c3ercxYmH+QeWeZfDyW T/dUhXN5EVmXCmtZH8K8r4BgC+Op3a7Z5ZTd7HDBZdnX3WM3KIKqVZ6JpMpVEw1WkTx/neeVPLi VyoFDE8x9CK/V31ResawpIkVoWaZoe46h3R/iZnZEzROauxAmQxwOd3ceL335NhM+U1lEymVSxJ yFjxQAqk//VVRupV7dWU3TxepN+4x/Pz82abvym+gIw0JWJi8vKJvfwiGMSosLXndYslaj1XxaE G1P+CkL7wnXF5E6SRTkw7/te+HW+s2xPJ6KmeGk3PX94nnU2nfql1oE//uNd7efjlvlEdvuFZnH Cc5k0eYT X-Proofpoint-GUID: ZxAqpAz-Luid5KwGkY8Oihb7WNu1V4kH X-Proofpoint-ORIG-GUID: ZxAqpAz-Luid5KwGkY8Oihb7WNu1V4kH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_04,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230032 On Wed, Aug 27, 2025 at 04:20:20AM +0300, Dmitry Baryshkov wrote: > On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote: > > From: Monish Chunara > > > > Introduce the SDHC v5 controller node for the Lemans platform. > > This controller supports either eMMC or SD-card, but only one > > can be active at a time. SD-card is the preferred configuration > > on Lemans targets, so describe this controller. > > > > Define the SDC interface pins including clk, cmd, and data lines > > to enable proper communication with the SDHC controller. > > > > Signed-off-by: Monish Chunara > > Co-developed-by: Wasim Nazir > > Signed-off-by: Wasim Nazir > > --- > > arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 70 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > > index 99a566b42ef2..a5a3cdba47f3 100644 > > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > > @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint { > > }; > > }; > > > > + sdhc: mmc@87c4000 { > > + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; > > + reg = <0x0 0x087c4000 0x0 0x1000>; > > + > > + interrupts = , > > + ; > > + interrupt-names = "hc_irq", "pwr_irq"; > > + > > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > > + <&gcc GCC_SDCC1_APPS_CLK>; > > + clock-names = "iface", "core"; > > + > > + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>, > > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>; > > + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > > + > > + iommus = <&apps_smmu 0x0 0x0>; > > + dma-coherent; > > + > > + resets = <&gcc GCC_SDCC1_BCR>; > > + > > + no-sdio; > > + no-mmc; > > + bus-width = <4>; > > This is the board configuration, it should be defined in the EVK DTS. ACK. > > > + qcom,dll-config = <0x0007642c>; > > + qcom,ddr-config = <0x80040868>; > > + > > + status = "disabled"; > > + }; Regards, Monish