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Mon, 10 Nov 2025 08:46:36 +0000 Message-ID: Date: Mon, 10 Nov 2025 10:46:32 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] mmc: sdhci-msm: Enable ICE support for non-cmdq eMMC devices To: Md Sadre Alam , , , , , Eric Biggers CC: References: <20251104063943.3424529-1-quic_mdalam@quicinc.com> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20251104063943.3424529-1-quic_mdalam@quicinc.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DU2PR04CA0288.eurprd04.prod.outlook.com (2603:10a6:10:28c::23) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|PH7PR11MB7516:EE_ X-MS-Office365-Filtering-Correlation-Id: 10a6e863-1fec-4917-8bba-08de2035a83a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|7053199007; 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to > integrate ICE configuration into the standard request path for non-CMDQ > eMMC devices. > > * Removed sdhci_crypto_cfg() from sdhci.c and its invocation in sdhci_request() > > Change in [v1] > > * Added initial support for Inline Crypto Engine (ICE) on non-CMDQ eMMC > devices. > > drivers/mmc/host/sdhci-msm.c | 71 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 71 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c > index 4e5edbf2fc9b..6ce205238720 100644 > --- a/drivers/mmc/host/sdhci-msm.c > +++ b/drivers/mmc/host/sdhci-msm.c > @@ -157,6 +157,18 @@ > #define CQHCI_VENDOR_CFG1 0xA00 > #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13) > > +/* non command queue crypto enable register*/ > +#define NONCQ_CRYPTO_PARM 0x70 > +#define NONCQ_CRYPTO_DUN 0x74 > + > +#define DISABLE_CRYPTO BIT(15) > +#define CRYPTO_GENERAL_ENABLE BIT(1) > +#define HC_VENDOR_SPECIFIC_FUNC4 0x260 > +#define ICE_HCI_SUPPORT BIT(28) > + > +#define ICE_HCI_PARAM_CCI GENMASK(7, 0) > +#define ICE_HCI_PARAM_CE GENMASK(8, 8) > + > struct sdhci_msm_offset { > u32 core_hc_mode; > u32 core_mci_data_cnt; > @@ -1885,6 +1897,48 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) > > #ifdef CONFIG_MMC_CRYPTO > > +static int sdhci_msm_ice_cfg(struct sdhci_host *host, struct mmc_request *mrq) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); > + struct mmc_host *mmc = msm_host->mmc; > + struct cqhci_host *cq_host = mmc->cqe_private; > + unsigned int crypto_params = 0; > + int key_index; > + bool crypto_enable; > + u64 dun = 0; > + > + if (mrq->crypto_ctx) { > + crypto_enable = true; > + dun = mrq->crypto_ctx->bc_dun[0]; > + key_index = mrq->crypto_key_slot; > + crypto_params = FIELD_PREP(ICE_HCI_PARAM_CE, crypto_enable) | > + FIELD_PREP(ICE_HCI_PARAM_CCI, key_index); > + > + cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM); > + cqhci_writel(cq_host, lower_32_bits(dun), NONCQ_CRYPTO_DUN); > + } else { > + crypto_enable = false; > + key_index = 0; > + cqhci_writel(cq_host, crypto_params, NONCQ_CRYPTO_PARM); > + } > + > + /* Ensure crypto configuration is written before proceeding */ > + wmb(); > + > + return 0; > +} > + > +static void sdhci_msm_request(struct mmc_host *mmc, struct mmc_request *mrq) > +{ > + struct sdhci_host *host = mmc_priv(mmc); > + > + if (mmc->caps2 & MMC_CAP2_CRYPTO) > + sdhci_msm_ice_cfg(host, mrq); > + > + sdhci_request(mmc, mrq); > +} > + > static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops; /* forward decl */ > > static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, > @@ -2131,6 +2185,8 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host, > struct cqhci_host *cq_host; > bool dma64; > u32 cqcfg; > + u32 config; > + u32 ice_cap; > int ret; > > /* > @@ -2181,6 +2237,18 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host, > if (host->flags & SDHCI_USE_64_BIT_DMA) > host->desc_sz = 12; > > + /* Initialize ICE for non-CMDQ eMMC devices */ > + config = sdhci_readl(host, HC_VENDOR_SPECIFIC_FUNC4); > + config &= ~DISABLE_CRYPTO; > + sdhci_writel(host, config, HC_VENDOR_SPECIFIC_FUNC4); > + ice_cap = cqhci_readl(cq_host, CQHCI_CAP); > + if (ice_cap & ICE_HCI_SUPPORT) { > + config = cqhci_readl(cq_host, CQHCI_CFG); > + config |= CRYPTO_GENERAL_ENABLE; > + cqhci_writel(cq_host, config, CQHCI_CFG); > + } > + sdhci_msm_ice_enable(msm_host); Perhaps this could all be done lazily in sdhci_msm_ice_cfg() ? e.g. if (mrq->crypto_ctx) { if (!msm_host->ice_init_done) { sdhci_msm_non_cqe_ice_init(host, ...); msm_host->ice_init_done = true; } ... > + > ret = __sdhci_add_host(host); > if (ret) > goto cleanup; > @@ -2759,6 +2827,9 @@ static int sdhci_msm_probe(struct platform_device *pdev) > > msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; > > +#ifdef CONFIG_MMC_CRYPTO > + host->mmc_host_ops.request = sdhci_msm_request; > +#endif > /* Set the timeout value to max possible */ > host->max_timeout_count = 0xF; >