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From: Michal Simek <michal.simek@xilinx.com>
To: Ulf Hansson <ulf.hansson@linaro.org>,
	Manish Narani <manish.narani@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	"linux-mmc@vger.kernel.org" <linux-mmc@vger.kernel.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	<git@xilinx.com>
Subject: Re: [PATCH] mmc: sdhci-of-arasan: Add pinctrl support to the driver
Date: Wed, 18 Nov 2020 19:24:28 +0100	[thread overview]
Message-ID: <aeb44b64-5ff6-5662-2761-0e804708ce8a@xilinx.com> (raw)
In-Reply-To: <CAPDyKFr7KTf7jUAuPj=0NZ1sty+y7ySV8PkdrKFXPVthJ=VJVQ@mail.gmail.com>



On 18. 11. 20 16:43, Ulf Hansson wrote:
> On Wed, 18 Nov 2020 at 07:22, Manish Narani <manish.narani@xilinx.com> wrote:
>>
>> Driver should be able to handle optional pinctrl setting.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> Signed-off-by: Manish Narani <manish.narani@xilinx.com>
>> ---
>>  drivers/mmc/host/sdhci-of-arasan.c | 24 ++++++++++++++++++++++++
>>  1 file changed, 24 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
>> index 829ccef87426..f788cc9d5914 100644
>> --- a/drivers/mmc/host/sdhci-of-arasan.c
>> +++ b/drivers/mmc/host/sdhci-of-arasan.c
>> @@ -23,6 +23,7 @@
>>  #include <linux/regmap.h>
>>  #include <linux/of.h>
>>  #include <linux/firmware/xlnx-zynqmp.h>
>> +#include <linux/pinctrl/consumer.h>
>>
>>  #include "cqhci.h"
>>  #include "sdhci-pltfm.h"
>> @@ -135,6 +136,8 @@ struct sdhci_arasan_clk_data {
>>   * @clk_ops:           Struct for the Arasan Controller Clock Operations.
>>   * @soc_ctl_base:      Pointer to regmap for syscon for soc_ctl registers.
>>   * @soc_ctl_map:       Map to get offsets into soc_ctl registers.
>> + * @pinctrl:           Per-device pin control state holder.
>> + * @pins_default:      Pinctrl state for a device.
>>   * @quirks:            Arasan deviations from spec.
>>   */
>>  struct sdhci_arasan_data {
>> @@ -149,6 +152,8 @@ struct sdhci_arasan_data {
>>
>>         struct regmap   *soc_ctl_base;
>>         const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
>> +       struct pinctrl  *pinctrl;
>> +       struct pinctrl_state *pins_default;
>>         unsigned int    quirks;
>>
>>  /* Controller does not have CD wired and will not function normally without */
>> @@ -1619,6 +1624,25 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>>                 goto unreg_clk;
>>         }
>>
>> +       sdhci_arasan->pinctrl = devm_pinctrl_get(&pdev->dev);
>> +       if (!IS_ERR(sdhci_arasan->pinctrl)) {
>> +               sdhci_arasan->pins_default =
>> +                       pinctrl_lookup_state(sdhci_arasan->pinctrl,
>> +                                            PINCTRL_STATE_DEFAULT);
>> +               if (IS_ERR(sdhci_arasan->pins_default)) {
>> +                       dev_err(&pdev->dev, "Missing default pinctrl config\n");
>> +                       ret = PTR_ERR(sdhci_arasan->pins_default);
>> +                       goto unreg_clk;
>> +               }
>> +
>> +               ret = pinctrl_select_state(sdhci_arasan->pinctrl,
>> +                                          sdhci_arasan->pins_default);
>> +               if (ret) {
>> +                       dev_err(&pdev->dev, "could not select default state\n");
>> +                       goto unreg_clk;
>> +               }
>> +       }
> 
> Isn't all this already taken care of via pinctrl_bind_pins() called by
> driver core during probe?
> 

Thanks for the hint.
Manish: Can you please check it?

Thanks,
Michal

  reply	other threads:[~2020-11-18 18:25 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-18  6:21 [PATCH] mmc: sdhci-of-arasan: Add pinctrl support to the driver Manish Narani
2020-11-18 13:49 ` Michal Simek
2020-11-18 15:43 ` Ulf Hansson
2020-11-18 18:24   ` Michal Simek [this message]
2020-11-19 17:20     ` Manish Narani

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