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Mon, 22 Jun 2026 00:38:12 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84564e745besm6303006b3a.28.2026.06.22.00.38.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 00:38:12 -0700 (PDT) Date: Mon, 22 Jun 2026 13:08:04 +0530 From: Abhinaba Rakshit To: Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Adrian Hunter , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neeraj Soni , Harshal Dev , Kuldeep Singh , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v11 5/6] arm64: dts: qcom: monaco: Add OPP-table for ICE UFS and ICE eMMC nodes Message-ID: References: <20260609-enable-ice-clock-scaling-v11-0-1cebc8b3275b@oss.qualcomm.com> <20260609-enable-ice-clock-scaling-v11-5-1cebc8b3275b@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-GUID: SgN4q38vRuEKd4h7M3K22hnlnSMiKccG X-Proofpoint-ORIG-GUID: SgN4q38vRuEKd4h7M3K22hnlnSMiKccG X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIyMDA3NCBTYWx0ZWRfX1Tkds9eFtNjL Fs8oWgo61ESGn30FVNxH/tRR2lfRQZnU1s8RNyznCcW3xxxIAz4AGfFEEFO6dN201k4L0QqBy4H 0z0MXcH3UBMf9SEcQWtWMy4ft8QUpe4= X-Authority-Analysis: v=2.4 cv=NovhtcdJ c=1 sm=1 tr=0 ts=6a38e665 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=FjpnKfaMezcxXxbuv6AA:9 a=CjuIK1q_8ugA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIyMDA3NCBTYWx0ZWRfX+MfVcyzINSvO f+v1XPdmZKWW3MO7b2oRrSTIg+OMTh3Ex6bVWD9efif0XiDNJJHlh3GBftEzkF5s1CUfsuvECbz N2Ypf+zf/FfG5UEoPs1IejxVbMrvElC7g+9MFjhjeIgbq7CNDqxaveBC1l4G7NKBqbXhRC7uRMJ JI4LI9sUFnfFhqxIQhe9F3U1IYFut3/vvr/dGAWzwboBiEw/TMqHmq5/05g0omseJXUv42PGnfl kZ3BFMkpfJPPgbYwr7aCwJXtqlHDj+pIueTmLWCkYgcPuT3diOrn93tYtDtq5J9u13raxPGC34h qc08jcrOP4yB4kM7bX3WOq35LIOmVvOmyPmXqgmCQdv5Ap3+3G5sRELSKv2WFR7P3Md9g327jqk KqG6ygz//ybxkPQKdH+X7vngjdf9sDiCXERNxj58OcRBcdlR8oYezaqzHmRp5cDrIJeYdX8GIVm CT2CihcDHPeRtOlbtOg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-22_01,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606220074 On Thu, Jun 18, 2026 at 03:04:57PM +0200, Konrad Dybcio wrote: > On 6/8/26 11:47 PM, Abhinaba Rakshit wrote: > > Qualcomm Inline Crypto Engine (ICE) platform driver now, supports > > an optional OPP-table. > > > > Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco > > platform. > > > > Signed-off-by: Abhinaba Rakshit > > --- > > arch/arm64/boot/dts/qcom/monaco.dtsi | 37 ++++++++++++++++++++++++++++++++++++ > > 1 file changed, 37 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi > > index a1b6e6211b84d0d5008231c55613a0ccd61b9450..d9298d8b7874b8669b2cded2a28a99dce6eadbda 100644 > > --- a/arch/arm64/boot/dts/qcom/monaco.dtsi > > +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi > > @@ -2742,6 +2742,27 @@ ice: crypto@1d88000 { > > clock-names = "core", > > "iface"; > > power-domains = <&gcc GCC_UFS_PHY_GDSC>; > > + > > + operating-points-v2 = <&ice_opp_table>; > > + > > + ice_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-75000000 { > > + opp-hz = /bits/ 64 <75000000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > + > > + opp-201600000 { > > + opp-hz = /bits/ 64 <201600000>; > > + required-opps = <&rpmhpd_opp_svs_l1>; > > + }; > > Since 75 MHz and 201.6 Mhz require the same power level, is the former > OPP any useful? Yes, both use the same power requirements. However recommended by the ICE team, the DT should include all opp/freq supported by the hardware. Abhinaba Rakshit