Re: [PATCH v2 1/4] mmc: sdhci: fix timing selection for 1-bit bus width

Frank Li
2026-03-03T21:02:13Z

From: Frank Li (AI-BOT) <frank.li@nxp.com>

Subject: Re: [PATCH v2 1/4] mmc: sdhci: fix timing selection for 1-bit bus width

> - if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
> + if (host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA) {
> + host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
> + SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_HS400);
> + mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400 | MMC_CAP2_HS400_ES);
> + mmc->caps &= ~(MMC_CAP_DDR | MMC_CAP_UHS);
> + } else {
> mmc->caps |= MMC_CAP_4_BIT_DATA;
> + }

The logic inversion here is correct and the fix addresses the root cause
per JEDEC spec. However, consider whether clearing MMC_CAP_UHS is
necessary—UHS modes require 4-bit width anyway, so this may be redundant
with the SDR104/SDR50/DDR50 clears. If intentional for belt-and-suspenders
safety, add a brief comment explaining why.

Also verify that mmc pointer is always valid at this point in
sdhci_setup_host(). If there's any path where mmc could be NULL, the
new code will crash.

AI bot review and may be useless.