RE: [EXT] Re: [PATCH v2 1/4] mmc: sdhci: fix timing selection for 1-bit bus width

Luke Wang
2026-03-11T09:19:09Z

> -----Original Message-----
> From: Adrian Hunter <adrian.hunter@intel.com>
> Sent: Wednesday, March 11, 2026 5:05 PM
> To: Luke Wang <ziniu.wang_1@nxp.com>; ulf.hansson@linaro.org; Bough
> Chen <haibo.chen@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; imx@lists.linux.dev; linux-
> mmc@vger.kernel.org; dl-S32 <S32@nxp.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: [EXT] Re: [PATCH v2 1/4] mmc: sdhci: fix timing selection for 1-bit
> bus width
>
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>
> On 03/03/2026 12:50, ziniu.wang_1@nxp.com wrote:
> > From: Luke Wang <ziniu.wang_1@nxp.com>
> >
> > When 1-bit bus width is used with HS200/HS400 capabilities set,
> > mmc_select_hs200() returns 0 without actually switching. This
> > causes mmc_select_timing() to skip mmc_select_hs(), leaving eMMC
> > in legacy mode (26MHz) instead of High Speed SDR (52MHz).
> >
> > Per JEDEC eMMC spec section 5.3.2, 1-bit mode supports High Speed
> > SDR. Drop incompatible HS200/HS400/UHS/DDR caps early so timing
> > selection falls through to mmc_select_hs() correctly.
> >
>
> Fixes: f2119df6b7646 ("mmc: sd: add support for signal voltage switch
> procedure")
>
> > Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
> > ---
> > drivers/mmc/host/sdhci.c | 8 +++++++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index b1a3cd574c84..3e163f14a640 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -4539,8 +4539,14 @@ int sdhci_setup_host(struct sdhci_host *host)
> > * their platform code before calling sdhci_add_host(), and we
> > * won't assume 8-bit width for hosts without that CAP.
> > */
> > - if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
> > + if (host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA) {
> > + host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_SDR50 |
> > + SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_HS400);
>
> SDHCI_SUPPORT_HS400 is non-standard. Hence the check for
> SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 is needed:

Got it, thanks for the explanation. I'll keep the check in v3.

>
> host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
> SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
> if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400)
> host->caps1 &= ~SDHCI_SUPPORT_HS400;
>
> > + mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400 |
> MMC_CAP2_HS400_ES);
> > + mmc->caps &= ~(MMC_CAP_DDR | MMC_CAP_UHS);
> > + } else {
> > mmc->caps |= MMC_CAP_4_BIT_DATA;
> > + }
> >
> > if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
> > mmc->caps &= ~MMC_CAP_CMD23;