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Mon, 29 Dec 2025 05:58:05 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5BT5w4qd021213 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Dec 2025 05:58:04 GMT Received: from [10.151.36.184] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Sun, 28 Dec 2025 21:58:02 -0800 Message-ID: Date: Mon, 29 Dec 2025 11:27:48 +0530 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode To: Eric Biggers CC: , , , , , References: <20251224101050.3497746-1-quic_mdalam@quicinc.com> <20251228202057.GB2431@quark> Content-Language: en-US From: Md Sadre Alam In-Reply-To: <20251228202057.GB2431@quark> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UbVpXeSvbPH-gcrPkCRanGrhasGVYFBH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI5MDA1MiBTYWx0ZWRfXzdrUrsrWFhOI f0yYGnQTHvmOBfMX1DiBm95DFX+g6KDu6axT0+avBGlubfcRyyij0sxBDhM+eoB9Q2i29wvCeQ5 MBmtMvjsZlcoybzB6WV9+FVpIc++3mwfO0Ewu8WznPUTbzpABZR3G9TsIhsGRZyK0D5qft92i30 EXglw/KxOJGQOu9aOxKHeCe7/DNLNUJ6KRoBf+8Km6fcDLjGSRHzMHu5walYRueQ8XFWIBHuuQq 87Iek2T6HUaah9rDW4tEG5WPXXEp2tSRD2zo3t3StLNO50aZELEir/eJmTynDGhCy2gC7MVdFsD ++4UgrcWcXqxpbBDwDCSamnLCWs9KJ1IlNVlaTqaDDgktcP9HpjPGT2L+WE2ppXV/j6VI4V9U50 5MkSS9dDeYQyeFpulVDHRcbgZ03zIlYzwoHF2WNYRLdtMGalvFj+oTq301ABkkrrxU6/8TgWmEr ee27q36us5+8N5UOi6A== X-Proofpoint-ORIG-GUID: UbVpXeSvbPH-gcrPkCRanGrhasGVYFBH X-Authority-Analysis: v=2.4 cv=Y+L1cxeN c=1 sm=1 tr=0 ts=6952186d cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=KkW5yuFp_KLN4ZHH0lMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-29_01,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512290052 Hi, On 12/29/2025 1:50 AM, Eric Biggers wrote: > On Wed, Dec 24, 2025 at 03:40:50PM +0530, Md Sadre Alam wrote: >> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode >> instead of Command Queue Engine (CQE) mode for platform-specific >> requirements or compatibility reasons. Introduce a host-level quirk >> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE >> to function through the legacy request path. >> >> When the device tree omits the "supports-cqe" property, the driver sets >> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card >> initialization. This ensures that even CQE-capable hardware falls back >> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is >> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to >> force the fallback. Other ops are left NULL for safe defaults. >> >> For builds without CONFIG_MMC_CRYPTO, the driver uses standard >> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization. >> >> This allows platforms to forcefully opt out of CQE usage and ensure ICE >> operates reliably in legacy mode, providing stable crypto operations >> without command queuing complexity. >> >> Signed-off-by: Md Sadre Alam > > I'm confused. If CQE isn't supported by the hardware, surely it would > make more sense for the driver to not advertise the host as being > CQE-capable at all? This patch seems to introduce an ambiguous middle > ground, where the host is CQE-capable but not really. The hardware supports CQE: both the SDHCI‑MSM controller and the eMMC device are CQE‑capable. The issue arises because the ICE driver is tightly coupled with the CMDQ (CQE) driver code, creating a dependency. If the host forcefully disables CMDQ, ICE becomes unusable under the current design. This patch allows ICE to remain functional via the legacy SDHCI path even when CMDQ is explicitly disabled by the host. Thanks, Alam.