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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b04110b94cbsm1003115266b.93.2025.09.03.09.12.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Sep 2025 09:13:01 -0700 (PDT) Message-ID: Date: Wed, 3 Sep 2025 18:12:59 +0200 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration To: Dmitry Baryshkov , Wasim Nazir Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Richard Cochran , kernel@oss.qualcomm.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, Monish Chunara References: <20250826-lemans-evk-bu-v1-0-08016e0d3ce5@oss.qualcomm.com> <20250826-lemans-evk-bu-v1-2-08016e0d3ce5@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODMwMDAxOSBTYWx0ZWRfX2uqxVrDRsZXX XOELrAQABo7EbCU39FZtgzdIfAnsQ7059BsFvfB4jiBWg+pui+EiIEvAEyoEQuuQZKDglzHYam3 ClDXdEkWqyDco8akTVBjpuMdCXVNt+Fd0RG00Z4Yotq9OGKmmpuTwuganspLePNUX+rboeUjcPk PK89RiQRV7bHNLLP3+AxQt6F6jYWq0aB2WGVTFOYYwOAdSPy32cznHcbL/+iZmtfNEYMpjNoLzn PCdXQLXr3wCnlv1scEvYPSyEyq+6QMVWk0wdbKrv18aqWficFeSb+NqMRsVJd45X2/awPDq0z6H VHE7vnqpkfUQv6d9Mb7uopu63C5J01tPgwUGTr6rVEi1t0CHAiOW3iHzzL+KCUt8yrrNE+yzjEC I5oAnXVq X-Proofpoint-GUID: w1zkAyFeZladnROsfqMsdKZKlDOnag9- X-Proofpoint-ORIG-GUID: w1zkAyFeZladnROsfqMsdKZKlDOnag9- X-Authority-Analysis: v=2.4 cv=PNkP+eqC c=1 sm=1 tr=0 ts=68b86910 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=onm5DRxEkm4ScgEcFVIA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-03_08,2025-08-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 suspectscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508300019 On 8/27/25 3:20 AM, Dmitry Baryshkov wrote: > On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote: >> From: Monish Chunara >> >> Introduce the SDHC v5 controller node for the Lemans platform. >> This controller supports either eMMC or SD-card, but only one >> can be active at a time. SD-card is the preferred configuration >> on Lemans targets, so describe this controller. >> >> Define the SDC interface pins including clk, cmd, and data lines >> to enable proper communication with the SDHC controller. >> >> Signed-off-by: Monish Chunara >> Co-developed-by: Wasim Nazir >> Signed-off-by: Wasim Nazir >> --- >> arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 70 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >> index 99a566b42ef2..a5a3cdba47f3 100644 >> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >> @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint { >> }; >> }; >> >> + sdhc: mmc@87c4000 { >> + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0x0 0x087c4000 0x0 0x1000>; >> + >> + interrupts = , >> + ; >> + interrupt-names = "hc_irq", "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, >> + <&gcc GCC_SDCC1_APPS_CLK>; >> + clock-names = "iface", "core"; >> + >> + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>, >> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>; >> + interconnect-names = "sdhc-ddr", "cpu-sdhc"; >> + >> + iommus = <&apps_smmu 0x0 0x0>; >> + dma-coherent; >> + >> + resets = <&gcc GCC_SDCC1_BCR>; >> + >> + no-sdio; >> + no-mmc; >> + bus-width = <4>; > > This is the board configuration, it should be defined in the EVK DTS. Unless the controller is actually incapable of doing non-SDCards But from the limited information I can find, this one should be able to do both Konrad