[PATCH v1 0/2] eMMC RST_N support on BlueField-2 SoC

[PATCH v1 0/2] eMMC RST_N support on BlueField-2 SoC

[Liming Sun]

The dw_mmc driver supports eMMC RST_N recovery flow but doesn't work
on BlueField-2 SoC because the RST_N register is designed as secure
register. This patch series enhance the dw_mci_drv_data structure to
support platform-specific hw_reset(), then implements this function in
dw_mmc-bluefield.c to support RST_N via SMC call.

Liming Sun (2):
  dw_mmc: support platform specific hw_reset()
  dw_mmc-bluefield: add hw_reset() support

 drivers/mmc/host/dw_mmc-bluefield.c | 18 +++++++++++++++++-
 drivers/mmc/host/dw_mmc.c           |  6 ++++++
 drivers/mmc/host/dw_mmc.h           |  2 ++
 3 files changed, 25 insertions(+), 1 deletion(-)

-- 
2.30.1

[PATCH v1 1/2] dw_mmc: support platform specific hw_reset()

[Liming Sun]

This commit enhances the dw_mmc driver to support platform specific
hw_reset().

Reviewed-by: David Thompson <davthompson@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
---
 drivers/mmc/host/dw_mmc.c | 6 ++++++
 drivers/mmc/host/dw_mmc.h | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 8e2d676b9239..2d72da03fdfd 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1617,6 +1617,7 @@ static void dw_mci_hw_reset(struct mmc_host *mmc)
 {
 	struct dw_mci_slot *slot = mmc_priv(mmc);
 	struct dw_mci *host = slot->host;
+	const struct dw_mci_drv_data *drv_data = host->drv_data;
 	int reset;
 
 	if (host->use_dma == TRANS_MODE_IDMAC)
@@ -1626,6 +1627,11 @@ static void dw_mci_hw_reset(struct mmc_host *mmc)
 				     SDMMC_CTRL_FIFO_RESET))
 		return;
 
+	if (drv_data && drv_data->hw_reset) {
+		drv_data->hw_reset(host);
+		return;
+	}
+
 	/*
 	 * According to eMMC spec, card reset procedure:
 	 * tRstW >= 1us:   RST_n pulse width
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 4ed81f94f7ca..1b86531a485c 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -565,6 +565,7 @@ struct dw_mci_slot {
  * @execute_tuning: implementation specific tuning procedure.
  * @set_data_timeout: implementation specific timeout.
  * @get_drto_clks: implementation specific cycle count for data read timeout.
+ * @hw_reset: implementation specific HW reset.
  *
  * Provide controller implementation specific extensions. The usage of this
  * data structure is fully optional and usage of each member in this structure
@@ -585,5 +586,6 @@ struct dw_mci_drv_data {
 	void		(*set_data_timeout)(struct dw_mci *host,
 					  unsigned int timeout_ns);
 	u32		(*get_drto_clks)(struct dw_mci *host);
+	void		(*hw_reset)(struct dw_mci *host);
 };
 #endif /* _DW_MMC_H_ */
-- 
2.30.1

[PATCH v1 2/2] dw_mmc-bluefield: add hw_reset() support

[Liming Sun]

The eMMC RST_N register is implemented as secure register on
BlueField SoC and controlled by ATF. This commit sends SMC call
to ATF for the eMMC HW reset.

Reviewed-by: David Thompson <davthompson@nvidia.com>
Signed-off-by: Liming Sun <limings@nvidia.com>
---
 drivers/mmc/host/dw_mmc-bluefield.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/dw_mmc-bluefield.c b/drivers/mmc/host/dw_mmc-bluefield.c
index 4747e5698f48..24e0b604b405 100644
--- a/drivers/mmc/host/dw_mmc-bluefield.c
+++ b/drivers/mmc/host/dw_mmc-bluefield.c
@@ -3,6 +3,7 @@
  * Copyright (C) 2018 Mellanox Technologies.
  */
 
+#include <linux/arm-smccc.h>
 #include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/mmc/host.h>
@@ -20,6 +21,9 @@
 #define BLUEFIELD_UHS_REG_EXT_SAMPLE	2
 #define BLUEFIELD_UHS_REG_EXT_DRIVE	4
 
+/* SMC call for RST_N */
+#define BLUEFIELD_SMC_SET_EMMC_RST_N	0x82000007
+
 static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 {
 	u32 reg;
@@ -34,8 +38,20 @@ static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 	mci_writel(host, UHS_REG_EXT, reg);
 }
 
+static void dw_mci_bluefield_hw_reset(struct dw_mci *host)
+{
+		struct arm_smccc_res res = { 0 };
+
+		arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0,
+			      &res);
+
+		if (res.a0)
+			pr_err("RST_N failed.\n");
+}
+
 static const struct dw_mci_drv_data bluefield_drv_data = {
-	.set_ios		= dw_mci_bluefield_set_ios
+	.set_ios		= dw_mci_bluefield_set_ios,
+	.hw_reset		= dw_mci_bluefield_hw_reset
 };
 
 static const struct of_device_id dw_mci_bluefield_match[] = {
-- 
2.30.1

Re: [PATCH v1 2/2] dw_mmc-bluefield: add hw_reset() support

[Ulf Hansson]

On Thu, 13 Jun 2024 at 00:53, Liming Sun <limings@nvidia.com> wrote:
>
> The eMMC RST_N register is implemented as secure register on
> BlueField SoC and controlled by ATF. This commit sends SMC call
> to ATF for the eMMC HW reset.

Just to make sure I get this correctly. Asserting the eMMC reset line
is managed through a secure register? Or is this about resetting the
eMMC controller?

No matter what, it looks to me that it should be implemented as a
reset provider.

Kind regards
Uffe

>
> Reviewed-by: David Thompson <davthompson@nvidia.com>
> Signed-off-by: Liming Sun <limings@nvidia.com>
> ---
>  drivers/mmc/host/dw_mmc-bluefield.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-bluefield.c b/drivers/mmc/host/dw_mmc-bluefield.c
> index 4747e5698f48..24e0b604b405 100644
> --- a/drivers/mmc/host/dw_mmc-bluefield.c
> +++ b/drivers/mmc/host/dw_mmc-bluefield.c
> @@ -3,6 +3,7 @@
>   * Copyright (C) 2018 Mellanox Technologies.
>   */
>
> +#include <linux/arm-smccc.h>
>  #include <linux/bitfield.h>
>  #include <linux/bitops.h>
>  #include <linux/mmc/host.h>
> @@ -20,6 +21,9 @@
>  #define BLUEFIELD_UHS_REG_EXT_SAMPLE   2
>  #define BLUEFIELD_UHS_REG_EXT_DRIVE    4
>
> +/* SMC call for RST_N */
> +#define BLUEFIELD_SMC_SET_EMMC_RST_N   0x82000007
> +
>  static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>  {
>         u32 reg;
> @@ -34,8 +38,20 @@ static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios *ios)
>         mci_writel(host, UHS_REG_EXT, reg);
>  }
>
> +static void dw_mci_bluefield_hw_reset(struct dw_mci *host)
> +{
> +               struct arm_smccc_res res = { 0 };
> +
> +               arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0,
> +                             &res);
> +
> +               if (res.a0)
> +                       pr_err("RST_N failed.\n");
> +}
> +
>  static const struct dw_mci_drv_data bluefield_drv_data = {
> -       .set_ios                = dw_mci_bluefield_set_ios
> +       .set_ios                = dw_mci_bluefield_set_ios,
> +       .hw_reset               = dw_mci_bluefield_hw_reset
>  };
>
>  static const struct of_device_id dw_mci_bluefield_match[] = {
> --
> 2.30.1
>

RE: [PATCH v1 2/2] dw_mmc-bluefield: add hw_reset() support

[Liming Sun]

Thanks, Uffe. Please see some comments/questions below.

> -----Original Message-----
> From: Ulf Hansson <ulf.hansson@linaro.org>
> Sent: Thursday, June 20, 2024 10:22 AM
> To: Liming Sun <limings@nvidia.com>
> Cc: Adrian Hunter <adrian.hunter@intel.com>; David Thompson
> <davthompson@nvidia.com>; linux-mmc@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH v1 2/2] dw_mmc-bluefield: add hw_reset() support
> 
> On Thu, 13 Jun 2024 at 00:53, Liming Sun <limings@nvidia.com> wrote:
> >
> > The eMMC RST_N register is implemented as secure register on
> > BlueField SoC and controlled by ATF. This commit sends SMC call
> > to ATF for the eMMC HW reset.
> 
> Just to make sure I get this correctly. Asserting the eMMC reset line
> is managed through a secure register? Or is this about resetting the
> eMMC controller?

Yes, asserting the eMMC reset line (RST_N) is managed through a secure register.
It's the same register but implemented as secure and can only be written in ATF.

> 
> No matter what, it looks to me that it should be implemented as a
> reset provider.

Do you mean that ' hw_reset()' should implement the whole function instead of just the toggling the RST_N?

> 
> Kind regards
> Uffe
> 
> >
> > Reviewed-by: David Thompson <davthompson@nvidia.com>
> > Signed-off-by: Liming Sun <limings@nvidia.com>
> > ---
> >  drivers/mmc/host/dw_mmc-bluefield.c | 18 +++++++++++++++++-
> >  1 file changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mmc/host/dw_mmc-bluefield.c
> b/drivers/mmc/host/dw_mmc-bluefield.c
> > index 4747e5698f48..24e0b604b405 100644
> > --- a/drivers/mmc/host/dw_mmc-bluefield.c
> > +++ b/drivers/mmc/host/dw_mmc-bluefield.c
> > @@ -3,6 +3,7 @@
> >   * Copyright (C) 2018 Mellanox Technologies.
> >   */
> >
> > +#include <linux/arm-smccc.h>
> >  #include <linux/bitfield.h>
> >  #include <linux/bitops.h>
> >  #include <linux/mmc/host.h>
> > @@ -20,6 +21,9 @@
> >  #define BLUEFIELD_UHS_REG_EXT_SAMPLE   2
> >  #define BLUEFIELD_UHS_REG_EXT_DRIVE    4
> >
> > +/* SMC call for RST_N */
> > +#define BLUEFIELD_SMC_SET_EMMC_RST_N   0x82000007
> > +
> >  static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios
> *ios)
> >  {
> >         u32 reg;
> > @@ -34,8 +38,20 @@ static void dw_mci_bluefield_set_ios(struct dw_mci
> *host, struct mmc_ios *ios)
> >         mci_writel(host, UHS_REG_EXT, reg);
> >  }
> >
> > +static void dw_mci_bluefield_hw_reset(struct dw_mci *host)
> > +{
> > +               struct arm_smccc_res res = { 0 };
> > +
> > +               arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0,
> 0, 0,
> > +                             &res);
> > +
> > +               if (res.a0)
> > +                       pr_err("RST_N failed.\n");
> > +}
> > +
> >  static const struct dw_mci_drv_data bluefield_drv_data = {
> > -       .set_ios                = dw_mci_bluefield_set_ios
> > +       .set_ios                = dw_mci_bluefield_set_ios,
> > +       .hw_reset               = dw_mci_bluefield_hw_reset
> >  };
> >
> >  static const struct of_device_id dw_mci_bluefield_match[] = {
> > --
> > 2.30.1
> >

Re: [PATCH v1 2/2] dw_mmc-bluefield: add hw_reset() support

[Ulf Hansson]

On Tue, 25 Jun 2024 at 21:13, Liming Sun <limings@nvidia.com> wrote:
>
> Thanks, Uffe. Please see some comments/questions below.
>
> > -----Original Message-----
> > From: Ulf Hansson <ulf.hansson@linaro.org>
> > Sent: Thursday, June 20, 2024 10:22 AM
> > To: Liming Sun <limings@nvidia.com>
> > Cc: Adrian Hunter <adrian.hunter@intel.com>; David Thompson
> > <davthompson@nvidia.com>; linux-mmc@vger.kernel.org; linux-
> > kernel@vger.kernel.org
> > Subject: Re: [PATCH v1 2/2] dw_mmc-bluefield: add hw_reset() support
> >
> > On Thu, 13 Jun 2024 at 00:53, Liming Sun <limings@nvidia.com> wrote:
> > >
> > > The eMMC RST_N register is implemented as secure register on
> > > BlueField SoC and controlled by ATF. This commit sends SMC call
> > > to ATF for the eMMC HW reset.
> >
> > Just to make sure I get this correctly. Asserting the eMMC reset line
> > is managed through a secure register? Or is this about resetting the
> > eMMC controller?
>
> Yes, asserting the eMMC reset line (RST_N) is managed through a secure register.
> It's the same register but implemented as secure and can only be written in ATF.

Okay, thanks for clarifying!

>
> >
> > No matter what, it looks to me that it should be implemented as a
> > reset provider.
>
> Do you mean that ' hw_reset()' should implement the whole function instead of just the toggling the RST_N?

Sorry, for being very unclear from my side! I was thinking of
modelling it as a GPIO pin that we can assert/deassert to manage the
reset.

However, after a second thought, it looks to me that it would be
unnecessarily complicated. That said, I decided to apply patch 1 and
patch 2, as is. While applying I took the liberty of clarifying the
commit messages a bit, please let me know if it doesn't look okay to
you.

Kind regards
Uffe



>
> >
> > Kind regards
> > Uffe
> >
> > >
> > > Reviewed-by: David Thompson <davthompson@nvidia.com>
> > > Signed-off-by: Liming Sun <limings@nvidia.com>
> > > ---
> > >  drivers/mmc/host/dw_mmc-bluefield.c | 18 +++++++++++++++++-
> > >  1 file changed, 17 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/mmc/host/dw_mmc-bluefield.c
> > b/drivers/mmc/host/dw_mmc-bluefield.c
> > > index 4747e5698f48..24e0b604b405 100644
> > > --- a/drivers/mmc/host/dw_mmc-bluefield.c
> > > +++ b/drivers/mmc/host/dw_mmc-bluefield.c
> > > @@ -3,6 +3,7 @@
> > >   * Copyright (C) 2018 Mellanox Technologies.
> > >   */
> > >
> > > +#include <linux/arm-smccc.h>
> > >  #include <linux/bitfield.h>
> > >  #include <linux/bitops.h>
> > >  #include <linux/mmc/host.h>
> > > @@ -20,6 +21,9 @@
> > >  #define BLUEFIELD_UHS_REG_EXT_SAMPLE   2
> > >  #define BLUEFIELD_UHS_REG_EXT_DRIVE    4
> > >
> > > +/* SMC call for RST_N */
> > > +#define BLUEFIELD_SMC_SET_EMMC_RST_N   0x82000007
> > > +
> > >  static void dw_mci_bluefield_set_ios(struct dw_mci *host, struct mmc_ios
> > *ios)
> > >  {
> > >         u32 reg;
> > > @@ -34,8 +38,20 @@ static void dw_mci_bluefield_set_ios(struct dw_mci
> > *host, struct mmc_ios *ios)
> > >         mci_writel(host, UHS_REG_EXT, reg);
> > >  }
> > >
> > > +static void dw_mci_bluefield_hw_reset(struct dw_mci *host)
> > > +{
> > > +               struct arm_smccc_res res = { 0 };
> > > +
> > > +               arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0,
> > 0, 0,
> > > +                             &res);
> > > +
> > > +               if (res.a0)
> > > +                       pr_err("RST_N failed.\n");
> > > +}
> > > +
> > >  static const struct dw_mci_drv_data bluefield_drv_data = {
> > > -       .set_ios                = dw_mci_bluefield_set_ios
> > > +       .set_ios                = dw_mci_bluefield_set_ios,
> > > +       .hw_reset               = dw_mci_bluefield_hw_reset
> > >  };
> > >
> > >  static const struct of_device_id dw_mci_bluefield_match[] = {
> > > --
> > > 2.30.1
> > >