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Wed, 14 Apr 2021 08:49:49 +0000 Subject: Re: Question on HS400 timing sequence To: Adrian Hunter Cc: linux-mmc@vger.kernel.org, Jasbeer.Singh@amd.com, Sudheesh.Mavila@amd.com References: <0c27d8cd-a102-8daa-dcd4-57647fff0f25@intel.com> From: "Shah, Nehal-bakulchandra" Message-ID: Date: Wed, 14 Apr 2021 14:19:38 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.9.1 In-Reply-To: <0c27d8cd-a102-8daa-dcd4-57647fff0f25@intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Content-Language: en-US X-Originating-IP: [165.204.159.242] X-ClientProxiedBy: PN1PR0101CA0011.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:e::21) To MN2PR12MB3453.namprd12.prod.outlook.com (2603:10b6:208:c3::18) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from [172.31.35.91] (165.204.159.242) by PN1PR0101CA0011.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4042.16 via Frontend Transport; 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(Note: This step may be skipped if changes of driver strength is not needed) >> 5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD register to the appropriate driver strength for HS400 operation and set the “Timing Interface” >> parameter to 0x2 to switch to HS200 mode. >> 6) Perform the Tuning Process at the HS400 target operating frequency (Note: tuning process in HS200 mode is required to synchronize the command response on the CMD line to CLK for HS400 operation). >> 7) After the Tuning Process has completed, set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to 0x3 to switch to HS400 mode. >> >> But in case of JESD84-B51 spec  EMMC 5.1, HS400 timing sequence is following >> >> 1 )Initialize device with “Backward Compatible Timings”, >> 2) Select the device with CMD7, >> 3) Read the DEVICE_TYPE [196] field of the Extended CSD register to validate whether the device >> supports HS400, >> 4) Read the DRIVER_STRENGTH [197] field of the Extended CSD register to find the supported >> device Driver Strengths, >> NOTE This step may be skipped if changes of driver strength is not needed. >> 5) Set the “Selected Driver Strength” parameter in the HS_TIMING [185] field of the Extended CSD >> register to the appropriate driver strength for HS400 operation and set the “Timing Interface” >> parameter to 0x2 to switch to HS200 mode, >> 6) Perform the Tuning Process at the HS400 target operating frequency, >> NOTE Tuning process in HS200 mode is required to synchronize the command response on the CMD line to >> CLK for HS400 operation. >> 7) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to >> 0x1 to switch to High Speed mode and then set the clock frequency to a value not greater than 52 >> MHz, >> 8) Set BUS_WIDTH[183] to 0x06 to select the dual data rate x8 bus mode, >> 9) Set the “Timing Interface” parameter in the HS_TIMING [185] field of the Extended CSD register to >> 0x3 to switch to HS400 mode. >> >> So basically in case EMMC5.1 for HS400 mode selection, there is some difference after tuning. However driver >> existing driver always follow spec of EMMC5.1 . Is there any specific reason for the same? So on our some AMD platforms >> with EMMC5.0 driver is failing but if we modify the driver as per EMCC5.0 sequencing it is passing. So can you please provide >> your inputs? > Hi Nehal Shah > > There was another specification between those two, namely JESD84-B50.1 eMMC 5.01 which has the same procedure as eMMC 5.1 > > AFAICT the 5.0 text was almost immediately "clarified" in 5.01 to match the 5.1 text. > > So we have only 1 HS400 sequence. But some host controllers do have issues, which is why there are additional hooks like ->hs400_downgrade() and ->hs400_prepare_ddr() Sure we will try the same. > Regards > Adrian Regards Nehal