[PATCH v2 0/7] arm64: Add initial support for NXP S32N79 SoC

[PATCH v2 0/7] arm64: Add initial support for NXP S32N79 SoC

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

This series introduces initial device tree support for the NXP S32N79
automotive SoC and its Reference Design Board (RDB).

The S32N79 is an automotive-grade system-on-chip featuring eight Arm
Cortex-A78AE cores organized in four dual-core clusters. It is designed
for high-performance networking and gateway applications vehicle
architectures [1]

Hardware features included in this initial support:
- 8x Arm Cortex-A78AE cores (4 clusters of 2 cores each)
- 32GB DRAM Memory. 28GB are usable and 4GB are reserved for ECC logic
- Three-level cache hierarchy (L1/L2 per core, L3 per cluster)
- GICv3 interrupt controller with ITS
- SMMUv3 for IOMMU support
- Generic Timer
- IRQ steering controller
- PL011 UART controllers
- uSDHC controller

This series also includes the necessary driver updates:
- sdhci-esdhc-imx: Add S32N79 uSDHC controller support
- irq-imx-irqsteer: Add S32N79 IRQ steering support
- irqchip Kconfig: Add ARCH_S32 dependency for IMX_IRQSTEER

Future patches will add support for additional peripherals such as
networking controllers, PCIe, and other IP blocks.

[1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N

v2 -> v1
- added driver changes required for S32N79 uSDHC support
- added driver changes required for S32N79 IRQ_STEER support
- updated commit message for uSDHC dt-bindings
- implemented fixes for 'dt-format' tool findings on newly added S32N79 dts files

Ciprian Marian Costea (7):
  dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support
  dt-bindings: mmc: fsl-imx-esdhc: add S32N79 support
  dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board
  mmc: sdhci-esdhc-imx: add NXP S32N79 support
  irqchip/imx-irqsteer: add NXP S32N79 support
  irqchip: add ARCH_S32 dependency to Kconfig
  arm64: dts: freescale: Add minimal support for S32N79

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 .../interrupt-controller/fsl,irqsteer.yaml    |   1 +
 .../bindings/mmc/fsl-imx-esdhc.yaml           |   1 +
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 arch/arm64/boot/dts/freescale/s32n79-rdb.dts  |  70 ++++
 arch/arm64/boot/dts/freescale/s32n79.dtsi     | 362 ++++++++++++++++++
 drivers/irqchip/Kconfig                       |   6 +-
 drivers/irqchip/irq-imx-irqsteer.c            |  35 +-
 drivers/mmc/host/sdhci-esdhc-imx.c            |   9 +
 9 files changed, 485 insertions(+), 6 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/s32n79-rdb.dts
 create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi

-- 
2.43.0

[PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add compatible string for the interrupt steering controller used in NXP
S32N79 SoC.

The S32N79 SoC differs from the i.MX version by not implementing the
CHANCTRL register, but otherwise maintains the same programming model and
register layout.

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
index 5c768c1e159c..caf3e4a1f26f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
@@ -22,6 +22,7 @@ properties:
               - fsl,imx94-irqsteer
               - fsl,imx95-irqsteer
           - const: fsl,imx-irqsteer
+      - const: nxp,s32n79-irqsteer
 
   reg:
     maxItems: 1
-- 
2.43.0

[PATCH v2 2/7] dt-bindings: mmc: fsl-imx-esdhc: add S32N79 support

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add compatible string "nxp,s32n79-usdhc" for the uSDHC controller found in
NXP S32N79 series automotive SoCs.

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
index b98a84f93277..014b049baeb6 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -35,6 +35,7 @@ properties:
           - fsl,imx8mm-usdhc
           - fsl,imxrt1050-usdhc
           - nxp,s32g2-usdhc
+          - nxp,s32n79-usdhc
       - items:
           - const: fsl,imx50-esdhc
           - const: fsl,imx53-esdhc
-- 
2.43.0

[PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add device tree binding documentation for the NXP S32N79 automotive SoC
and the S32N79 Reference Design Board (S32N79-RDB).

The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
cores organized for high-performance networking and gateway applications
in vehicles.

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 5716d701292c..415081423a30 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1827,6 +1827,12 @@ properties:
               - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
           - const: fsl,s32v234
 
+      - description: S32N79 based Boards
+        items:
+          - enum:
+              - nxp,s32n79-rdb
+          - const: nxp,s32n79
+
       - description: Traverse LS1088A based Boards
         items:
           - enum:
-- 
2.43.0

[PATCH v2 4/7] mmc: sdhci-esdhc-imx: add NXP S32N79 support

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add support for the uSDHC controller found in NXP S32N79 automotive SoCs.

The controller is compatible with the existing sdhci-esdhc-imx driver.

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 drivers/mmc/host/sdhci-esdhc-imx.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index a7a5df673b0f..28288fca87ff 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -321,6 +321,14 @@ static struct esdhc_soc_data usdhc_s32g2_data = {
 	.quirks = SDHCI_QUIRK_NO_LED,
 };
 
+static struct esdhc_soc_data usdhc_s32n79_data = {
+	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
+			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
+			| ESDHC_FLAG_SKIP_ERR004536,
+	.quirks = SDHCI_QUIRK_NO_LED,
+};
+
 static struct esdhc_soc_data usdhc_imx7ulp_data = {
 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
@@ -408,6 +416,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
 	{ .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, },
 	{ .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
 	{ .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
+	{ .compatible = "nxp,s32n79-usdhc", .data = &usdhc_s32n79_data, },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
-- 
2.43.0

[PATCH v2 5/7] irqchip/imx-irqsteer: add NXP S32N79 support

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add support for the interrupt steering controller found in NXP S32N79
series automotive SoCs.

The S32N79 IRQ_STEER variant differs from the i.MX version by not
implementing the CHANCTRL register. To handle this hardware difference,
introduce a device type data structure with quirks field. The
IRQSTEER_QUIRK_NO_CHANCTRL quirk skips CHANCTRL register access for S32N79
variants.

The interrupt routing functionality and register layout are otherwise
identical between the two variants.

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 drivers/irqchip/irq-imx-irqsteer.c | 35 +++++++++++++++++++++++++++---
 1 file changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/irq-imx-irqsteer.c b/drivers/irqchip/irq-imx-irqsteer.c
index 4682ce5bf8d3..82e64af87c0b 100644
--- a/drivers/irqchip/irq-imx-irqsteer.c
+++ b/drivers/irqchip/irq-imx-irqsteer.c
@@ -26,6 +26,13 @@
 
 #define CHAN_MAX_OUTPUT_INT	0xF
 
+/* SoC does not implement the CHANCTRL register */
+#define IRQSTEER_QUIRK_NO_CHANCTRL	BIT(0)
+
+struct irqsteer_devtype_data {
+	u32 quirks;
+};
+
 struct irqsteer_data {
 	void __iomem		*regs;
 	struct clk		*ipg_clk;
@@ -37,8 +44,22 @@ struct irqsteer_data {
 	struct irq_domain	*domain;
 	u32			*saved_reg;
 	struct device		*dev;
+	const struct irqsteer_devtype_data *devtype_data;
 };
 
+static const struct irqsteer_devtype_data imx_data = {
+	.quirks = 0,
+};
+
+static const struct irqsteer_devtype_data s32n79_data = {
+	.quirks = IRQSTEER_QUIRK_NO_CHANCTRL,
+};
+
+static bool irqsteer_has_chanctrl(const struct irqsteer_devtype_data *data)
+{
+	return !(data->quirks & IRQSTEER_QUIRK_NO_CHANCTRL);
+}
+
 static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
 				      unsigned long irqnum)
 {
@@ -188,6 +209,10 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	data->devtype_data = device_get_match_data(&pdev->dev);
+	if (!data->devtype_data)
+		return dev_err_probe(&pdev->dev, -ENODEV,
+				"failed to match device data\n");
 	/*
 	 * There is one output irq for each group of 64 inputs.
 	 * One register bit map can represent 32 input interrupts.
@@ -210,7 +235,8 @@ static int imx_irqsteer_probe(struct platform_device *pdev)
 	}
 
 	/* steer all IRQs into configured channel */
-	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
+	if (irqsteer_has_chanctrl(data->devtype_data))
+		writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
 
 	data->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), data->reg_num * 32,
 						&imx_irqsteer_domain_ops, data);
@@ -279,7 +305,9 @@ static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
 {
 	int i;
 
-	writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
+	if (irqsteer_has_chanctrl(data->devtype_data))
+		writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
+
 	for (i = 0; i < data->reg_num; i++)
 		writel_relaxed(data->saved_reg[i],
 			       data->regs + CHANMASK(i, data->reg_num));
@@ -319,7 +347,8 @@ static const struct dev_pm_ops imx_irqsteer_pm_ops = {
 };
 
 static const struct of_device_id imx_irqsteer_dt_ids[] = {
-	{ .compatible = "fsl,imx-irqsteer", },
+	{ .compatible = "fsl,imx-irqsteer", .data = &imx_data },
+	{ .compatible = "nxp,s32n79-irqsteer", .data = &s32n79_data },
 	{},
 };
 
-- 
2.43.0

[PATCH v2 6/7] irqchip: add ARCH_S32 dependency to Kconfig

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

IMX_IRQSTEER is also used on ARCH_S32, but only requires ARCH_MXC. This
can result in unmet dependencies when compiling strictly for ARCH_S32.
Resolve this by adding ARCH_S32 in the driver's dependencies as an
alternative.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 drivers/irqchip/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f07b00d7fef9..ad32a084afba 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -541,11 +541,11 @@ config CSKY_APB_INTC
 
 config IMX_IRQSTEER
 	bool "i.MX IRQSTEER support"
-	depends on ARCH_MXC || COMPILE_TEST
-	default ARCH_MXC
+	depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST
+	default y if ARCH_MXC || ARCH_S32
 	select IRQ_DOMAIN
 	help
-	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
+	  Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper.
 
 config IMX_INTMUX
 	bool "i.MX INTMUX support" if COMPILE_TEST
-- 
2.43.0

[PATCH v2 7/7] arm64: dts: freescale: Add minimal support for S32N79

[Ciprian Costea]

From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>

Add device tree support for the NXP S32N79 automotive SoC and the S32N79
Reference Design Board (RDB) [1].

The S32N79 features eight Arm Cortex-A78AE cores organized in four
dual-core clusters, with a three-level cache hierarchy (L1/L2 per core,
L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3
for IOMMU functionality.

On S32N79 SoC, peripherals are organized into subsystems, such as:
- CIS (Coherent Interconnect Subsystem).
- COSS (Connectivity Subsystem)
- FSS (Foundation Subsystem)

This initial support includes basic peripherals:
- GICv3, SMMUv3 from CIS Subsystem
- PL011 UARTs and IRQ steering controller from COSS Subsystem
- uSDHC from FSS Subsystem

Clock and Pin multiplexing settings for the chip are managed over SCMI.

[1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Co-developed-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Co-developed-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile       |   1 +
 arch/arm64/boot/dts/freescale/s32n79-rdb.dts |  70 ++++
 arch/arm64/boot/dts/freescale/s32n79.dtsi    | 362 +++++++++++++++++++
 3 files changed, 433 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/s32n79-rdb.dts
 create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 700bab4d3e60..e79807bf1820 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -501,4 +501,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
 dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
+dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb
 dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
new file mode 100644
index 000000000000..d13eb3a0666b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright 2026 NXP
+ *
+ * NXP S32N79 Reference Design Board (S32N79-RDB)
+ */
+
+/dts-v1/;
+#include "s32n79.dtsi"
+
+/ {
+	compatible = "nxp,s32n79-rdb", "nxp,s32n79";
+	model = "NXP S32N79-RDB";
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart5;
+		serial2 = &uart6;
+		serial3 = &uart7;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		scmi_shbuf: shm@93000000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x93000000 0x0 0x80>;
+			no-map;
+		};
+	};
+
+	memory@80000000 {
+		reg = <0x00 0x80000000 0x00 0x80000000>,
+			<0x88 0x00000000 0x03 0x40000000>,
+			<0xc0 0x00000000 0x03 0x40000000>;
+		device_type = "memory";
+	};
+};
+
+&irqsteer_coss {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&uart6 {
+	status = "okay";
+};
+
+&uart7 {
+	status = "okay";
+};
+
+&usdhc0 {
+	disable-wp;
+	no-sdio;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
new file mode 100644
index 000000000000..94ab58783fdc
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
@@ -0,0 +1,362 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * NXP S32N79 SoC
+ *
+ * Copyright 2026 NXP
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cis-bus {
+		compatible = "simple-bus";
+		ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		gic: interrupt-controller@4f200000 {
+			compatible = "arm,gic-v3";
+			reg = <0x4f200000 0x10000>, /* GIC Dist */
+			      <0x4f260000 0x100000>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* GICR (RD_base + SGI_base) */
+			ranges;
+
+			its: msi-controller@4f240000 {
+				compatible = "arm,gic-v3-its";
+				reg = <0x4f240000 0x20000>;
+				#msi-cells = <1>;
+				msi-controller;
+			};
+		};
+
+		smmu: iommu@4fc00000 {
+			compatible = "arm,smmu-v3";
+			reg = <0x4fc00000 0x200000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
+			#iommu-cells = <1>;
+			dma-coherent;
+			status = "disabled";
+		};
+	};
+
+	coss-bus {
+		compatible = "simple-bus";
+		ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
+			 <0x4e000000 0x0 0x4e000000 0x1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		uart0: serial@4a030000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x4a030000 0x1000>;
+			interrupt-parent = <&irqsteer_coss>;
+			interrupts = <264>;
+			clocks = <&clks 0x9a>, <&clks 0x9a>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart5: serial@4a060000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x4a060000 0x1000>;
+			interrupt-parent = <&irqsteer_coss>;
+			interrupts = <269>;
+			clocks = <&clks 0x9a>, <&clks 0x9a>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart6: serial@4aa30000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x4aa30000 0x1000>;
+			interrupt-parent = <&irqsteer_coss>;
+			interrupts = <270>;
+			clocks = <&clks 0x9a>, <&clks 0x9a>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart7: serial@4aa40000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x4aa40000 0x1000>;
+			interrupt-parent = <&irqsteer_coss>;
+			interrupts = <271>;
+			clocks = <&clks 0x9a>, <&clks 0x9a>;
+			clock-names = "uartclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		irqsteer_coss: interrupt-controller@4ed00000 {
+			compatible = "nxp,s32n79-irqsteer";
+			reg = <0x4ed00000 0x10000>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 0x9a>;
+			clock-names = "ipg";
+			fsl,channel = <0>;
+			fsl,num-irqs = <512>;
+			status = "disabled";
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu2>;
+				};
+
+				core1 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster2 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+			};
+
+			cluster3 {
+				core0 {
+					cpu = <&cpu6>;
+				};
+
+				core1 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+
+		l2_0: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-size = <524288>;
+			cache-unified;
+			next-level-cache = <&l3_0>;
+		};
+
+		l2_1: l2-cache1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-size = <524288>;
+			cache-unified;
+			next-level-cache = <&l3_1>;
+		};
+
+		l2_2: l2-cache2 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-size = <524288>;
+			cache-unified;
+			next-level-cache = <&l3_2>;
+		};
+
+		l2_3: l2-cache3 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
+			cache-size = <524288>;
+			cache-unified;
+			next-level-cache = <&l3_3>;
+		};
+
+		l3_0: l3-cache0 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-size = <1048576>;
+			cache-unified;
+		};
+
+		l3_1: l3-cache1 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-size = <1048576>;
+			cache-unified;
+		};
+
+		l3_2: l3-cache2 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-size = <1048576>;
+			cache-unified;
+		};
+
+		l3_3: l3-cache3 {
+			compatible = "cache";
+			cache-level = <3>;
+			cache-line-size = <64>;
+			cache-sets = <1024>;
+			cache-size = <1048576>;
+			cache-unified;
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x0>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_0>;
+		};
+
+		cpu2: cpu@10000 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x10000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu3: cpu@10100 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x10100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_1>;
+		};
+
+		cpu4: cpu@20000 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x20000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_2>;
+		};
+
+		cpu5: cpu@20100 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x20100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_2>;
+		};
+
+		cpu6: cpu@30000 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x30000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_3>;
+		};
+
+		cpu7: cpu@30100 {
+			compatible = "arm,cortex-a78ae";
+			reg = <0x30100>;
+			device_type = "cpu";
+			enable-method = "psci";
+			next-level-cache = <&l2_3>;
+		};
+	};
+
+	firmware {
+		psci {
+			compatible = "arm,psci-1.0";
+			method = "smc";
+		};
+
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			shmem = <&scmi_shbuf>;
+			arm,smc-id = <0xc20000fe>;
+			status = "okay";
+
+			clks: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+	};
+
+	fss-bus {
+		compatible = "simple-bus";
+		ranges = <0x5b490000 0x0 0x5b490000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		usdhc0: mmc@5b490000 {
+			compatible = "nxp,s32n79-usdhc";
+			reg = <0x5b490000 0x1000>;
+			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>;
+			clock-names = "ipg", "ahb", "per";
+			bus-width = <8>;
+			status = "disabled";
+		};
+	};
+
+	pmu: pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+};
-- 
2.43.0

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Frank Li]

On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add device tree binding documentation for the NXP S32N79 automotive SoC
> and the S32N79 Reference Design Board (S32N79-RDB).
>
> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
> cores organized for high-performance networking and gateway applications
> in vehicles.
>
> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 5716d701292c..415081423a30 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1827,6 +1827,12 @@ properties:
>                - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>            - const: fsl,s32v234
>
> +      - description: S32N79 based Boards
> +        items:
> +          - enum:
> +              - nxp,s32n79-rdb
> +          - const: nxp,s32n79
> +

can you put after S32G3 based Boards

Frank

>        - description: Traverse LS1088A based Boards
>          items:
>            - enum:
> --
> 2.43.0
>

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Ciprian Marian Costea]

On 2/25/2026 5:21 PM, Frank Li wrote:
> On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add device tree binding documentation for the NXP S32N79 automotive SoC
>> and the S32N79 Reference Design Board (S32N79-RDB).
>>
>> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
>> cores organized for high-performance networking and gateway applications
>> in vehicles.
>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>> index 5716d701292c..415081423a30 100644
>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>> @@ -1827,6 +1827,12 @@ properties:
>>                 - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>>             - const: fsl,s32v234
>>
>> +      - description: S32N79 based Boards
>> +        items:
>> +          - enum:
>> +              - nxp,s32n79-rdb
>> +          - const: nxp,s32n79
>> +
> 
> can you put after S32G3 based Boards
> 
> Frank

Sounds good. Will update in V3.

Regards,
Ciprian

> 
>>         - description: Traverse LS1088A based Boards
>>           items:
>>             - enum:
>> --
>> 2.43.0
>>

Re: [PATCH v2 4/7] mmc: sdhci-esdhc-imx: add NXP S32N79 support

[Frank Li]

On Wed, Feb 25, 2026 at 02:38:55PM +0100, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add support for the uSDHC controller found in NXP S32N79 automotive SoCs.
>
> The controller is compatible with the existing sdhci-esdhc-imx driver.

"compatible" is not exactly,

Add support for the uSDHC controller found in NXP S32N79 automotive SoCs,
which reuse the existing sdhci-esdhc-imx driver with slice difference.

Compared with s32n79, needn't set ESDHC_FLAG_SKIP_CD_WAKE flags because
...

Frank
>
> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
> index a7a5df673b0f..28288fca87ff 100644
> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
> @@ -321,6 +321,14 @@ static struct esdhc_soc_data usdhc_s32g2_data = {
>  	.quirks = SDHCI_QUIRK_NO_LED,
>  };
>
> +static struct esdhc_soc_data usdhc_s32n79_data = {
> +	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> +			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
> +			| ESDHC_FLAG_SKIP_ERR004536,
> +	.quirks = SDHCI_QUIRK_NO_LED,
> +};
> +
>  static struct esdhc_soc_data usdhc_imx7ulp_data = {
>  	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
>  			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
> @@ -408,6 +416,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
>  	{ .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, },
>  	{ .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
>  	{ .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
> +	{ .compatible = "nxp,s32n79-usdhc", .data = &usdhc_s32n79_data, },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
> --
> 2.43.0
>

Re: [PATCH v2 4/7] mmc: sdhci-esdhc-imx: add NXP S32N79 support

[Ciprian Marian Costea]

On 2/25/2026 5:26 PM, Frank Li wrote:
> On Wed, Feb 25, 2026 at 02:38:55PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add support for the uSDHC controller found in NXP S32N79 automotive SoCs.
>>
>> The controller is compatible with the existing sdhci-esdhc-imx driver.
> 
> "compatible" is not exactly,
> 
> Add support for the uSDHC controller found in NXP S32N79 automotive SoCs,
> which reuse the existing sdhci-esdhc-imx driver with slice difference.
> 
> Compared with s32n79, needn't set ESDHC_FLAG_SKIP_CD_WAKE flags because
> ...
> 
> Frank

Makes sense. I will update the commit message accordingly in V3.

Regards,
Ciprian

>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   drivers/mmc/host/sdhci-esdhc-imx.c | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
>> index a7a5df673b0f..28288fca87ff 100644
>> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
>> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
>> @@ -321,6 +321,14 @@ static struct esdhc_soc_data usdhc_s32g2_data = {
>>   	.quirks = SDHCI_QUIRK_NO_LED,
>>   };
>>
>> +static struct esdhc_soc_data usdhc_s32n79_data = {
>> +	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
>> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
>> +			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
>> +			| ESDHC_FLAG_SKIP_ERR004536,
>> +	.quirks = SDHCI_QUIRK_NO_LED,
>> +};
>> +
>>   static struct esdhc_soc_data usdhc_imx7ulp_data = {
>>   	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
>>   			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
>> @@ -408,6 +416,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
>>   	{ .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, },
>>   	{ .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
>>   	{ .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
>> +	{ .compatible = "nxp,s32n79-usdhc", .data = &usdhc_s32n79_data, },
>>   	{ /* sentinel */ }
>>   };
>>   MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
>> --
>> 2.43.0
>>

Re: [PATCH v2 7/7] arm64: dts: freescale: Add minimal support for S32N79

[Frank Li]

On Wed, Feb 25, 2026 at 02:38:58PM +0100, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>
> Add device tree support for the NXP S32N79 automotive SoC and the S32N79
> Reference Design Board (RDB) [1].
>
> The S32N79 features eight Arm Cortex-A78AE cores organized in four
> dual-core clusters, with a three-level cache hierarchy (L1/L2 per core,
> L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3
> for IOMMU functionality.
>
> On S32N79 SoC, peripherals are organized into subsystems, such as:
> - CIS (Coherent Interconnect Subsystem).
> - COSS (Connectivity Subsystem)
> - FSS (Foundation Subsystem)
>
> This initial support includes basic peripherals:
> - GICv3, SMMUv3 from CIS Subsystem
> - PL011 UARTs and IRQ steering controller from COSS Subsystem
> - uSDHC from FSS Subsystem
>
> Clock and Pin multiplexing settings for the chip are managed over SCMI.
>
> [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N
>
> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Co-developed-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
> Co-developed-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile       |   1 +
>  arch/arm64/boot/dts/freescale/s32n79-rdb.dts |  70 ++++
>  arch/arm64/boot/dts/freescale/s32n79.dtsi    | 362 +++++++++++++++++++

chip dtsi need seperate patch.

>  3 files changed, 433 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 700bab4d3e60..e79807bf1820 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -501,4 +501,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb
>  dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
>  dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
>  dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
> +dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb
>  dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
> new file mode 100644
> index 000000000000..d13eb3a0666b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
> @@ -0,0 +1,70 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright 2026 NXP
> + *
> + * NXP S32N79 Reference Design Board (S32N79-RDB)
> + */
> +
> +/dts-v1/;
> +#include "s32n79.dtsi"
> +
> +/ {
> +	compatible = "nxp,s32n79-rdb", "nxp,s32n79";
> +	model = "NXP S32N79-RDB";
> +
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart5;
> +		serial2 = &uart6;
> +		serial3 = &uart7;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	reserved-memory {
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		scmi_shbuf: shm@93000000 {

use common node name memory@93000000

Frank
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x93000000 0x0 0x80>;
> +			no-map;
> +		};
> +	};
> +
> +	memory@80000000 {
> +		reg = <0x00 0x80000000 0x00 0x80000000>,
> +			<0x88 0x00000000 0x03 0x40000000>,
> +			<0xc0 0x00000000 0x03 0x40000000>;
> +		device_type = "memory";
> +	};
> +};
> +
> +&irqsteer_coss {
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&uart5 {
> +	status = "okay";
> +};
> +
> +&uart6 {
> +	status = "okay";
> +};
> +
> +&uart7 {
> +	status = "okay";
> +};
> +
> +&usdhc0 {
> +	disable-wp;
> +	no-sdio;
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
> new file mode 100644
> index 000000000000..94ab58783fdc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
> @@ -0,0 +1,362 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * NXP S32N79 SoC
> + *
> + * Copyright 2026 NXP
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cis-bus {
> +		compatible = "simple-bus";
> +		ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		gic: interrupt-controller@4f200000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x4f200000 0x10000>, /* GIC Dist */
> +			      <0x4f260000 0x100000>;
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			/* GICR (RD_base + SGI_base) */
> +			ranges;
> +
> +			its: msi-controller@4f240000 {
> +				compatible = "arm,gic-v3-its";
> +				reg = <0x4f240000 0x20000>;
> +				#msi-cells = <1>;
> +				msi-controller;
> +			};
> +		};
> +
> +		smmu: iommu@4fc00000 {
> +			compatible = "arm,smmu-v3";
> +			reg = <0x4fc00000 0x200000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> +			#iommu-cells = <1>;
> +			dma-coherent;
> +			status = "disabled";
> +		};
> +	};
> +
> +	coss-bus {
> +		compatible = "simple-bus";
> +		ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
> +			 <0x4e000000 0x0 0x4e000000 0x1000000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		uart0: serial@4a030000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x4a030000 0x1000>;
> +			interrupt-parent = <&irqsteer_coss>;
> +			interrupts = <264>;
> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@4a060000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x4a060000 0x1000>;
> +			interrupt-parent = <&irqsteer_coss>;
> +			interrupts = <269>;
> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart6: serial@4aa30000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x4aa30000 0x1000>;
> +			interrupt-parent = <&irqsteer_coss>;
> +			interrupts = <270>;
> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		uart7: serial@4aa40000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0x4aa40000 0x1000>;
> +			interrupt-parent = <&irqsteer_coss>;
> +			interrupts = <271>;
> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
> +			clock-names = "uartclk", "apb_pclk";
> +			status = "disabled";
> +		};
> +
> +		irqsteer_coss: interrupt-controller@4ed00000 {
> +			compatible = "nxp,s32n79-irqsteer";
> +			reg = <0x4ed00000 0x10000>;
> +			#interrupt-cells = <1>;
> +			interrupt-controller;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 0x9a>;
> +			clock-names = "ipg";
> +			fsl,channel = <0>;
> +			fsl,num-irqs = <512>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +
> +			cluster1 {
> +				core0 {
> +					cpu = <&cpu2>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +
> +			cluster2 {
> +				core0 {
> +					cpu = <&cpu4>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu5>;
> +				};
> +			};
> +
> +			cluster3 {
> +				core0 {
> +					cpu = <&cpu6>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu7>;
> +				};
> +			};
> +		};
> +
> +		l2_0: l2-cache0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +			cache-size = <524288>;
> +			cache-unified;
> +			next-level-cache = <&l3_0>;
> +		};
> +
> +		l2_1: l2-cache1 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +			cache-size = <524288>;
> +			cache-unified;
> +			next-level-cache = <&l3_1>;
> +		};
> +
> +		l2_2: l2-cache2 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +			cache-size = <524288>;
> +			cache-unified;
> +			next-level-cache = <&l3_2>;
> +		};
> +
> +		l2_3: l2-cache3 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +			cache-size = <524288>;
> +			cache-unified;
> +			next-level-cache = <&l3_3>;
> +		};
> +
> +		l3_0: l3-cache0 {
> +			compatible = "cache";
> +			cache-level = <3>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-size = <1048576>;
> +			cache-unified;
> +		};
> +
> +		l3_1: l3-cache1 {
> +			compatible = "cache";
> +			cache-level = <3>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-size = <1048576>;
> +			cache-unified;
> +		};
> +
> +		l3_2: l3-cache2 {
> +			compatible = "cache";
> +			cache-level = <3>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-size = <1048576>;
> +			cache-unified;
> +		};
> +
> +		l3_3: l3-cache3 {
> +			compatible = "cache";
> +			cache-level = <3>;
> +			cache-line-size = <64>;
> +			cache-sets = <1024>;
> +			cache-size = <1048576>;
> +			cache-unified;
> +		};
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x0>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_0>;
> +		};
> +
> +		cpu1: cpu@100 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x100>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_0>;
> +		};
> +
> +		cpu2: cpu@10000 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x10000>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_1>;
> +		};
> +
> +		cpu3: cpu@10100 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x10100>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_1>;
> +		};
> +
> +		cpu4: cpu@20000 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x20000>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_2>;
> +		};
> +
> +		cpu5: cpu@20100 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x20100>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_2>;
> +		};
> +
> +		cpu6: cpu@30000 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x30000>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_3>;
> +		};
> +
> +		cpu7: cpu@30100 {
> +			compatible = "arm,cortex-a78ae";
> +			reg = <0x30100>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			next-level-cache = <&l2_3>;
> +		};
> +	};
> +
> +	firmware {
> +		psci {
> +			compatible = "arm,psci-1.0";
> +			method = "smc";
> +		};
> +
> +		scmi: scmi {
> +			compatible = "arm,scmi-smc";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			shmem = <&scmi_shbuf>;
> +			arm,smc-id = <0xc20000fe>;
> +			status = "okay";
> +
> +			clks: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +	};
> +
> +	fss-bus {
> +		compatible = "simple-bus";
> +		ranges = <0x5b490000 0x0 0x5b490000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		usdhc0: mmc@5b490000 {
> +			compatible = "nxp,s32n79-usdhc";
> +			reg = <0x5b490000 0x1000>;
> +			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>;
> +			clock-names = "ipg", "ahb", "per";
> +			bus-width = <8>;
> +			status = "disabled";
> +		};
> +	};
> +
> +	pmu: pmu {
> +		compatible = "arm,armv8-pmuv3";
> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
> +	timer: timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +};
> --
> 2.43.0
>

Re: [PATCH v2 7/7] arm64: dts: freescale: Add minimal support for S32N79

[Ciprian Marian Costea]

On 2/25/2026 5:30 PM, Frank Li wrote:
> On Wed, Feb 25, 2026 at 02:38:58PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add device tree support for the NXP S32N79 automotive SoC and the S32N79
>> Reference Design Board (RDB) [1].
>>
>> The S32N79 features eight Arm Cortex-A78AE cores organized in four
>> dual-core clusters, with a three-level cache hierarchy (L1/L2 per core,
>> L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3
>> for IOMMU functionality.
>>
>> On S32N79 SoC, peripherals are organized into subsystems, such as:
>> - CIS (Coherent Interconnect Subsystem).
>> - COSS (Connectivity Subsystem)
>> - FSS (Foundation Subsystem)
>>
>> This initial support includes basic peripherals:
>> - GICv3, SMMUv3 from CIS Subsystem
>> - PL011 UARTs and IRQ steering controller from COSS Subsystem
>> - uSDHC from FSS Subsystem
>>
>> Clock and Pin multiplexing settings for the chip are managed over SCMI.
>>
>> [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N
>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Co-developed-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
>> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
>> Co-developed-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
>> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   arch/arm64/boot/dts/freescale/Makefile       |   1 +
>>   arch/arm64/boot/dts/freescale/s32n79-rdb.dts |  70 ++++
>>   arch/arm64/boot/dts/freescale/s32n79.dtsi    | 362 +++++++++++++++++++
> 
> chip dtsi need seperate patch.

I will make a separate patch for the '.dtsi' file in V3.

> 
>>   3 files changed, 433 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>>   create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
>> index 700bab4d3e60..e79807bf1820 100644
>> --- a/arch/arm64/boot/dts/freescale/Makefile
>> +++ b/arch/arm64/boot/dts/freescale/Makefile
>> @@ -501,4 +501,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
>> +dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
>> diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>> new file mode 100644
>> index 000000000000..d13eb3a0666b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>> @@ -0,0 +1,70 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright 2026 NXP
>> + *
>> + * NXP S32N79 Reference Design Board (S32N79-RDB)
>> + */
>> +
>> +/dts-v1/;
>> +#include "s32n79.dtsi"
>> +
>> +/ {
>> +	compatible = "nxp,s32n79-rdb", "nxp,s32n79";
>> +	model = "NXP S32N79-RDB";
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +		serial1 = &uart5;
>> +		serial2 = &uart6;
>> +		serial3 = &uart7;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	reserved-memory {
>> +		ranges;
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +
>> +		scmi_shbuf: shm@93000000 {
> 
> use common node name memory@93000000
> 
> Frank

Ok. I will update accordingly in V3.

Regards,
Ciprian

>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0x0 0x93000000 0x0 0x80>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	memory@80000000 {
>> +		reg = <0x00 0x80000000 0x00 0x80000000>,
>> +			<0x88 0x00000000 0x03 0x40000000>,
>> +			<0xc0 0x00000000 0x03 0x40000000>;
>> +		device_type = "memory";
>> +	};
>> +};
>> +
>> +&irqsteer_coss {
>> +	status = "okay";
>> +};
>> +
>> +&uart0 {
>> +	status = "okay";
>> +};
>> +
>> +&uart5 {
>> +	status = "okay";
>> +};
>> +
>> +&uart6 {
>> +	status = "okay";
>> +};
>> +
>> +&uart7 {
>> +	status = "okay";
>> +};
>> +
>> +&usdhc0 {
>> +	disable-wp;
>> +	no-sdio;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
>> new file mode 100644
>> index 000000000000..94ab58783fdc
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
>> @@ -0,0 +1,362 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * NXP S32N79 SoC
>> + *
>> + * Copyright 2026 NXP
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	cis-bus {
>> +		compatible = "simple-bus";
>> +		ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		gic: interrupt-controller@4f200000 {
>> +			compatible = "arm,gic-v3";
>> +			reg = <0x4f200000 0x10000>, /* GIC Dist */
>> +			      <0x4f260000 0x100000>;
>> +			#interrupt-cells = <3>;
>> +			interrupt-controller;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			/* GICR (RD_base + SGI_base) */
>> +			ranges;
>> +
>> +			its: msi-controller@4f240000 {
>> +				compatible = "arm,gic-v3-its";
>> +				reg = <0x4f240000 0x20000>;
>> +				#msi-cells = <1>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		smmu: iommu@4fc00000 {
>> +			compatible = "arm,smmu-v3";
>> +			reg = <0x4fc00000 0x200000>;
>> +			interrupt-parent = <&gic>;
>> +			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
>> +			interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
>> +			#iommu-cells = <1>;
>> +			dma-coherent;
>> +			status = "disabled";
>> +		};
>> +	};
>> +
>> +	coss-bus {
>> +		compatible = "simple-bus";
>> +		ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
>> +			 <0x4e000000 0x0 0x4e000000 0x1000000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		uart0: serial@4a030000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4a030000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <264>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart5: serial@4a060000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4a060000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <269>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart6: serial@4aa30000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4aa30000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <270>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart7: serial@4aa40000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4aa40000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <271>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		irqsteer_coss: interrupt-controller@4ed00000 {
>> +			compatible = "nxp,s32n79-irqsteer";
>> +			reg = <0x4ed00000 0x10000>;
>> +			#interrupt-cells = <1>;
>> +			interrupt-controller;
>> +			interrupt-parent = <&gic>;
>> +			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clks 0x9a>;
>> +			clock-names = "ipg";
>> +			fsl,channel = <0>;
>> +			fsl,num-irqs = <512>;
>> +			status = "disabled";
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu-map {
>> +			cluster0 {
>> +				core0 {
>> +					cpu = <&cpu0>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu1>;
>> +				};
>> +			};
>> +
>> +			cluster1 {
>> +				core0 {
>> +					cpu = <&cpu2>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu3>;
>> +				};
>> +			};
>> +
>> +			cluster2 {
>> +				core0 {
>> +					cpu = <&cpu4>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu5>;
>> +				};
>> +			};
>> +
>> +			cluster3 {
>> +				core0 {
>> +					cpu = <&cpu6>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu7>;
>> +				};
>> +			};
>> +		};
>> +
>> +		l2_0: l2-cache0 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_0>;
>> +		};
>> +
>> +		l2_1: l2-cache1 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_1>;
>> +		};
>> +
>> +		l2_2: l2-cache2 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_2>;
>> +		};
>> +
>> +		l2_3: l2-cache3 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_3>;
>> +		};
>> +
>> +		l3_0: l3-cache0 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		l3_1: l3-cache1 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		l3_2: l3-cache2 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		l3_3: l3-cache3 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		cpu0: cpu@0 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x0>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_0>;
>> +		};
>> +
>> +		cpu1: cpu@100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_0>;
>> +		};
>> +
>> +		cpu2: cpu@10000 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x10000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_1>;
>> +		};
>> +
>> +		cpu3: cpu@10100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x10100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_1>;
>> +		};
>> +
>> +		cpu4: cpu@20000 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x20000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_2>;
>> +		};
>> +
>> +		cpu5: cpu@20100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x20100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_2>;
>> +		};
>> +
>> +		cpu6: cpu@30000 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x30000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_3>;
>> +		};
>> +
>> +		cpu7: cpu@30100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x30100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_3>;
>> +		};
>> +	};
>> +
>> +	firmware {
>> +		psci {
>> +			compatible = "arm,psci-1.0";
>> +			method = "smc";
>> +		};
>> +
>> +		scmi: scmi {
>> +			compatible = "arm,scmi-smc";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			shmem = <&scmi_shbuf>;
>> +			arm,smc-id = <0xc20000fe>;
>> +			status = "okay";
>> +
>> +			clks: protocol@14 {
>> +				reg = <0x14>;
>> +				#clock-cells = <1>;
>> +			};
>> +		};
>> +	};
>> +
>> +	fss-bus {
>> +		compatible = "simple-bus";
>> +		ranges = <0x5b490000 0x0 0x5b490000 0x1000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		usdhc0: mmc@5b490000 {
>> +			compatible = "nxp,s32n79-usdhc";
>> +			reg = <0x5b490000 0x1000>;
>> +			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>;
>> +			clock-names = "ipg", "ahb", "per";
>> +			bus-width = <8>;
>> +			status = "disabled";
>> +		};
>> +	};
>> +
>> +	pmu: pmu {
>> +		compatible = "arm,armv8-pmuv3";
>> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +	};
>> +
>> +	timer: timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>> +	};
>> +};
>> --
>> 2.43.0
>>

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Krzysztof Kozlowski]

On Wed, Feb 25, 2026 at 02:38:52PM +0100, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> Add compatible string for the interrupt steering controller used in NXP
> S32N79 SoC.
> 
> The S32N79 SoC differs from the i.MX version by not implementing the
> CHANCTRL register, but otherwise maintains the same programming model and
> register layout.
> 
> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
>  .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
> index 5c768c1e159c..caf3e4a1f26f 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
> @@ -22,6 +22,7 @@ properties:
>                - fsl,imx94-irqsteer
>                - fsl,imx95-irqsteer
>            - const: fsl,imx-irqsteer
> +      - const: nxp,s32n79-irqsteer

So that should be part of enum with the first entry.

Best regards,
Krzysztof

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Krzysztof Kozlowski]

On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> 
> Add device tree binding documentation for the NXP S32N79 automotive SoC
> and the S32N79 Reference Design Board (S32N79-RDB).
> 
> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
> cores organized for high-performance networking and gateway applications
> in vehicles.
> 
> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> ---
>  Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 5716d701292c..415081423a30 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1827,6 +1827,12 @@ properties:
>                - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>            - const: fsl,s32v234
>  
> +      - description: S32N79 based Boards
> +        items:
> +          - enum:
> +              - nxp,s32n79-rdb
> +          - const: nxp,s32n79

I believe these are ordered by fallback, so s32v > s32n.

> +
>        - description: Traverse LS1088A based Boards
>          items:
>            - enum:
> -- 
> 2.43.0
> 

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Frank Li]

On Thu, Feb 26, 2026 at 08:32:16AM +0100, Krzysztof Kozlowski wrote:
> On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
> > From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> >
> > Add device tree binding documentation for the NXP S32N79 automotive SoC
> > and the S32N79 Reference Design Board (S32N79-RDB).
> >
> > The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
> > cores organized for high-performance networking and gateway applications
> > in vehicles.
> >
> > Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
> > Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
> > Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
> > ---
> >  Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index 5716d701292c..415081423a30 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -1827,6 +1827,12 @@ properties:
> >                - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
> >            - const: fsl,s32v234
> >
> > +      - description: S32N79 based Boards
> > +        items:
> > +          - enum:
> > +              - nxp,s32n79-rdb
> > +          - const: nxp,s32n79
>
> I believe these are ordered by fallback, so s32v > s32n.

Previous use fsl,s32v234, now use nxp,s32n79, I suggest keep consistent
with existing one, use fsl,s32n79

Frank

>
> > +
> >        - description: Traverse LS1088A based Boards
> >          items:
> >            - enum:
> > --
> > 2.43.0
> >

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Krzysztof Kozlowski]

On 26/02/2026 16:17, Frank Li wrote:
> On Thu, Feb 26, 2026 at 08:32:16AM +0100, Krzysztof Kozlowski wrote:
>> On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>
>>> Add device tree binding documentation for the NXP S32N79 automotive SoC
>>> and the S32N79 Reference Design Board (S32N79-RDB).
>>>
>>> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
>>> cores organized for high-performance networking and gateway applications
>>> in vehicles.
>>>
>>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>>>  1 file changed, 6 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>>> index 5716d701292c..415081423a30 100644
>>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>>> @@ -1827,6 +1827,12 @@ properties:
>>>                - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>>>            - const: fsl,s32v234
>>>
>>> +      - description: S32N79 based Boards
>>> +        items:
>>> +          - enum:
>>> +              - nxp,s32n79-rdb
>>> +          - const: nxp,s32n79
>>
>> I believe these are ordered by fallback, so s32v > s32n.
> 
> Previous use fsl,s32v234, now use nxp,s32n79, I suggest keep consistent
> with existing one, use fsl,s32n79
> 

Ah, I missed that prefix is different! Well, that I don't mind, it's
your call which prefix you want.

Best regards,
Krzysztof

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Ciprian Marian Costea]

On 2/26/2026 9:31 AM, Krzysztof Kozlowski wrote:
> On Wed, Feb 25, 2026 at 02:38:52PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add compatible string for the interrupt steering controller used in NXP
>> S32N79 SoC.
>>
>> The S32N79 SoC differs from the i.MX version by not implementing the
>> CHANCTRL register, but otherwise maintains the same programming model and
>> register layout.
>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>> index 5c768c1e159c..caf3e4a1f26f 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>> @@ -22,6 +22,7 @@ properties:
>>                 - fsl,imx94-irqsteer
>>                 - fsl,imx95-irqsteer
>>             - const: fsl,imx-irqsteer
>> +      - const: nxp,s32n79-irqsteer
> 
> So that should be part of enum with the first entry.
> 
> Best regards,
> Krzysztof
> 

Hello Krzysztof,

Thanks for your review. Regarding this change, I was thinking since 
S32N79 irqsteer does not implement the 'CHANCTRL' register, it should 
not fallback to 'fsl,imx-irqsteer'. If the driver were to match on the 
fallback compatible, it would attempt to write to the non-existent 
CHANCTRL register.

Am I wrong?

Best regards,
Ciprian

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Ciprian Marian Costea]

On 2/26/2026 9:32 AM, Krzysztof Kozlowski wrote:
> On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add device tree binding documentation for the NXP S32N79 automotive SoC
>> and the S32N79 Reference Design Board (S32N79-RDB).
>>
>> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
>> cores organized for high-performance networking and gateway applications
>> in vehicles.
>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>> index 5716d701292c..415081423a30 100644
>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>> @@ -1827,6 +1827,12 @@ properties:
>>                 - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>>             - const: fsl,s32v234
>>   
>> +      - description: S32N79 based Boards
>> +        items:
>> +          - enum:
>> +              - nxp,s32n79-rdb
>> +          - const: nxp,s32n79
> 
> I believe these are ordered by fallback, so s32v > s32n.

Makes sense. I will move S32N79 entry before S32V234 in V3 patchset.

Best regards,
Ciprian

> 
>> +
>>         - description: Traverse LS1088A based Boards
>>           items:
>>             - enum:
>> -- 
>> 2.43.0
>>

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Ciprian Marian Costea]

On 2/25/2026 5:21 PM, Frank Li wrote:
> On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add device tree binding documentation for the NXP S32N79 automotive SoC
>> and the S32N79 Reference Design Board (S32N79-RDB).
>>
>> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
>> cores organized for high-performance networking and gateway applications
>> in vehicles.
>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>> index 5716d701292c..415081423a30 100644
>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>> @@ -1827,6 +1827,12 @@ properties:
>>                 - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>>             - const: fsl,s32v234
>>
>> +      - description: S32N79 based Boards
>> +        items:
>> +          - enum:
>> +              - nxp,s32n79-rdb
>> +          - const: nxp,s32n79
>> +
> 
> can you put after S32G3 based Boards
> 
> Frank

Makes sense. I will move S32N79 entry before S32V234 in V3 patchset.

Best regards,
Ciprian

> 
>>         - description: Traverse LS1088A based Boards
>>           items:
>>             - enum:
>> --
>> 2.43.0
>>

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Krzysztof Kozlowski]

On 05/03/2026 13:02, Ciprian Marian Costea wrote:
> On 2/26/2026 9:31 AM, Krzysztof Kozlowski wrote:
>> On Wed, Feb 25, 2026 at 02:38:52PM +0100, Ciprian Costea wrote:
>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>
>>> Add compatible string for the interrupt steering controller used in NXP
>>> S32N79 SoC.
>>>
>>> The S32N79 SoC differs from the i.MX version by not implementing the
>>> CHANCTRL register, but otherwise maintains the same programming model and
>>> register layout.
>>>
>>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>> ---
>>>   .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>> index 5c768c1e159c..caf3e4a1f26f 100644
>>> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>> @@ -22,6 +22,7 @@ properties:
>>>                 - fsl,imx94-irqsteer
>>>                 - fsl,imx95-irqsteer
>>>             - const: fsl,imx-irqsteer
>>> +      - const: nxp,s32n79-irqsteer
>>
>> So that should be part of enum with the first entry.
>>
>> Best regards,
>> Krzysztof
>>
> 
> Hello Krzysztof,
> 
> Thanks for your review. Regarding this change, I was thinking since 
> S32N79 irqsteer does not implement the 'CHANCTRL' register, it should 
> not fallback to 'fsl,imx-irqsteer'. If the driver were to match on the 
> fallback compatible, it would attempt to write to the non-existent 
> CHANCTRL register.
> 
> Am I wrong?

No clue, I did not say anything about fallbacks.

Best regards,
Krzysztof

Re: [PATCH v2 3/7] dt-bindings: arm: fsl: Add NXP S32N79 SoC and RDB board

[Ciprian Marian Costea]

On 2/26/2026 7:00 PM, Krzysztof Kozlowski wrote:
> On 26/02/2026 16:17, Frank Li wrote:
>> On Thu, Feb 26, 2026 at 08:32:16AM +0100, Krzysztof Kozlowski wrote:
>>> On Wed, Feb 25, 2026 at 02:38:54PM +0100, Ciprian Costea wrote:
>>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>
>>>> Add device tree binding documentation for the NXP S32N79 automotive SoC
>>>> and the S32N79 Reference Design Board (S32N79-RDB).
>>>>
>>>> The S32N79 is an automotive-grade SoC featuring eight ARM Cortex-A78AE
>>>> cores organized for high-performance networking and gateway applications
>>>> in vehicles.
>>>>
>>>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>> ---
>>>>   Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
>>>>   1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>>>> index 5716d701292c..415081423a30 100644
>>>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>>>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>>>> @@ -1827,6 +1827,12 @@ properties:
>>>>                 - fsl,s32v234-evb           # S32V234-EVB2 Customer Evaluation Board
>>>>             - const: fsl,s32v234
>>>>
>>>> +      - description: S32N79 based Boards
>>>> +        items:
>>>> +          - enum:
>>>> +              - nxp,s32n79-rdb
>>>> +          - const: nxp,s32n79
>>>
>>> I believe these are ordered by fallback, so s32v > s32n.
>>
>> Previous use fsl,s32v234, now use nxp,s32n79, I suggest keep consistent
>> with existing one, use fsl,s32n79
>>
> 
> Ah, I missed that prefix is different! Well, that I don't mind, it's
> your call which prefix you want.
> 
> Best regards,
> Krzysztof

Ah, since they are ordered by fallback, I will keep 'nxp,s32n79*'.
Therefore, I will leave the order as is. S32N79 after S32V234.

Thanks,
Ciprian C

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Ciprian Marian Costea]

On 3/5/2026 2:12 PM, Krzysztof Kozlowski wrote:
> On 05/03/2026 13:02, Ciprian Marian Costea wrote:
>> On 2/26/2026 9:31 AM, Krzysztof Kozlowski wrote:
>>> On Wed, Feb 25, 2026 at 02:38:52PM +0100, Ciprian Costea wrote:
>>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>
>>>> Add compatible string for the interrupt steering controller used in NXP
>>>> S32N79 SoC.
>>>>
>>>> The S32N79 SoC differs from the i.MX version by not implementing the
>>>> CHANCTRL register, but otherwise maintains the same programming model and
>>>> register layout.
>>>>
>>>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>> ---
>>>>    .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
>>>>    1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>> index 5c768c1e159c..caf3e4a1f26f 100644
>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>> @@ -22,6 +22,7 @@ properties:
>>>>                  - fsl,imx94-irqsteer
>>>>                  - fsl,imx95-irqsteer
>>>>              - const: fsl,imx-irqsteer
>>>> +      - const: nxp,s32n79-irqsteer
>>>
>>> So that should be part of enum with the first entry.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Hello Krzysztof,
>>
>> Thanks for your review. Regarding this change, I was thinking since
>> S32N79 irqsteer does not implement the 'CHANCTRL' register, it should
>> not fallback to 'fsl,imx-irqsteer'. If the driver were to match on the
>> fallback compatible, it would attempt to write to the non-existent
>> CHANCTRL register.
>>
>> Am I wrong?
> 
> No clue, I did not say anything about fallbacks.
> 
> Best regards,
> Krzysztof

Indeed, but your suggestion of moving 'nxp,s32n79-irqsteer' under the
enum would fallback on 'fsl,imx-irqsteer'.

Am I misunderstanding your suggestion ?

Best regards,
Ciprian

Re: [PATCH v2 4/7] mmc: sdhci-esdhc-imx: add NXP S32N79 support

[Ciprian Marian Costea]

On 2/25/2026 5:26 PM, Frank Li wrote:
> On Wed, Feb 25, 2026 at 02:38:55PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add support for the uSDHC controller found in NXP S32N79 automotive SoCs.
>>
>> The controller is compatible with the existing sdhci-esdhc-imx driver.
> 
> "compatible" is not exactly,
> 
> Add support for the uSDHC controller found in NXP S32N79 automotive SoCs,
> which reuse the existing sdhci-esdhc-imx driver with slice difference.
> 
> Compared with s32n79, needn't set ESDHC_FLAG_SKIP_CD_WAKE flags because
> ...
> 
> Frank

Thanks for your suggestion. I will add to the description in V3.

Best regards,
Ciprian

>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   drivers/mmc/host/sdhci-esdhc-imx.c | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
>> index a7a5df673b0f..28288fca87ff 100644
>> --- a/drivers/mmc/host/sdhci-esdhc-imx.c
>> +++ b/drivers/mmc/host/sdhci-esdhc-imx.c
>> @@ -321,6 +321,14 @@ static struct esdhc_soc_data usdhc_s32g2_data = {
>>   	.quirks = SDHCI_QUIRK_NO_LED,
>>   };
>>
>> +static struct esdhc_soc_data usdhc_s32n79_data = {
>> +	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
>> +			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
>> +			| ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
>> +			| ESDHC_FLAG_SKIP_ERR004536,
>> +	.quirks = SDHCI_QUIRK_NO_LED,
>> +};
>> +
>>   static struct esdhc_soc_data usdhc_imx7ulp_data = {
>>   	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
>>   			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
>> @@ -408,6 +416,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
>>   	{ .compatible = "fsl,imx95-usdhc", .data = &usdhc_imx95_data, },
>>   	{ .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, },
>>   	{ .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, },
>> +	{ .compatible = "nxp,s32n79-usdhc", .data = &usdhc_s32n79_data, },
>>   	{ /* sentinel */ }
>>   };
>>   MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
>> --
>> 2.43.0
>>

Re: [PATCH v2 7/7] arm64: dts: freescale: Add minimal support for S32N79

[Ciprian Marian Costea]

On 2/25/2026 5:30 PM, Frank Li wrote:
> On Wed, Feb 25, 2026 at 02:38:58PM +0100, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> Add device tree support for the NXP S32N79 automotive SoC and the S32N79
>> Reference Design Board (RDB) [1].
>>
>> The S32N79 features eight Arm Cortex-A78AE cores organized in four
>> dual-core clusters, with a three-level cache hierarchy (L1/L2 per core,
>> L3 per dual-core cluster) and 32GB of DRAM memory. It includes an SMMUv3
>> for IOMMU functionality.
>>
>> On S32N79 SoC, peripherals are organized into subsystems, such as:
>> - CIS (Coherent Interconnect Subsystem).
>> - COSS (Connectivity Subsystem)
>> - FSS (Foundation Subsystem)
>>
>> This initial support includes basic peripherals:
>> - GICv3, SMMUv3 from CIS Subsystem
>> - PL011 UARTs and IRQ steering controller from COSS Subsystem
>> - uSDHC from FSS Subsystem
>>
>> Clock and Pin multiplexing settings for the chip are managed over SCMI.
>>
>> [1] https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32n-vehicle-super-integration-processors:S32N
>>
>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>> Co-developed-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
>> Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
>> Co-developed-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
>> Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>> ---
>>   arch/arm64/boot/dts/freescale/Makefile       |   1 +
>>   arch/arm64/boot/dts/freescale/s32n79-rdb.dts |  70 ++++
>>   arch/arm64/boot/dts/freescale/s32n79.dtsi    | 362 +++++++++++++++++++
> 
> chip dtsi need seperate patch.
> 

Hello Frank,

Thanks for your review.
I will add s32n79 dtsi in a separate commit in V3.

>>   3 files changed, 433 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>>   create mode 100644 arch/arm64/boot/dts/freescale/s32n79.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
>> index 700bab4d3e60..e79807bf1820 100644
>> --- a/arch/arm64/boot/dts/freescale/Makefile
>> +++ b/arch/arm64/boot/dts/freescale/Makefile
>> @@ -501,4 +501,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
>> +dtb-$(CONFIG_ARCH_S32) += s32n79-rdb.dtb
>>   dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
>> diff --git a/arch/arm64/boot/dts/freescale/s32n79-rdb.dts b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>> new file mode 100644
>> index 000000000000..d13eb3a0666b
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/s32n79-rdb.dts
>> @@ -0,0 +1,70 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * Copyright 2026 NXP
>> + *
>> + * NXP S32N79 Reference Design Board (S32N79-RDB)
>> + */
>> +
>> +/dts-v1/;
>> +#include "s32n79.dtsi"
>> +
>> +/ {
>> +	compatible = "nxp,s32n79-rdb", "nxp,s32n79";
>> +	model = "NXP S32N79-RDB";
>> +
>> +	aliases {
>> +		serial0 = &uart0;
>> +		serial1 = &uart5;
>> +		serial2 = &uart6;
>> +		serial3 = &uart7;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	reserved-memory {
>> +		ranges;
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +
>> +		scmi_shbuf: shm@93000000 {
> 
> use common node name memory@93000000
> 
> Frank

Will update accordingly in V3.

Best regards,
Ciprian

>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0x0 0x93000000 0x0 0x80>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	memory@80000000 {
>> +		reg = <0x00 0x80000000 0x00 0x80000000>,
>> +			<0x88 0x00000000 0x03 0x40000000>,
>> +			<0xc0 0x00000000 0x03 0x40000000>;
>> +		device_type = "memory";
>> +	};
>> +};
>> +
>> +&irqsteer_coss {
>> +	status = "okay";
>> +};
>> +
>> +&uart0 {
>> +	status = "okay";
>> +};
>> +
>> +&uart5 {
>> +	status = "okay";
>> +};
>> +
>> +&uart6 {
>> +	status = "okay";
>> +};
>> +
>> +&uart7 {
>> +	status = "okay";
>> +};
>> +
>> +&usdhc0 {
>> +	disable-wp;
>> +	no-sdio;
>> +	status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi
>> new file mode 100644
>> index 000000000000..94ab58783fdc
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi
>> @@ -0,0 +1,362 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>> +/*
>> + * NXP S32N79 SoC
>> + *
>> + * Copyright 2026 NXP
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	cis-bus {
>> +		compatible = "simple-bus";
>> +		ranges = <0x4f200000 0x0 0x4f200000 0xc00000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		gic: interrupt-controller@4f200000 {
>> +			compatible = "arm,gic-v3";
>> +			reg = <0x4f200000 0x10000>, /* GIC Dist */
>> +			      <0x4f260000 0x100000>;
>> +			#interrupt-cells = <3>;
>> +			interrupt-controller;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			/* GICR (RD_base + SGI_base) */
>> +			ranges;
>> +
>> +			its: msi-controller@4f240000 {
>> +				compatible = "arm,gic-v3-its";
>> +				reg = <0x4f240000 0x20000>;
>> +				#msi-cells = <1>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		smmu: iommu@4fc00000 {
>> +			compatible = "arm,smmu-v3";
>> +			reg = <0x4fc00000 0x200000>;
>> +			interrupt-parent = <&gic>;
>> +			interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>,
>> +				     <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
>> +			interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
>> +			#iommu-cells = <1>;
>> +			dma-coherent;
>> +			status = "disabled";
>> +		};
>> +	};
>> +
>> +	coss-bus {
>> +		compatible = "simple-bus";
>> +		ranges = <0x4a000000 0x0 0x4a000000 0xff0000>,
>> +			 <0x4e000000 0x0 0x4e000000 0x1000000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		uart0: serial@4a030000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4a030000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <264>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart5: serial@4a060000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4a060000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <269>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart6: serial@4aa30000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4aa30000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <270>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		uart7: serial@4aa40000 {
>> +			compatible = "arm,pl011", "arm,primecell";
>> +			reg = <0x4aa40000 0x1000>;
>> +			interrupt-parent = <&irqsteer_coss>;
>> +			interrupts = <271>;
>> +			clocks = <&clks 0x9a>, <&clks 0x9a>;
>> +			clock-names = "uartclk", "apb_pclk";
>> +			status = "disabled";
>> +		};
>> +
>> +		irqsteer_coss: interrupt-controller@4ed00000 {
>> +			compatible = "nxp,s32n79-irqsteer";
>> +			reg = <0x4ed00000 0x10000>;
>> +			#interrupt-cells = <1>;
>> +			interrupt-controller;
>> +			interrupt-parent = <&gic>;
>> +			interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clks 0x9a>;
>> +			clock-names = "ipg";
>> +			fsl,channel = <0>;
>> +			fsl,num-irqs = <512>;
>> +			status = "disabled";
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu-map {
>> +			cluster0 {
>> +				core0 {
>> +					cpu = <&cpu0>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu1>;
>> +				};
>> +			};
>> +
>> +			cluster1 {
>> +				core0 {
>> +					cpu = <&cpu2>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu3>;
>> +				};
>> +			};
>> +
>> +			cluster2 {
>> +				core0 {
>> +					cpu = <&cpu4>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu5>;
>> +				};
>> +			};
>> +
>> +			cluster3 {
>> +				core0 {
>> +					cpu = <&cpu6>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu7>;
>> +				};
>> +			};
>> +		};
>> +
>> +		l2_0: l2-cache0 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_0>;
>> +		};
>> +
>> +		l2_1: l2-cache1 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_1>;
>> +		};
>> +
>> +		l2_2: l2-cache2 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_2>;
>> +		};
>> +
>> +		l2_3: l2-cache3 {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <512>;
>> +			cache-size = <524288>;
>> +			cache-unified;
>> +			next-level-cache = <&l3_3>;
>> +		};
>> +
>> +		l3_0: l3-cache0 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		l3_1: l3-cache1 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		l3_2: l3-cache2 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		l3_3: l3-cache3 {
>> +			compatible = "cache";
>> +			cache-level = <3>;
>> +			cache-line-size = <64>;
>> +			cache-sets = <1024>;
>> +			cache-size = <1048576>;
>> +			cache-unified;
>> +		};
>> +
>> +		cpu0: cpu@0 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x0>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_0>;
>> +		};
>> +
>> +		cpu1: cpu@100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_0>;
>> +		};
>> +
>> +		cpu2: cpu@10000 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x10000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_1>;
>> +		};
>> +
>> +		cpu3: cpu@10100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x10100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_1>;
>> +		};
>> +
>> +		cpu4: cpu@20000 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x20000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_2>;
>> +		};
>> +
>> +		cpu5: cpu@20100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x20100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_2>;
>> +		};
>> +
>> +		cpu6: cpu@30000 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x30000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_3>;
>> +		};
>> +
>> +		cpu7: cpu@30100 {
>> +			compatible = "arm,cortex-a78ae";
>> +			reg = <0x30100>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			next-level-cache = <&l2_3>;
>> +		};
>> +	};
>> +
>> +	firmware {
>> +		psci {
>> +			compatible = "arm,psci-1.0";
>> +			method = "smc";
>> +		};
>> +
>> +		scmi: scmi {
>> +			compatible = "arm,scmi-smc";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			shmem = <&scmi_shbuf>;
>> +			arm,smc-id = <0xc20000fe>;
>> +			status = "okay";
>> +
>> +			clks: protocol@14 {
>> +				reg = <0x14>;
>> +				#clock-cells = <1>;
>> +			};
>> +		};
>> +	};
>> +
>> +	fss-bus {
>> +		compatible = "simple-bus";
>> +		ranges = <0x5b490000 0x0 0x5b490000 0x1000>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +
>> +		usdhc0: mmc@5b490000 {
>> +			compatible = "nxp,s32n79-usdhc";
>> +			reg = <0x5b490000 0x1000>;
>> +			interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clks 0x58>, <&clks 0x50>, <&clks 0x5f>;
>> +			clock-names = "ipg", "ahb", "per";
>> +			bus-width = <8>;
>> +			status = "disabled";
>> +		};
>> +	};
>> +
>> +	pmu: pmu {
>> +		compatible = "arm,armv8-pmuv3";
>> +		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +	};
>> +
>> +	timer: timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>> +	};
>> +};
>> --
>> 2.43.0
>>

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Krzysztof Kozlowski]

On 05/03/2026 13:25, Ciprian Marian Costea wrote:
> On 3/5/2026 2:12 PM, Krzysztof Kozlowski wrote:
>> On 05/03/2026 13:02, Ciprian Marian Costea wrote:
>>> On 2/26/2026 9:31 AM, Krzysztof Kozlowski wrote:
>>>> On Wed, Feb 25, 2026 at 02:38:52PM +0100, Ciprian Costea wrote:
>>>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>>
>>>>> Add compatible string for the interrupt steering controller used in NXP
>>>>> S32N79 SoC.
>>>>>
>>>>> The S32N79 SoC differs from the i.MX version by not implementing the
>>>>> CHANCTRL register, but otherwise maintains the same programming model and
>>>>> register layout.
>>>>>
>>>>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>> ---
>>>>>    .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
>>>>>    1 file changed, 1 insertion(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>>> index 5c768c1e159c..caf3e4a1f26f 100644
>>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>>> @@ -22,6 +22,7 @@ properties:
>>>>>                  - fsl,imx94-irqsteer
>>>>>                  - fsl,imx95-irqsteer
>>>>>              - const: fsl,imx-irqsteer
>>>>> +      - const: nxp,s32n79-irqsteer
>>>>
>>>> So that should be part of enum with the first entry.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> Hello Krzysztof,
>>>
>>> Thanks for your review. Regarding this change, I was thinking since
>>> S32N79 irqsteer does not implement the 'CHANCTRL' register, it should
>>> not fallback to 'fsl,imx-irqsteer'. If the driver were to match on the
>>> fallback compatible, it would attempt to write to the non-existent
>>> CHANCTRL register.
>>>
>>> Am I wrong?
>>
>> No clue, I did not say anything about fallbacks.
>>
>> Best regards,
>> Krzysztof
> 
> Indeed, but your suggestion of moving 'nxp,s32n79-irqsteer' under the
> enum would fallback on 'fsl,imx-irqsteer'.
> 
> Am I misunderstanding your suggestion ?

Open the code. What is the first entry?

Best regards,
Krzysztof

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Ciprian Marian Costea]

On 3/5/2026 2:39 PM, Krzysztof Kozlowski wrote:
> On 05/03/2026 13:25, Ciprian Marian Costea wrote:
>> On 3/5/2026 2:12 PM, Krzysztof Kozlowski wrote:
>>> On 05/03/2026 13:02, Ciprian Marian Costea wrote:
>>>> On 2/26/2026 9:31 AM, Krzysztof Kozlowski wrote:
>>>>> On Wed, Feb 25, 2026 at 02:38:52PM +0100, Ciprian Costea wrote:
>>>>>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>>>
>>>>>> Add compatible string for the interrupt steering controller used in NXP
>>>>>> S32N79 SoC.
>>>>>>
>>>>>> The S32N79 SoC differs from the i.MX version by not implementing the
>>>>>> CHANCTRL register, but otherwise maintains the same programming model and
>>>>>> register layout.
>>>>>>
>>>>>> Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>>>> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
>>>>>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>>>>> ---
>>>>>>     .../devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml   | 1 +
>>>>>>     1 file changed, 1 insertion(+)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>>>> index 5c768c1e159c..caf3e4a1f26f 100644
>>>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
>>>>>> @@ -22,6 +22,7 @@ properties:
>>>>>>                   - fsl,imx94-irqsteer
>>>>>>                   - fsl,imx95-irqsteer
>>>>>>               - const: fsl,imx-irqsteer
>>>>>> +      - const: nxp,s32n79-irqsteer
>>>>>
>>>>> So that should be part of enum with the first entry.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Hello Krzysztof,
>>>>
>>>> Thanks for your review. Regarding this change, I was thinking since
>>>> S32N79 irqsteer does not implement the 'CHANCTRL' register, it should
>>>> not fallback to 'fsl,imx-irqsteer'. If the driver were to match on the
>>>> fallback compatible, it would attempt to write to the non-existent
>>>> CHANCTRL register.
>>>>
>>>> Am I wrong?
>>>
>>> No clue, I did not say anything about fallbacks.
>>>
>>> Best regards,
>>> Krzysztof
>>
>> Indeed, but your suggestion of moving 'nxp,s32n79-irqsteer' under the
>> enum would fallback on 'fsl,imx-irqsteer'.
>>
>> Am I misunderstanding your suggestion ?
> 
> Open the code. What is the first entry?
> 
> Best regards,
> Krzysztof

Sorry, the enum reference confused me.

Is the following in accordance with your suggestion?

oneOf:
   - enum:
       - fsl,imx-irqsteer
       - nxp,s32n79-irqsteer
   - items:
       - enum:
           ...
       - const: fsl,imx-irqsteer

Best regards,
Ciprian

Re: [PATCH v2 1/7] dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support

[Krzysztof Kozlowski]

On 05/03/2026 14:32, Ciprian Marian Costea wrote:
> Sorry, the enum reference confused me.
> 
> Is the following in accordance with your suggestion?
> 
> oneOf:
>    - enum:
>        - fsl,imx-irqsteer
>        - nxp,s32n79-irqsteer

Yes

Best regards,
Krzysztof