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([2601:586:5000:570:28d9:4790:bc16:cc93]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006cf9084f7d0sm8962060qkb.4.2022.11.02.11.59.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Nov 2022 11:59:44 -0700 (PDT) Message-ID: Date: Wed, 2 Nov 2022 14:59:42 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCHv7 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Content-Language: en-US To: Dinh Nguyen , jh80.chung@samsung.com Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org References: <20221102173843.409039-1-dinguyen@kernel.org> From: Krzysztof Kozlowski In-Reply-To: <20221102173843.409039-1-dinguyen@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org On 02/11/2022 13:38, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen > --- > v7: and "not" for the required "altr,sysmgr-syscon" binding > v6: make "altr,sysmgr-syscon" optional > v5: document reg shift > v4: add else statement > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 33 +++++++++++++++++-- > 1 file changed, 30 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > index ae6d6fca79e2..80dd3d72424f 100644 > --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > > title: Synopsys Designware Mobile Storage Host Controller Binding > > -allOf: > - - $ref: "synopsys-dw-mshc-common.yaml#" > - > maintainers: > - Ulf Hansson > > @@ -38,6 +35,36 @@ properties: > - const: biu > - const: ciu > > + altr,sysmgr-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to the sysmgr node > + - description: register offset that controls the SDMMC clock phase > + - description: register shift for the smplsel(drive in) setting > + description: > + This property is optional. Contains the phandle to System Manager block > + that contains the SDMMC clock-phase control register. The first value is > + the pointer to the sysmgr, the 2nd value is the register offset for the > + SDMMC clock phase register, and the 3rd value is the bit shift for the > + smplsel(drive in) setting. > + > +allOf: > + - $ref: "synopsys-dw-mshc-common.yaml#" Drop the quotes. Best regards, Krzysztof