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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa67d63f867sm679690666b.133.2024.12.12.09.34.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2024 09:34:39 -0800 (PST) Message-ID: Date: Thu, 12 Dec 2024 18:34:37 +0100 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/2] arm64: dts: qcom: x1e80100: Describe the SDHC controllers To: Abel Vesa , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Johan Hovold , Dmitry Baryshkov , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20241212-x1e80100-qcp-sdhc-v4-0-a74c48ee68a3@linaro.org> <20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: b8pPXs-jBtsSUBz-jrn25cl1P6GQVsHJ X-Proofpoint-GUID: b8pPXs-jBtsSUBz-jrn25cl1P6GQVsHJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 malwarescore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120126 On 12.12.2024 5:50 PM, Abel Vesa wrote: > The X Elite platform features two SDHC v5 controllers. > > Describe the controllers along with the pin configuration in TLMM > for the SDC2, since they are hardwired and cannot be muxed to any > other function. The SDC4 pin configuration can be muxed to different > functions, so leave those to board specific dts. > > Signed-off-by: Abel Vesa > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 142 +++++++++++++++++++++++++++++++++ > 1 file changed, 142 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..1584df66ea915230995f0cf662cde813f4ae02a1 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -4094,6 +4094,108 @@ lpass_lpicx_noc: interconnect@7430000 { > #interconnect-cells = <2>; > }; > > + sdhc_2: mmc@8804000 { > + compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0 0x08804000 0 0x1000>; > + > + interrupts = , > + ; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "core", "xo"; > + iommus = <&apps_smmu 0x520 0>; > + qcom,dll-config = <0x0007642c>; > + qcom,ddr-config = <0x80040868>; > + power-domains = <&rpmhpd RPMHPD_CX>; > + operating-points-v2 = <&sdhc2_opp_table>; > + > + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; The comment regarding ICC defines from v3 still stands the rest of the patch looks good Konrad