* Re: [PATCH v3 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Ulf Hansson @ 2016-09-17 9:09 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Ziyuan Xu, Rob Herring, devicetree@vger.kernel.org,
open list:ARM/Rockchip SoC..., linux-mmc, Shawn Lin,
Doug Anderson, zhangqing
In-Reply-To: <1516490.mHlkLq5CeM@phil>
On 17 September 2016 at 11:01, Heiko Stuebner <heiko@sntech.de> wrote:
> Hi,
>
> Am Samstag, 17. September 2016, 10:32:49 CEST schrieb Ziyuan Xu:
>> Add power domain as a optional property for sdhci-of-arasan, which can
>> be turned off in the so-called unused condition, such as suspend and
>> remove. Aim to lower power requirements.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> Acked-by: Rob Herring <robh@kernel.org>
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>
> @Ulf: I guess you'll take this binding change through the mmc tree and I'll
> pick up the devicetree change.
Ideally the documentation and DT change should go together, so I think
it's better for you to pick up both.
I intend to ack it, although it would be nice with some more
information as I requested, in the change-log first.
Kind regards
Uffe
>
>
> Heiko
>
>> ---
>>
>> Changes in v3:
>> - fix a typo
>> - add Rob's ack-tag
>>
>> Changes in v2:
>> - fix a typo
>> - add an example code for power-domain
>>
>> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index
>> 3404afa..eb84d29 100644
>> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
>> @@ -1,12 +1,14 @@
>> Device Tree Bindings for the Arasan SDHCI Controller
>>
>> - The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4]
>> bindings. + The bindings follow the mmc[1], clock[2], interrupt[3], phy[4]
>> and power + domain[5] bindings.
>> Only deviations are documented here.
>>
>> [1] Documentation/devicetree/bindings/mmc/mmc.txt
>> [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
>> [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
>> + [5] Documentation/devicetree/bindings/power/power_domain.txt
>>
>> Required Properties:
>> - compatible: Compatibility string. One of:
>> @@ -36,6 +38,8 @@ Optional Properties:
>> - #clock-cells: If specified this should be the value <0>. With this
>> property in place we will export a clock representing the Card Clock. This
>> clock is expected to be consumed by our PHY. You must also specify + -
>> power-domains: A phandle and PM domain as specifier defined by bindings +
>> of the power controller specified by phandle.
>>
>> Example:
>> sdhci@e0100000 {
>> @@ -71,5 +75,6 @@ Example:
>> phys = <&emmc_phy>;
>> phy-names = "phy_arasan";
>> #clock-cells = <0>;
>> + power-domains = <&power RK3399_PD_EMMC>;
>> status = "disabled";
>> };
>
>
^ permalink raw reply
* Re: RTS5227 errors on mount
From: Ulf Hansson @ 2016-09-17 9:03 UTC (permalink / raw)
To: Don Zickus; +Cc: linux-mmc
In-Reply-To: <20160915151129.GM98438@redhat.com>
On 15 September 2016 at 17:11, Don Zickus <dzickus@redhat.com> wrote:
> Hi Ulf,
>
> My emails to Micky seem to get blocked. Is there a better person to contact
> about the rts5227 chip?
Sorry, I don't know.
Do you think this is a regression? Care to do a bisect?
[...]
Kind regards
Uffe
^ permalink raw reply
* Re: [PATCH v3 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Heiko Stuebner @ 2016-09-17 9:01 UTC (permalink / raw)
To: Ziyuan Xu, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw,
zhangqing-TNX95d0MmH7DzftRWevZcw
In-Reply-To: <20160917023250.1159-2-xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Hi,
Am Samstag, 17. September 2016, 10:32:49 CEST schrieb Ziyuan Xu:
> Add power domain as a optional property for sdhci-of-arasan, which can
> be turned off in the so-called unused condition, such as suspend and
> remove. Aim to lower power requirements.
>
> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Reviewed-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
@Ulf: I guess you'll take this binding change through the mmc tree and I'll
pick up the devicetree change.
Heiko
> ---
>
> Changes in v3:
> - fix a typo
> - add Rob's ack-tag
>
> Changes in v2:
> - fix a typo
> - add an example code for power-domain
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index
> 3404afa..eb84d29 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -1,12 +1,14 @@
> Device Tree Bindings for the Arasan SDHCI Controller
>
> - The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4]
> bindings. + The bindings follow the mmc[1], clock[2], interrupt[3], phy[4]
> and power + domain[5] bindings.
> Only deviations are documented here.
>
> [1] Documentation/devicetree/bindings/mmc/mmc.txt
> [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
> [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
> [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
> + [5] Documentation/devicetree/bindings/power/power_domain.txt
>
> Required Properties:
> - compatible: Compatibility string. One of:
> @@ -36,6 +38,8 @@ Optional Properties:
> - #clock-cells: If specified this should be the value <0>. With this
> property in place we will export a clock representing the Card Clock. This
> clock is expected to be consumed by our PHY. You must also specify + -
> power-domains: A phandle and PM domain as specifier defined by bindings +
> of the power controller specified by phandle.
>
> Example:
> sdhci@e0100000 {
> @@ -71,5 +75,6 @@ Example:
> phys = <&emmc_phy>;
> phy-names = "phy_arasan";
> #clock-cells = <0>;
> + power-domains = <&power RK3399_PD_EMMC>;
> status = "disabled";
> };
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^ permalink raw reply
* Re: [PATCH v3 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Ulf Hansson @ 2016-09-17 8:49 UTC (permalink / raw)
To: Ziyuan Xu
Cc: Heiko Stübner, Rob Herring, devicetree@vger.kernel.org,
open list:ARM/Rockchip SoC..., linux-mmc, Shawn Lin,
Doug Anderson, zhangqing
In-Reply-To: <20160917023250.1159-2-xzy.xu@rock-chips.com>
On 17 September 2016 at 04:32, Ziyuan Xu <xzy.xu@rock-chips.com> wrote:
> Add power domain as a optional property for sdhci-of-arasan, which can
> be turned off in the so-called unused condition, such as suspend and
> remove. Aim to lower power requirements.
I assume runtime suspend make sense as well?
Moreover, perhaps you could share a little information here about what
needs to be done at the driver level which controls the mmc IP. More
precisely, what do you need to do at runtime_suspend, suspend,
runtime_resume, and resume?
Kind regards
Uffe
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
>
> Changes in v3:
> - fix a typo
> - add Rob's ack-tag
>
> Changes in v2:
> - fix a typo
> - add an example code for power-domain
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 3404afa..eb84d29 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -1,12 +1,14 @@
> Device Tree Bindings for the Arasan SDHCI Controller
>
> - The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
> + The bindings follow the mmc[1], clock[2], interrupt[3], phy[4] and power
> + domain[5] bindings.
> Only deviations are documented here.
>
> [1] Documentation/devicetree/bindings/mmc/mmc.txt
> [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
> [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
> [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
> + [5] Documentation/devicetree/bindings/power/power_domain.txt
>
> Required Properties:
> - compatible: Compatibility string. One of:
> @@ -36,6 +38,8 @@ Optional Properties:
> - #clock-cells: If specified this should be the value <0>. With this property
> in place we will export a clock representing the Card Clock. This clock
> is expected to be consumed by our PHY. You must also specify
> + - power-domains: A phandle and PM domain as specifier defined by bindings
> + of the power controller specified by phandle.
>
> Example:
> sdhci@e0100000 {
> @@ -71,5 +75,6 @@ Example:
> phys = <&emmc_phy>;
> phy-names = "phy_arasan";
> #clock-cells = <0>;
> + power-domains = <&power RK3399_PD_EMMC>;
> status = "disabled";
> };
> --
> 2.9.2
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH v3 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399
From: Ziyuan Xu @ 2016-09-17 2:32 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw,
zhangqing-TNX95d0MmH7DzftRWevZcw, Ziyuan Xu
In-Reply-To: <20160917023250.1159-1-xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Control power domain for eMMC via genpd to reduce power consumption.
Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v3: None
Changes in v2:
- add Shawn's review-tag and Doug's review-tag
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 76b2864..13905ce 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -269,6 +269,7 @@
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
+ power-domains = <&power RK3399_PD_EMMC>;
status = "disabled";
};
@@ -690,6 +691,11 @@
status = "disabled";
};
+ qos_emmc: qos@ffa58000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa58000 0x0 0x20>;
+ };
+
qos_gmac: qos@ffa5c000 {
compatible = "syscon";
reg = <0x0 0xffa5c000 0x0 0x20>;
@@ -823,6 +829,11 @@
};
/* These power domains are grouped by VD_LOGIC */
+ pd_emmc@RK3399_PD_EMMC {
+ reg = <RK3399_PD_EMMC>;
+ clocks = <&cru ACLK_EMMC>;
+ pm_qos = <&qos_emmc>;
+ };
pd_gmac@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>;
--
2.9.2
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^ permalink raw reply related
* [PATCH v3 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Ziyuan Xu @ 2016-09-17 2:32 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw,
zhangqing-TNX95d0MmH7DzftRWevZcw, Ziyuan Xu
In-Reply-To: <20160917023250.1159-1-xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Add power domain as a optional property for sdhci-of-arasan, which can
be turned off in the so-called unused condition, such as suspend and
remove. Aim to lower power requirements.
Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
Changes in v3:
- fix a typo
- add Rob's ack-tag
Changes in v2:
- fix a typo
- add an example code for power-domain
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 3404afa..eb84d29 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -1,12 +1,14 @@
Device Tree Bindings for the Arasan SDHCI Controller
- The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
+ The bindings follow the mmc[1], clock[2], interrupt[3], phy[4] and power
+ domain[5] bindings.
Only deviations are documented here.
[1] Documentation/devicetree/bindings/mmc/mmc.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[4] Documentation/devicetree/bindings/phy/phy-bindings.txt
+ [5] Documentation/devicetree/bindings/power/power_domain.txt
Required Properties:
- compatible: Compatibility string. One of:
@@ -36,6 +38,8 @@ Optional Properties:
- #clock-cells: If specified this should be the value <0>. With this property
in place we will export a clock representing the Card Clock. This clock
is expected to be consumed by our PHY. You must also specify
+ - power-domains: A phandle and PM domain as specifier defined by bindings
+ of the power controller specified by phandle.
Example:
sdhci@e0100000 {
@@ -71,5 +75,6 @@ Example:
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
+ power-domains = <&power RK3399_PD_EMMC>;
status = "disabled";
};
--
2.9.2
--
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^ permalink raw reply related
* [PATCH v3 0/2] Add power domain support for eMMC node on rk3399
From: Ziyuan Xu @ 2016-09-17 2:32 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Ziyuan Xu,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
zhangqing-TNX95d0MmH7DzftRWevZcw,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, dianders-F7+t8E8rja9g9hUCZPvPmw,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This series add power domain for eMMC node which will be controlled by
genpd to make sure it's available in probing state, and will be gate
once suspend/resume.
Changes in v3:
- fix a typo
- add Rob's ack-tag
Changes in v2:
- fix a typo
- add an example code for power-domain
- add Shawn's review-tag and Doug's review-tag
Ziyuan Xu (2):
Documentation: mmc: sdhci-of-arasan: add description of power domain
arm64: dts: rockchip: add eMMC's power domain support for rk3399
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
--
2.9.2
^ permalink raw reply
* Re: [PATCH v2 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Ziyuan Xu @ 2016-09-17 2:18 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, heiko-4mtYJXux2i+zQB+pC5nmwQ,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, dianders-F7+t8E8rja9g9hUCZPvPmw,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20160916152535.GA6020@rob-hp-laptop>
Hi Rob,
On 2016年09月16日 23:25, Rob Herring wrote:
> On Thu, Sep 08, 2016 at 02:49:04PM +0800, Ziyuan Xu wrote:
>> Add power domain as a optional property for sdhci-of-arasan, which can
>> be truned off in the so-called unused condition, such as suspend and
> s/truned/turned/
>
>> remove. Aim to lower power requirements.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>
>> ---
>>
>> Changes in v2:
>> - fix a typo
>> - add an example code for power-domain
>>
>> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
> With that,
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Thanks, Rob. I fill fix it and send a follow up patch with your tag.
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>
>
>
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^ permalink raw reply
* Re: xHCI problem? [was Re: Erratic USB device behavior and device loss]
From: Alan Stern @ 2016-09-16 21:40 UTC (permalink / raw)
To: Ritesh Raj Sarraf; +Cc: Ulf Hansson, USB list, linux-mmc
In-Reply-To: <1474040525.18741.1.camel@researchut.com>
On Fri, 16 Sep 2016, Ritesh Raj Sarraf wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA512
>
> Hello Ulf and Alan,
>
> On Thu, 2016-09-15 at 10:16 -0400, Alan Stern wrote:
> > > ---
> > > drivers/mmc/host/rtsx_usb_sdmmc.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c
> > > b/drivers/mmc/host/rtsx_usb_sdmmc.c
> > > index 6c71fc9..a59c7fa 100644
> > > --- a/drivers/mmc/host/rtsx_usb_sdmmc.c
> > > +++ b/drivers/mmc/host/rtsx_usb_sdmmc.c
> > > @@ -1314,6 +1314,7 @@ static void rtsx_usb_update_led(struct work_struct
> > *work)
> > > container_of(work, struct rtsx_usb_sdmmc, led_work);
> > > struct rtsx_ucr *ucr = host->ucr;
> > >
> > > + pm_runtime_get_sync(sdmmc_dev(host));
> > > mutex_lock(&ucr->dev_mutex);
> > >
> > > if (host->led.brightness == LED_OFF)
> > > @@ -1322,6 +1323,7 @@ static void rtsx_usb_update_led(struct work_struct
> > *work)
> > > rtsx_usb_turn_on_led(ucr);
> > >
> > > mutex_unlock(&ucr->dev_mutex);
> > > + pm_runtime_put(sdmmc_dev(host));
> > > }
> > > #endif
> > >
> > > --
> > >
> > > Although, I doubt the above is the main reason to the issues we see.
> >
> > I don't know -- it could well be the reason. The symptoms are
> > definitely what you would expect to see if some thread was doing I/O
> > without calling the pm_runtime_* routines.
> I was able to hit it again. Please find the usbmon trace at:
> https://people.debian.org/~rrs/tmp/usb-4.8.0-rc6ulf1+.log.gz
We're still getting runtime suspends, but now at 2-second intervals.
This is partly because the driver isn't calling
pm_runtime_mark_last_busy(), but there may be more to it. The 2-second
period is the default autosuspend timeout for USB devices. However, I
don't see the activity that rtsx_usb_get_card_status() should produce
when rtsx_usb_suspend() runs; I don't know why not.
We're also getting occasional I/O attempts while the device is
suspended. They must be on some other pathway, not the one fixed by
the patch above. Let's see if we can find out just where they come
from.
Ritesh, please try applying this patch on top of the previous one. It
will produce output in the kernel log whenever these bad I/O attempts
occur. Also, enable dynamic debugging for the rtsx_usb driver:
echo 'module rtsx_usb =p' >/sys/kernel/debug/dynamic_debug/control
before starting the test. (You may need to mount a debugfs filesystem
on /sys/kernel/debug first.)
Alan Stern
Index: usb-4.x/drivers/usb/core/hcd.c
===================================================================
--- usb-4.x.orig/drivers/usb/core/hcd.c
+++ usb-4.x/drivers/usb/core/hcd.c
@@ -1647,6 +1647,8 @@ int usb_hcd_submit_urb (struct urb *urb,
status = map_urb_for_dma(hcd, urb, mem_flags);
if (likely(status == 0)) {
status = hcd->driver->urb_enqueue(hcd, urb, mem_flags);
+ if (status == -EHOSTUNREACH)
+ dump_stack();
if (unlikely(status))
unmap_urb_for_dma(hcd, urb);
}
^ permalink raw reply
* Re: [v4 1/2] mmc: DT: sdhci-brcmstb: Bindings document for common sdhci-brcmstb
From: Rob Herring @ 2016-09-16 19:42 UTC (permalink / raw)
To: Jaedon Shin
Cc: Ulf Hansson, Adrian Hunter, Al Cooper, Florian Fainelli,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
devicetree-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann
In-Reply-To: <20160909020840.2718-2-jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Fri, Sep 09, 2016 at 11:08:39AM +0900, Jaedon Shin wrote:
> Changes to the DT binding document to separate the BCM7425 and the
> BCM7445.
>
> A compatible string "brcm,bcm7425-sdhci" was representing the BCM7425
> SDHCI host controller with all BRCMSTB SoCs including the BCM7445. Now
> it should be separated because vary a bit in initialize each host
> controller.
>
> - Renames the DT binding document to common name.
> - Adds a compatible string "brcm,bcm7445-sdhci" that is representing the
> BCM7445 with thereafter 28nm generation ARM based SoCs.
> - Updates example nodes to represent the BCM7445.
>
> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> .../mmc/{brcm,bcm7425-sdhci.txt => brcm,sdhci-brcmstb.txt} | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
> rename Documentation/devicetree/bindings/mmc/{brcm,bcm7425-sdhci.txt => brcm,sdhci-brcmstb.txt} (81%)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v6 1/2] sdhci-of-arasan: Add device tree parameter xlnx-fails-without-test-cd bit
From: Rob Herring @ 2016-09-16 19:41 UTC (permalink / raw)
To: Zach Brown
Cc: adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA,
soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1473363766-12652-1-git-send-email-zach.brown-acOepvfBmUk@public.gmane.org>
On Thu, Sep 08, 2016 at 02:42:45PM -0500, Zach Brown wrote:
> The sdhci controller on xilinx zynq devices will not function unless
> the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
> In cases where it is impossible to provide the CD bit in hardware,
> setting the controller to test mode and then setting inserted to true
> will get the controller to function without the CD bit.
>
> The device property "xlnx-fails-without-test-cd" will let the arasan
> driver know the controller does not have the CD line wired and that the
> controller does not function without it.
>
> Signed-off-by: Zach Brown <zach.brown-acOepvfBmUk@public.gmane.org>
> ---
> v2:
> * improved commit messages
> * removed fake-cd device property
> * removed fake-cd quirk
> * use broken-cd device property
> * documented new usage of broken-cd
> v3:
> * removed new usage of broken-cd
> * created fails-without-test-cd device property
> * created arasan controller specific quirk
> v4:
> * changed fails-without-test-cd to xlnx-fails-without-test-cd
> * removed extra blank line
> v5:
> * Fixed style mistake
> * Changed (1 << 0 ) to BIT(0)
> v6:
> * Fixed style mistakes
> * Condensed unnecessarily long variable names
> * Removed line wraps that were no longer necessary.
> * Rebased changes off Ulf's mmc tree's next branch.
>
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> df --gt /Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 3404afa..e71f043 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -21,6 +21,10 @@ Required Properties:
> - interrupts: Interrupt specifier
> - interrupt-parent: Phandle for the interrupt controller that services
> interrupts for this device.
> +Optional Properties:
> +- xlnx-fails-without-test-cd: when present, the controller doesn't work when
xlnx,fails...
With that,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: xHCI problem? [was Re: Erratic USB device behavior and device loss]
From: Ritesh Raj Sarraf @ 2016-09-16 15:42 UTC (permalink / raw)
To: Alan Stern, Ulf Hansson; +Cc: USB list, linux-mmc
In-Reply-To: <Pine.LNX.4.44L0.1609151010240.1938-100000@iolanthe.rowland.org>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512
Hello Ulf and Alan,
On Thu, 2016-09-15 at 10:16 -0400, Alan Stern wrote:
> > ---
> > drivers/mmc/host/rtsx_usb_sdmmc.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c
> > b/drivers/mmc/host/rtsx_usb_sdmmc.c
> > index 6c71fc9..a59c7fa 100644
> > --- a/drivers/mmc/host/rtsx_usb_sdmmc.c
> > +++ b/drivers/mmc/host/rtsx_usb_sdmmc.c
> > @@ -1314,6 +1314,7 @@ static void rtsx_usb_update_led(struct work_struct
> *work)
> > container_of(work, struct rtsx_usb_sdmmc, led_work);
> > struct rtsx_ucr *ucr = host->ucr;
> >
> > + pm_runtime_get_sync(sdmmc_dev(host));
> > mutex_lock(&ucr->dev_mutex);
> >
> > if (host->led.brightness == LED_OFF)
> > @@ -1322,6 +1323,7 @@ static void rtsx_usb_update_led(struct work_struct
> *work)
> > rtsx_usb_turn_on_led(ucr);
> >
> > mutex_unlock(&ucr->dev_mutex);
> > + pm_runtime_put(sdmmc_dev(host));
> > }
> > #endif
> >
> > --
> >
> > Although, I doubt the above is the main reason to the issues we see.
>
> I don't know -- it could well be the reason. The symptoms are
> definitely what you would expect to see if some thread was doing I/O
> without calling the pm_runtime_* routines.
>
> > Instead I think somehow the parent device (usb device) isn't being
> > properly managed through runtime PM, but not due to wrong deployment
> > in the mmc core nor in the rtsx_usb_driver, but at some place else.
> > :-)
> >
> > I started looking for calls to pm_suspend_ignore_children(dev, true),
> > which would decouple the usb device from the mmc platform device from
> > a runtime PM point of view. I found one suspicious case!
> >
> > drivers/usb/storage/realtek_cr.c:
> > pm_suspend_ignore_children(&us->pusb_intf->dev, true);
> >
> > As I am not so familiar with USB, I can't really tell why the above
> > exists, although perhaps just removing that line would be worth a
> > try!?
>
> No, the realtek_cr driver has no connection with this. It's a
> sub-module of the usb_storage driver; it uses the SCSI interface,
> not the MMC interface.
>
> > If neither of the above works, the next step could be to start
> > checking error codes in the mmc core and in the rtsx_usb_sdmmc driver,
> > from the calls to pm_runtime_get|put() and pm_runtime_enable().
>
> Let's see what this patch does.
I was able to hit it again. Please find the usbmon trace at:
https://people.debian.org/~rrs/tmp/usb-4.8.0-rc6ulf1+.log.gz
- --
Ritesh Raj Sarraf
RESEARCHUT - http://www.researchut.com
"Necessity is the mother of invention."
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^ permalink raw reply
* Re: [PATCH v2 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Rob Herring @ 2016-09-16 15:25 UTC (permalink / raw)
To: Ziyuan Xu
Cc: heiko-4mtYJXux2i+zQB+pC5nmwQ, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw
In-Reply-To: <20160908064905.18080-2-xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
On Thu, Sep 08, 2016 at 02:49:04PM +0800, Ziyuan Xu wrote:
> Add power domain as a optional property for sdhci-of-arasan, which can
> be truned off in the so-called unused condition, such as suspend and
s/truned/turned/
> remove. Aim to lower power requirements.
>
> Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> ---
>
> Changes in v2:
> - fix a typo
> - add an example code for power-domain
>
> Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
With that,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* [RESEND PATCH v7 2/2] sdhci-of-arasan: Set controller to test mode when xlnx,fails-without-test-cd is present
From: Zach Brown @ 2016-09-16 15:01 UTC (permalink / raw)
To: adrian.hunter
Cc: robh+dt, ulf.hansson, mark.rutland, linux-mmc, devicetree,
linux-kernel, michal.simek, soren.brinkmann, linux-arm-kernel
In-Reply-To: <1474038102-20937-1-git-send-email-zach.brown@ni.com>
The sdhci controller on xilinx zynq devices will not function unless
the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
In cases where it is impossible to provide the CD bit in hardware,
setting the controller to test mode and then setting inserted to true
will get the controller to function without the CD bit.
When the device has the property xlnx,fails-without-test-cd the driver
changes the controller to test mode and sets test inserted to true to
make the controller function.
Signed-off-by: Zach Brown <zach.brown@ni.com>
---
drivers/mmc/host/sdhci-of-arasan.c | 27 ++++++++++++++++++++++++++-
drivers/mmc/host/sdhci.h | 2 ++
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 33601a8..da8e40a 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -26,6 +26,7 @@
#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include "sdhci-pltfm.h"
+#include <linux/of.h>
#define SDHCI_ARASAN_CLK_CTRL_OFFSET 0x2c
#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
@@ -98,6 +99,10 @@ struct sdhci_arasan_data {
struct regmap *soc_ctl_base;
const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
+ unsigned int quirks; /* Arasan deviations from spec */
+
+/* Controller does not have CD wired and will not function normally without */
+#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
};
static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
@@ -245,12 +250,27 @@ static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
}
+void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
+{
+ u8 ctrl;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+
+ sdhci_reset(host, mask);
+
+ if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+ ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ }
+}
+
static struct sdhci_ops sdhci_arasan_ops = {
.set_clock = sdhci_arasan_set_clock,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_arasan_get_timeout_clock,
.set_bus_width = sdhci_set_bus_width,
- .reset = sdhci_reset,
+ .reset = sdhci_arasan_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
};
@@ -545,6 +565,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_arasan_data *sdhci_arasan;
+ struct device_node *np = pdev->dev.of_node;
host = sdhci_pltfm_init(pdev, &sdhci_arasan_pdata,
sizeof(*sdhci_arasan));
@@ -599,6 +620,10 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
}
sdhci_get_of_property(pdev);
+
+ if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
+ sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
+
pltfm_host->clk = clk_xin;
if (of_device_is_compatible(pdev->dev.of_node,
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index a2bc9e1..c722cd2 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -84,6 +84,8 @@
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
#define SDHCI_CTRL_8BITBUS 0x20
+#define SDHCI_CTRL_CDTEST_INS 0x40
+#define SDHCI_CTRL_CDTEST_EN 0x80
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
--
2.7.4
^ permalink raw reply related
* [RESEND PATCH v7 1/2] sdhci-of-arasan: Add device tree parameter xlnx,fails-without-test-cd bit
From: Zach Brown @ 2016-09-16 15:01 UTC (permalink / raw)
To: adrian.hunter-ral2JQCrhuEAvxtiuMwx3w
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA,
soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
The sdhci controller on xilinx zynq devices will not function unless
the CD bit is provided. http://www.xilinx.com/support/answers/61064.html
In cases where it is impossible to provide the CD bit in hardware,
setting the controller to test mode and then setting inserted to true
will get the controller to function without the CD bit.
The device property "xlnx,fails-without-test-cd" will let the arasan
driver know the controller does not have the CD line wired and that the
controller does not function without it.
Signed-off-by: Zach Brown <zach.brown-acOepvfBmUk@public.gmane.org>
---
v2:
* improved commit messages
* removed fake-cd device property
* removed fake-cd quirk
* use broken-cd device property
* documented new usage of broken-cd
v3:
* removed new usage of broken-cd
* created fails-without-test-cd device property
* created arasan controller specific quirk
v4:
* changed fails-without-test-cd to xlnx-fails-without-test-cd
* removed extra blank line
v5:
* Fixed style mistake
* Changed (1 << 0 ) to BIT(0)
v6:
* Fixed style mistakes
* Condensed unnecessarily long variable names
* Removed line wraps that were no longer necessary.
* Rebased changes off Ulf's mmc tree's next branch.
v7:
* Removed erroneous re-creation of Optional Properties section
* Changed xlnx-fails-without-test-cd to xlnx,fails-without-test-cd
* Changed of_get_property to of_property_read_bool
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 3404afa..49df630 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -36,6 +36,9 @@ Optional Properties:
- #clock-cells: If specified this should be the value <0>. With this property
in place we will export a clock representing the Card Clock. This clock
is expected to be consumed by our PHY. You must also specify
+ - xlnx,fails-without-test-cd: when present, the controller doesn't work when
+ the CD line is not connected properly, and the line is not connected
+ properly. Test mode can be used to force the controller to function.
Example:
sdhci@e0100000 {
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH v7 08/11] arm64: dts: r8a7796: add SDHI nodes
From: Simon Horman @ 2016-09-16 10:53 UTC (permalink / raw)
To: Wolfram Sang
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <20160916103048.GL1411@katana>
On Fri, Sep 16, 2016 at 12:30:48PM +0200, Wolfram Sang wrote:
> On Tue, Sep 13, 2016 at 12:57:05PM +0200, Simon Horman wrote:
> > Add SDHI nodes to the DT of the r8a7796 SoC.
> >
> > Based on the DT of the r8a7795 SoC.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> If you remove the two lines you removed from H3 already:
Thanks, done.
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
^ permalink raw reply
* Re: [PATCH v7 07/11] ARM: dts: alt: Enable UHS-I SDR-50 and SDR-104
From: Simon Horman @ 2016-09-16 10:44 UTC (permalink / raw)
To: Wolfram Sang
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <20160916102710.GJ1411@katana>
On Fri, Sep 16, 2016 at 12:27:10PM +0200, Wolfram Sang wrote:
> On Tue, Sep 13, 2016 at 12:57:04PM +0200, Simon Horman wrote:
> > Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1}.
> > And the sd-uhs-sdr104 property to SDHI0.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> If you drop sdr104 here for now as well:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks, done.
The result is as follows:
From: Simon Horman <horms+renesas@verge.net.au>
Date: Tue, 13 Sep 2016 12:57:04 +0200
Subject: [PATCH] ARM: dts: alt: enable UHS for SDHI 0 & 1
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1}.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7794-alt.dts | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8d1b35afaf82..325d3f972c57 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -207,11 +207,25 @@
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
};
@@ -255,23 +269,27 @@
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* Re: [PATCH v7 10/11] arm64: dts: r8a7796: salvator-x: enable UHS for SDHI 0 & 3
From: Wolfram Sang @ 2016-09-16 10:33 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <1473764228-24768-11-git-send-email-horms+renesas@verge.net.au>
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On Tue, Sep 13, 2016 at 12:57:07PM +0200, Simon Horman wrote:
> Based on work for the r8a7796 by Wolfram Sang.
>
> Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH v7 09/11] arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3
From: Wolfram Sang @ 2016-09-16 10:32 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <1473764228-24768-10-git-send-email-horms+renesas@verge.net.au>
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On Tue, Sep 13, 2016 at 12:57:06PM +0200, Simon Horman wrote:
> Enable the exposed SD card slots in the DT of the r8a7796/salvator-x.
>
> Based on work for the r8a7795/salvator-x by Ai Kyuse.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH v7 08/11] arm64: dts: r8a7796: add SDHI nodes
From: Wolfram Sang @ 2016-09-16 10:30 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <1473764228-24768-9-git-send-email-horms+renesas@verge.net.au>
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On Tue, Sep 13, 2016 at 12:57:05PM +0200, Simon Horman wrote:
> Add SDHI nodes to the DT of the r8a7796 SoC.
>
> Based on the DT of the r8a7795 SoC.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
If you remove the two lines you removed from H3 already:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> + sdhi2: sd@ee140000 {
> + compatible = "renesas,sdhi-r8a7796";
> + reg = <0 0xee140000 0 0x2000>;
> + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 312>;
> + max-frequency = <200000000>;
> + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> + cap-mmc-highspeed;
This one...
> + status = "disabled";
> + };
> +
> + sdhi3: sd@ee160000 {
> + compatible = "renesas,sdhi-r8a7796";
> + reg = <0 0xee160000 0 0x2000>;
> + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 311>;
> + max-frequency = <200000000>;
> + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
> + cap-mmc-highspeed;
... and ditto.
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^ permalink raw reply
* Re: [PATCH v5 07/11] arm64: dts: r8a7795: remove unnecessary cap-mmc-highspeed property
From: Wolfram Sang @ 2016-09-16 10:29 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc
In-Reply-To: <1472591399-13907-8-git-send-email-horms+renesas@verge.net.au>
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On Tue, Aug 30, 2016 at 11:09:55PM +0200, Simon Horman wrote:
> Remove cap-mmc-highspeed property from SDHI2 and SDHI3.
>
> This property is unnecessary as the driver automatically sets
> the highspeed capability. Furthermore its use is inconsistent with SDHI0
> and SDHI1 which are also highspeed capable but do not have this property
> present.
>
> Found by inspection.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
For completeness:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH v7 07/11] ARM: dts: alt: Enable UHS-I SDR-50 and SDR-104
From: Wolfram Sang @ 2016-09-16 10:27 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <1473764228-24768-8-git-send-email-horms+renesas@verge.net.au>
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On Tue, Sep 13, 2016 at 12:57:04PM +0200, Simon Horman wrote:
> Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1}.
> And the sd-uhs-sdr104 property to SDHI0.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
If you drop sdr104 here for now as well:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH v7 06/11] ARM: dts: r8a7794: set maximum frequency for SDHI clocks
From: Wolfram Sang @ 2016-09-16 10:26 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <1473764228-24768-7-git-send-email-horms+renesas@verge.net.au>
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On Tue, Sep 13, 2016 at 12:57:03PM +0200, Simon Horman wrote:
> Define the upper limit otherwise the driver cannot utilize max speeds.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH v7 05/11] ARM: dts: koelsch: Enable UHS-I SDR-50 and SDR-104
From: Wolfram Sang @ 2016-09-16 10:23 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <20160916100031.GH14562@verge.net.au>
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On Fri, Sep 16, 2016 at 12:00:32PM +0200, Simon Horman wrote:
> On Tue, Sep 13, 2016 at 12:57:02PM +0200, Simon Horman wrote:
> > Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}.
> > And the sd-uhs-sdr104 property to SDHI0.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> As SDR50 support is present in the driver in mainline (correct me if I am
> wrong!) I have queued this up after dropping the sdr104 portion and
> updating the changelog accordingly.
Looks good!
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
* Re: [PATCH v7 02/11] arm64: dts: r8a7795: salvator-x: enable UHS for SDHI 0 & 3
From: Wolfram Sang @ 2016-09-16 10:22 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Ulf Hansson, Magnus Damm, linux-mmc,
linux-renesas-soc, linux-arm-kernel
In-Reply-To: <20160916095500.GG14562@verge.net.au>
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On Fri, Sep 16, 2016 at 11:55:00AM +0200, Simon Horman wrote:
> On Tue, Sep 13, 2016 at 12:56:59PM +0200, Simon Horman wrote:
> > From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> As SDR50 support is present in the driver in mainline (correct me if I am
> wrong!) I am queuing this up.
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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^ permalink raw reply
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