* Re: [PATCH PoC 0/7] mmc: switch to blk-mq
From: Linus Walleij @ 2016-09-30 0:50 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz
Cc: Ulf Hansson, Greg KH, Paolo Valente, Jens Axboe, Hannes Reinecke,
Tejun Heo, Omar Sandoval, Christoph Hellwig,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
Arnd Bergmann
In-Reply-To: <1474552630-28314-1-git-send-email-b.zolnierkie@samsung.com>
On Thu, Sep 22, 2016 at 6:57 AM, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
> Since Linus Walleij is also working on that and I won't
> probably have time to touch this code till the end of
> upcoming month, here it is (basically a code dump of my
> proof-of-concept work). I hope that it would be useful
> to somebody.
>
> It is extremely ugly & full of bogus debug code but boots
> fine on my Odroid-XU3 and benchmarks can be run.
Haha, it is still good discussion material.
FWIW your patchset is way more advanced than whatever I
cooked up, and the approach taken: first rip out async requests,
then adding a mq callback block and add async requests back
after adding a function to monitor if the queue is busy is a way
better approach.
I sat down with Ulf Hansson and Arnd Bergmann to discuss the
material and issues we face if/when migrating the MMC/SD code
to blk-mq.
Just for context to everyone: MMC/SD has an asynchronous
request handling that achieves a call all the way into the driver
to do some DMA mapping (flush) of SGlists with dma_map_sg()
before the hardware start processing the actual request. There
is a post_req() callback as well performing dma_unmap_sg().
This is mostly a non-issue on coherent memory architectures
like x86, but gives a nice performance boost on ARM (etc)
systems. In theory the callback could be used for other stuff
but all current drivers ultimately call
dma_map_sg()/dma_unmap_sg().
The interesting solution to achieve asynchronous requests,
a.k.a. double-buffering a.k.a. request pipelining is basically this
from the last patch:
- mq->qdepth = 1;
+ mq->qdepth = 2;
So we claim that the hardware queue has a depth of two
requests but well... that is not really true. If we start confusing
concepts like this to get parallelism, what shall we set this
to when we exploit command queueing and actually have a
queue depth of say 64? that will result in a pile of hacks.
The proper solution would be to augment struct blk_mq_ops
vtable with a .pre_queue_rq() and .post_complete_rq() or
something.
The way I read the code the init_request() and exit_request()
callbacks cannot be used as they only deal with allocating the
struct and this seems to happen before the request is actually
filled in with the data (correct me if I don't understand this right!)
this seems to be confirmed by the presence of a .reinit_request()
callback. So we can't map/unmap the requests in these
callbacks.
We noted that this dma map/upmap optimization can also be
applicable for USB mass storage, so we get an optimization
from the MQ block layer that we can reuse in more than
MMC/SD.
After this we will still run into the same issue that you find after
this patchset: regressions in performance because of the
absence of an elevator/scheduler algorithm in blk-mq. So we
cannot really apply the patch set before or at the same time
as we're fixing that.
Apart from that we saw some really arcane things in the
MMC/SD core, mmc_claim_host() being the most obvious
example, as far as we can tell some kind of reimplementation of
mutex_trylock(). Some serious cleanup may be needed here.
It's nice that your first patch rips out the quirky kthread that
polls the block queue for new requests and send them down
to the mmc core, including picking out a few NULL requests
and flusing it's asynch work queue with that.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [RESEND PATCH v2 1/4] mmc: core: switch to 1V8 or 1V2 for hs400es mode
From: Doug Anderson @ 2016-09-29 19:49 UTC (permalink / raw)
To: Shawn Lin
Cc: Ulf Hansson, Adrian Hunter, Jaehoon Chung,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
open list:ARM/Rockchip SoC..., stable@vger.kernel.org, 4.4#
In-Reply-To: <1474589577-11193-1-git-send-email-shawn.lin@rock-chips.com>
Hi,
On Thu, Sep 22, 2016 at 5:12 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> When introducing hs400es, I didn't notice that we haven't
> switched voltage to 1V2 or 1V8 for it. That happens to work
> as the first controller claiming to support hs400es, arasan(5.1),
> which is designed to only support 1V8. So the voltage is fixed to 1V8.
> But it actually is wrong, and will not fit for other host controllers.
> Let's fix it.
>
> Fixes: commit 81ac2af65793ecf ("mmc: core: implement enhanced strobe support")
> Cc: <stable@vger.kernel.org> 4.4#
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>
> ---
>
> Changes in v2:
> - fix copy-paste error, mea culpa
>
> drivers/mmc/core/mmc.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
This matches what's done for hs200 and also seems sane.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply
* Re: [PATCH v2 4/4] mmc: sdhci-of-arasan: add sdhci_arasan_voltage_switch for arasan,5.1
From: Doug Anderson @ 2016-09-29 19:49 UTC (permalink / raw)
To: Shawn Lin
Cc: Jaehoon Chung, Ulf Hansson, linux-mmc@vger.kernel.org,
linux-kernel@vger.kernel.org, open list:ARM/Rockchip SoC...
In-Reply-To: <1474588991-10344-4-git-send-email-shawn.lin@rock-chips.com>
Hi,
On Thu, Sep 22, 2016 at 5:03 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> Per the vendor's requirement, we shouldn't do any setting for
> 1.8V Signaling Enable, otherwise the interaction/behaviour between
> phy and controller will be undefined. Mostly it works fine if we do
> that, but we still see failures. Anyway, let's fix it to meet the
> vendor's requirement. The error log looks like:
>
> [ 93.405085] mmc1: unexpected status 0x800900 after switch
> [ 93.408474] mmc1: switch to bus width 1 failed
> [ 93.408482] mmc1: mmc_select_hs200 failed, error -110
> [ 93.408492] mmc1: error -110 during resume (card was removed?)
> [ 93.408705] PM: resume of devices complete after 213.453 msecs
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v2: None
>
> drivers/mmc/host/sdhci-of-arasan.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
Seems OK to me.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply
* Re: [RESEND PATCH v2 2/4] mmc: core: changes frequency to hs_max_dtr when selecting hs400es
From: Doug Anderson @ 2016-09-29 19:47 UTC (permalink / raw)
To: Shawn Lin
Cc: Ulf Hansson, Adrian Hunter, Jaehoon Chung,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
open list:ARM/Rockchip SoC...
In-Reply-To: <1474589577-11193-2-git-send-email-shawn.lin@rock-chips.com>
Hi,
On Thu, Sep 22, 2016 at 5:12 PM, Shawn Lin <shawn.lin@rock-chips.com> wrote:
> Per JESD84-B51 P69, Host need to change frequency to <=52MHz
Technically Page 49. In the PDF you go to page 69, but the heading on
the top of the page says 49.
> after setting HS_TIMING to 0x1, and host may changes frequency
> to <= 200MHz after setting HS_TIMING to 0x3. That means the card
> expects the clock rate to increase from the current used f_init
> (which is less than 400KHz, but still being less than 52MHz) to
> 52MHz, otherwise we find some eMMC devices significantly report
> failure when sending status.
Technically it seems like things ought to be OK at the slow speed
since technically we're allowed to talk "high speed" at 400 kHZ (or at
any rate <= 52MHz). ...but I guess I could also see some cards not
liking that. Though I'm no expert, feel free to add my reviewed-by if
it is useful:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply
* Re: [RESEND PATCH v2 4/4] mmc: sdhci-of-arasan: add sdhci_arasan_voltage_switch for arasan,5.1
From: Adrian Hunter @ 2016-09-28 8:20 UTC (permalink / raw)
To: Shawn Lin, Ulf Hansson
Cc: Jaehoon Chung, linux-mmc, linux-kernel, linux-rockchip
In-Reply-To: <1474589577-11193-4-git-send-email-shawn.lin@rock-chips.com>
On 23/09/16 03:12, Shawn Lin wrote:
> Per the vendor's requirement, we shouldn't do any setting for
> 1.8V Signaling Enable, otherwise the interaction/behaviour between
> phy and controller will be undefined. Mostly it works fine if we do
> that, but we still see failures. Anyway, let's fix it to meet the
> vendor's requirement. The error log looks like:
>
> [ 93.405085] mmc1: unexpected status 0x800900 after switch
> [ 93.408474] mmc1: switch to bus width 1 failed
> [ 93.408482] mmc1: mmc_select_hs200 failed, error -110
> [ 93.408492] mmc1: error -110 during resume (card was removed?)
> [ 93.408705] PM: resume of devices complete after 213.453 msecs
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
>
> Changes in v2: None
>
> drivers/mmc/host/sdhci-of-arasan.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index da8e40a..1573a8d 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -265,6 +265,28 @@ void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
> }
> }
>
> +static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
> + struct mmc_ios *ios)
> +{
> + switch (ios->signal_voltage) {
> + case MMC_SIGNAL_VOLTAGE_180:
> + /*
> + * Plese don't switch to 1V8 as arasan,5.1 doesn't
> + * actually refer to this setting to indicate the
> + * signal voltage and the state machine will be broken
> + * actually if we force to enable 1V8. That's something
> + * like broken quirk but we could work around here.
> + */
> + return 0;
> + case MMC_SIGNAL_VOLTAGE_330:
> + case MMC_SIGNAL_VOLTAGE_120:
> + /* We don't support 3V3 and 1V2 */
> + break;
> + }
> +
> + return -EINVAL;
> +}
> +
> static struct sdhci_ops sdhci_arasan_ops = {
> .set_clock = sdhci_arasan_set_clock,
> .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> @@ -661,6 +683,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
>
> host->mmc_host_ops.hs400_enhanced_strobe =
> sdhci_arasan_hs400_enhanced_strobe;
> + host->mmc_host_ops.start_signal_voltage_switch =
> + sdhci_arasan_voltage_switch;
> }
>
> ret = sdhci_add_host(host);
>
^ permalink raw reply
* [PATCH v4 1/2] Documentation: mmc: sdhci-of-arasan: add description of power domain
From: Ziyuan Xu @ 2016-09-27 6:15 UTC (permalink / raw)
To: heiko, ulf.hansson, robh+dt
Cc: devicetree, linux-rockchip, linux-mmc, shawn.lin, dianders,
zhangqing, Ziyuan Xu
In-Reply-To: <20160927061558.2110-1-xzy.xu@rock-chips.com>
Add power domain as a optional property for sdhci-of-arasan, which can
be turned off in the so-called unused condition, such as suspend and
remove. Aim to lower power requirements.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
Changes in v4:
- add heiko's review-tag
Changes in v3:
- fix a typo
- add Rob's ack-tag
Changes in v2:
- fix a typo
- add an example code for power-domain
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index 3404afa..eb84d29 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -1,12 +1,14 @@
Device Tree Bindings for the Arasan SDHCI Controller
- The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
+ The bindings follow the mmc[1], clock[2], interrupt[3], phy[4] and power
+ domain[5] bindings.
Only deviations are documented here.
[1] Documentation/devicetree/bindings/mmc/mmc.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
[3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[4] Documentation/devicetree/bindings/phy/phy-bindings.txt
+ [5] Documentation/devicetree/bindings/power/power_domain.txt
Required Properties:
- compatible: Compatibility string. One of:
@@ -36,6 +38,8 @@ Optional Properties:
- #clock-cells: If specified this should be the value <0>. With this property
in place we will export a clock representing the Card Clock. This clock
is expected to be consumed by our PHY. You must also specify
+ - power-domains: A phandle and PM domain as specifier defined by bindings
+ of the power controller specified by phandle.
Example:
sdhci@e0100000 {
@@ -71,5 +75,6 @@ Example:
phys = <&emmc_phy>;
phy-names = "phy_arasan";
#clock-cells = <0>;
+ power-domains = <&power RK3399_PD_EMMC>;
status = "disabled";
};
--
2.9.3
^ permalink raw reply related
* [PATCH v4 2/2] arm64: dts: rockchip: add eMMC's power domain support for rk3399
From: Ziyuan Xu @ 2016-09-27 6:15 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw,
zhangqing-TNX95d0MmH7DzftRWevZcw, Ziyuan Xu
In-Reply-To: <20160927061558.2110-1-xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Control power domain for eMMC via genpd to reduce power consumption.
Signed-off-by: Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Ziyuan Xu <xzy.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- add Shawn's review-tag and Doug's review-tag
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 76b2864..13905ce 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -269,6 +269,7 @@
#clock-cells = <0>;
phys = <&emmc_phy>;
phy-names = "phy_arasan";
+ power-domains = <&power RK3399_PD_EMMC>;
status = "disabled";
};
@@ -690,6 +691,11 @@
status = "disabled";
};
+ qos_emmc: qos@ffa58000 {
+ compatible = "syscon";
+ reg = <0x0 0xffa58000 0x0 0x20>;
+ };
+
qos_gmac: qos@ffa5c000 {
compatible = "syscon";
reg = <0x0 0xffa5c000 0x0 0x20>;
@@ -823,6 +829,11 @@
};
/* These power domains are grouped by VD_LOGIC */
+ pd_emmc@RK3399_PD_EMMC {
+ reg = <RK3399_PD_EMMC>;
+ clocks = <&cru ACLK_EMMC>;
+ pm_qos = <&qos_emmc>;
+ };
pd_gmac@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>;
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v4 0/2] Add power domain support for eMMC node on rk3399
From: Ziyuan Xu @ 2016-09-27 6:15 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, dianders-F7+t8E8rja9g9hUCZPvPmw,
zhangqing-TNX95d0MmH7DzftRWevZcw, Ziyuan Xu
This series add power domain for eMMC node which will be controlled by
genpd to make sure it's available in probing state, and will be gate
once suspend/resume.
Changes in v4:
- add heiko's review-tag
Changes in v3:
- fix a typo
- add Rob's ack-tag
Changes in v2:
- fix a typo
- add an example code for power-domain
- add Shawn's review-tag and Doug's review-tag
Ziyuan Xu (2):
Documentation: mmc: sdhci-of-arasan: add description of power domain
arm64: dts: rockchip: add eMMC's power domain support for rk3399
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 7 ++++++-
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 11 +++++++++++
2 files changed, 17 insertions(+), 1 deletion(-)
--
2.9.3
--
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^ permalink raw reply
* Re: [PATCH v4 3/9] mmc: sdhci-msm: add pltfm_data support to get clk-rates from DT
From: Ritesh Harjani @ 2016-09-27 5:06 UTC (permalink / raw)
To: Arnd Bergmann
Cc: adrian.hunter, ulf.hansson, linux-mmc, shawn.lin, linux-arm-msm,
georgi.djakov, alex.lemberg, mateusz.nowak, Yuliy.Izrailov,
asutoshd, david.griego, stummala, venkatg, pramod.gurav,
bjorn.andersson
In-Reply-To: <2575923.JUIzEdKygq@wuerfel>
Hi Arnd,
On 9/12/2016 1:03 PM, Arnd Bergmann wrote:
> On Wednesday, August 24, 2016 3:33:38 PM CEST Ritesh Harjani wrote:
>> #define CMUX_SHIFT_PHASE_SHIFT 24
>> #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
>>
>> +struct sdhci_msm_pltfm_data {
>> + u32 *clk_table;
>> + int clk_table_sz;
>> +};
>> +
>> struct sdhci_msm_host {
>> struct platform_device *pdev;
>> void __iomem *core_mem; /* MSM SDCC mapped address */
>> @@ -83,6 +88,7 @@ struct sdhci_msm_host {
>> struct clk *bus_clk; /* SDHC bus voter clock */
>> struct mmc_host *mmc;
>> bool use_14lpp_dll_reset;
>> + struct sdhci_msm_pltfm_data *pdata;
>> };
>>
>> /* Platform specific tuning */
>>
>
> Just noticed this. Please don't add another structure, just put the
> new members into struct sdhci_msm_host directly.
>
> We only need platform_data structures for drivers that also work
> with old-style board files, which this one doesn't.
Ok, I will move this into sdhci_msm_host directly.
Thanks
Ritesh
>
> Arnd
>
^ permalink raw reply
* Re: [PATCH v3] mmc: sdhci-msm: Add pm_runtime and system PM support
From: Ritesh Harjani @ 2016-09-27 4:40 UTC (permalink / raw)
To: Ulf Hansson
Cc: Pramod Gurav, Georgi Djakov, Adrian Hunter, linux-mmc,
open list:ARM/QUALCOMM SUPPORT, open list, Stephen Boyd
In-Reply-To: <CAPDyKFpVEYz+sGNHG_z2AwXuiDe9kSRk1sh8_p4V3m7FpwPOSg@mail.gmail.com>
Hi Ulf,
On 9/23/2016 3:37 PM, Ulf Hansson wrote:
> [...]
>
>>>>> Is there anything else needed in msm sdhci driver so that the auto
>>>>> tuning is taken care of?
>>>>
>>>>
>>>> I am not familiar with any other than sdhci-esdhc-imx which supports
>>>> the SDHCI_TUNING_MODE_3. I may be wrong though.
>>>>
>>>> In the sdhci-esdhc-imx case, enabling of auto tuning seems to be done
>>>> in esdhc_post_tuning(), where a vendor specific register
>>>> (ESDHC_MIX_CTRL) is being written to. Perhaps something similar in
>>>> your case?
>>>>
>>> Thanks Ulf for the comments. Will check this and see if there is
>>> something of this sort we have to do to achieve auto tuning.
>>> Adding Ritesh who has been posting some SDHCI MSM patches recently in
>>> case he knows about this.
>>
>>
>> Internally, we don't use this Auto re-tuning and rely on explicit re-tune by
>> host driver.
>>
>> Question though -
>> 1. why do we need to call sdhci_runtime_resume/suspend from
>> sdhci_msm_runtime_suspend/resume?
>> From what I see is, sdhci_runtime_susend/resume will do reset and re-program
>> of host->pwr and host->clk because of which a retune will be required for
>> the next command after runtime resume.
>>
>> We can *only* disable and enable the clocks in
>> sdhci_msm_runtime_suspend/resume?
>> Thoughts? With this, I suppose you would not see any issue.
>
> I see.
>
> I assumes that means saving/restoring register context will
> automatically handled by some other outer logic, when doing clock
> gating/ungating?
>
> In other words, if the controller has valid tuning values, those will
> be re-used and restored when clock ungating happens?
Yes, that is my understanding too. I double confirmed with HW team about
this. So, even if we gate the clock directly at GCC, sdhc msm controller
is capable of restoring it's register values.
In this case, it is not required to call for
sdhci_runtime_suspend/resume from sdhci_msm_runtime routines right?
Instead we can only have disabling/enabling of clks from
sdhci_msm_runtime_suspend/resume. Does this sounds good?
>
>>
>>
>> Though for this issue, since internally also auto retuning is never used, we
>> can have this mode disabled. I can once again check with HW team to get more
>> details about this mode for MSM controller.
>>
>>>
>>> Regards,
>>> Pramod
>>>
>>
>
> Kind regards
> Uffe
> --
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>
^ permalink raw reply
* MMC timeout issue on 4.6 kernel
From: Sai Krishna Potthuri @ 2016-09-26 16:58 UTC (permalink / raw)
To: linux-mmc@vger.kernel.org; +Cc: Ulf Hansson
Hi,
With 4.6 kernel, I am doing regression test on SD which does following things.
1. Mount SD card.
2. Read and write random 1MB data.
3. Reboot the board.
I am facing following error while reading the data from the SD card.
mmc0: Timeout waiting for hardware interrupt.
mmcblk0: error -110 transferring data, sector 8194, nr 2, cmd response 0x900, card status 0xb00
mmc0: tried to reset card
mmc0: Timeout waiting for hardware interrupt.
mmcblk0: error -110 transferring data, sector 8194, nr 2, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmc0: Timeout waiting for hardware interrupt.
mmcblk0: error -110 transferring data, sector 8194, nr 2, cmd response 0x900, card status 0x0
blk_update_request: I/O error, dev mmcblk0, sector 8194
mmc0: Timeout waiting for hardware interrupt.
mmcblk0: error -110 transferring data, sector 8195, nr 1, cmd response 0x900, card status 0x0
blk_update_request: I/O error, dev mmcblk0, sector 8195
EXT2-fs (mmcblk0p1): error: unable to read superblock
mmc0: Timeout waiting for hardware interrupt.
mmcblk0: error -110 transferring data, sector 16387, nr 61, cmd response 0x900, card status 0xb00
mmc0: tried to reset card
Getting this error once in a while in regression test after several runs.
I am not seeing this issue with 4.5 kernel.
Please let me know if anyone has seen this issue.
Regards
Sai Krishna
^ permalink raw reply
* Re: [PATCH 0/3] mmc: Check BKOPS Level On Runtime Suspend
From: Alex Lemberg @ 2016-09-26 15:10 UTC (permalink / raw)
To: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org; +Cc: Avi Shchislowski
In-Reply-To: <1472739890-3384-1-git-send-email-alex.lemberg@sandisk.com>
Hi Ulf,
Could you please review this?
Thanks,
Alex
On 9/1/16, 5:24 PM, "Alex Lemberg" <Alex.Lemberg@sandisk.com> wrote:
>Flash based storage devices might need to perform the internal
>Background Operations (BKOPS) in order to insure better performance
>for the next coming IO.
>Following the discussion in the mmc thread:
>www.spinics.net/lists/linux-mmc/msg37779.html
>To let the device complete its BKOPS during Runtime Suspend,
>we suggest to check the BKOPS level.
>In case the device need to complete its BKOPS, reschedule the Runtime
>Suspend.
>
>alex lemberg (3):
> mmc: replacing hardcoded value for runtime PM suspend
> mmc: Adding AUTO_BKOPS_EN bit set for Auto BKOPS support
> mmc: Checking BKOPS status prior to Suspend
>
> drivers/mmc/card/block.c | 3 ++-
> drivers/mmc/core/mmc.c | 36 +++++++++++++++++++++++++++++-------
> include/linux/mmc/card.h | 1 +
> include/linux/mmc/host.h | 2 ++
> include/linux/mmc/mmc.h | 2 ++
> 5 files changed, 36 insertions(+), 8 deletions(-)
>
>--
>1.9.1
>
^ permalink raw reply
* Re: [PATCH -next] mmc: sdhci-of-arasan: Fix non static symbol warning
From: Adrian Hunter @ 2016-09-26 6:45 UTC (permalink / raw)
To: Wei Yongjun, Michal Simek, soren.brinkmann, ulf.hansson
Cc: Wei Yongjun, linux-arm-kernel, linux-mmc
In-Reply-To: <1474818243-19207-1-git-send-email-weiyj.lk@gmail.com>
On 25/09/16 18:44, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> Fixes the following sparse warning:
>
> drivers/mmc/host/sdhci-of-arasan.c:253:6: warning:
> symbol 'sdhci_arasan_reset' was not declared. Should it be static?
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-of-arasan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index da8e40a..e263671 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -250,7 +250,7 @@ static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
> writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
> }
>
> -void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
> +static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
> {
> u8 ctrl;
> struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>
>
>
>
^ permalink raw reply
* Re: [PATCH -next] mmc: sdhci-of-arasan: Fix non static symbol warning
From: Sören Brinkmann @ 2016-09-26 3:46 UTC (permalink / raw)
To: Wei Yongjun
Cc: ulf.hansson, linux-mmc, Michal Simek, adrian.hunter, Wei Yongjun,
linux-arm-kernel
In-Reply-To: <1474818243-19207-1-git-send-email-weiyj.lk@gmail.com>
On Sun, 2016-09-25 at 15:44:03 +0000, Wei Yongjun wrote:
> From: Wei Yongjun <weiyongjun1@huawei.com>
>
> Fixes the following sparse warning:
>
> drivers/mmc/host/sdhci-of-arasan.c:253:6: warning:
> symbol 'sdhci_arasan_reset' was not declared. Should it be static?
>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Sören
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* RE: [v12, 0/8] Fix eSDHC host version register bug
From: Y.B. Lu @ 2016-09-26 3:14 UTC (permalink / raw)
To: linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, Scott Wood,
Arnd Bergmann
Cc: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Mark Rutland,
Rob Herring, Russell King, Jochen Friedrich, Joerg Roedel,
Claudiu Manoil, Bhupesh Sharma
In-Reply-To: <1474441040-11946-1-git-send-email-yangbo.lu-3arQi8VN3Tc@public.gmane.org>
Any comments about this version patchset ?
:)
> -----Original Message-----
> From: Yangbo Lu [mailto:yangbo.lu-3arQi8VN3Tc@public.gmane.org]
> Sent: Wednesday, September 21, 2016 2:57 PM
> To: linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Scott Wood; Arnd
> Bergmann
> Cc: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-
> clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; iommu-cunTk1MwBs/ROKNJybVBZg@public.gmane.org
> foundation.org; netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Mark Rutland; Rob Herring;
> Russell King; Jochen Friedrich; Joerg Roedel; Claudiu Manoil; Bhupesh
> Sharma; Qiang Zhao; Kumar Gala; Santosh Shilimkar; Leo Li; X.B. Xie; M.H.
> Lian; Y.B. Lu
> Subject: [v12, 0/8] Fix eSDHC host version register bug
>
> This patchset is used to fix a host version register bug in the T4240-
> R1.0-R2.0 eSDHC controller. To match the SoC version and revision, 10
> previous version patchsets had tried many methods but all of them were
> rejected by reviewers.
> Such as
> - dts compatible method
> - syscon method
> - ifdef PPC method
> - GUTS driver getting SVR method
> Anrd suggested a soc_device_match method in v10, and this is the only
> available method left now. This v11 patchset introduces the
> soc_device_match interface in soc driver.
>
> The first six patches of Yangbo are to add the GUTS driver. This is used
> to register a soc device which contain soc version and revision
> information.
> The other two patches introduce the soc_device_match method in soc driver
> and apply it on esdhc driver to fix this bug.
>
> Arnd Bergmann (1):
> base: soc: introduce soc_device_match() interface
>
> Yangbo Lu (7):
> dt: bindings: update Freescale DCFG compatible
> ARM64: dts: ls2080a: add device configuration node
> dt: bindings: move guts devicetree doc out of powerpc directory
> powerpc/fsl: move mpc85xx.h to include/linux/fsl
> soc: fsl: add GUTS driver for QorIQ platforms
> MAINTAINERS: add entry for Freescale SoC drivers
> mmc: sdhci-of-esdhc: fix host version for T4240-R1.0-R2.0
>
> Documentation/devicetree/bindings/arm/fsl.txt | 6 +-
> .../bindings/{powerpc => soc}/fsl/guts.txt | 3 +
> MAINTAINERS | 11 +-
> arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 6 +
> arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
> arch/powerpc/sysdev/fsl_pci.c | 2 +-
> drivers/base/Kconfig | 1 +
> drivers/base/soc.c | 66 ++++++
> drivers/clk/clk-qoriq.c | 3 +-
> drivers/i2c/busses/i2c-mpc.c | 2 +-
> drivers/iommu/fsl_pamu.c | 3 +-
> drivers/mmc/host/Kconfig | 1 +
> drivers/mmc/host/sdhci-of-esdhc.c | 20 ++
> drivers/net/ethernet/freescale/gianfar.c | 2 +-
> drivers/soc/Kconfig | 2 +-
> drivers/soc/fsl/Kconfig | 19 ++
> drivers/soc/fsl/Makefile | 1 +
> drivers/soc/fsl/guts.c | 257
> +++++++++++++++++++++
> include/linux/fsl/guts.h | 125 ++++++----
> .../asm/mpc85xx.h => include/linux/fsl/svr.h | 4 +-
> include/linux/sys_soc.h | 3 +
> 21 files changed, 478 insertions(+), 61 deletions(-) rename
> Documentation/devicetree/bindings/{powerpc => soc}/fsl/guts.txt (91%)
> create mode 100644 drivers/soc/fsl/Kconfig create mode 100644
> drivers/soc/fsl/guts.c rename arch/powerpc/include/asm/mpc85xx.h =>
> include/linux/fsl/svr.h (97%)
>
> --
> 2.1.0.27.g96db324
--
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^ permalink raw reply
* [PATCH -next] mmc: sdhci-of-arasan: Fix non static symbol warning
From: Wei Yongjun @ 2016-09-25 15:44 UTC (permalink / raw)
To: Michal Simek, soren.brinkmann, adrian.hunter, ulf.hansson
Cc: Wei Yongjun, linux-arm-kernel, linux-mmc
From: Wei Yongjun <weiyongjun1@huawei.com>
Fixes the following sparse warning:
drivers/mmc/host/sdhci-of-arasan.c:253:6: warning:
symbol 'sdhci_arasan_reset' was not declared. Should it be static?
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/mmc/host/sdhci-of-arasan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index da8e40a..e263671 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -250,7 +250,7 @@ static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
writel(vendor, host->ioaddr + SDHCI_ARASAN_VENDOR_REGISTER);
}
-void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
+static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
{
u8 ctrl;
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
^ permalink raw reply related
* RE RE
From: Mr.Campbell Neiman @ 2016-09-24 6:04 UTC (permalink / raw)
This message is the last notification about U USD14.5 million bearing our
Name as Beneficiary, all effort to reach you have not be successful,
Please if you Receive this message kindly respond back stating your Desire
to make the claim, Reconfirm your full name and age Mr. Mr.Campbell Neiman
^ permalink raw reply
* [RFC 1/2] sdhci: Add device tree property sd-broken-highspeed
From: Zach Brown @ 2016-09-23 20:01 UTC (permalink / raw)
To: ulf.hansson
Cc: adrian.hunter, robh+dt, mark.rutland, linux-mmc, devicetree,
linux-kernel, zach.brown
In-Reply-To: <1474660869-15532-1-git-send-email-zach.brown@ni.com>
Certain board configurations can make highspeed malfunction due to
timing issues. In these cases a way is needed to force the controller
and card into standard speed even if they otherwise appear to be capable
of highspeed.
The sd-broken-highspeed property will let the sdhci driver know that
highspeed will not work.
Signed-off-by: Zach Brown <zach.brown@ni.com>
---
Documentation/devicetree/bindings/mmc/mmc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index 8a37782..59332ea 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -52,6 +52,8 @@ Optional properties:
- no-sdio: controller is limited to send sdio cmd during initialization
- no-sd: controller is limited to send sd cmd during initialization
- no-mmc: controller is limited to send mmc cmd during initialization
+- sd-broken-highspeed: Highspeed is broken, even if the controller and card
+ themselves claim they support highspeed.
*NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
polarity properties, we have to fix the meaning of the "normal" and "inverted"
--
2.7.4
^ permalink raw reply related
* [RFC 2/2] sdhci: Prevent SD from doing highspeed timing when sd-broken-highspeed property is set
From: Zach Brown @ 2016-09-23 20:01 UTC (permalink / raw)
To: ulf.hansson
Cc: adrian.hunter, robh+dt, mark.rutland, linux-mmc, devicetree,
linux-kernel, zach.brown
In-Reply-To: <1474660869-15532-1-git-send-email-zach.brown@ni.com>
From: Chen Yee Chew <chen.yee.chew@ni.com>
When the sd-broken-highspeed property is set the sdhci driver will not
go into highspeed mode even if the controller and card appear to
otherwise support highspeed mode.
This is useful in cases where the controller and card support highspeed,
but the board configuration or some other issue make highspeed
impossible.
Signed-off-by: Chen Yee Chew <chen.yee.chew@ni.com>
Reviewed-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Zach Brown <zach.brown@ni.com>
---
drivers/mmc/host/sdhci-pltfm.c | 3 +++
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 2 ++
3 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c
index ad49bfa..7482706 100644
--- a/drivers/mmc/host/sdhci-pltfm.c
+++ b/drivers/mmc/host/sdhci-pltfm.c
@@ -87,6 +87,9 @@ void sdhci_get_of_property(struct platform_device *pdev)
if (of_get_property(np, "broken-cd", NULL))
host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+ if (of_get_property(np, "sd-broken-highspeed", NULL))
+ host->quirks2 |= SDHCI_QUIRK2_BROKEN_HISPD;
+
if (of_get_property(np, "no-1-8-v", NULL))
host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 4805566..4b0969c 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3274,7 +3274,8 @@ int sdhci_setup_host(struct sdhci_host *host)
if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
mmc->caps &= ~MMC_CAP_CMD23;
- if (host->caps & SDHCI_CAN_DO_HISPD)
+ if ((host->caps & SDHCI_CAN_DO_HISPD) &&
+ !(host->quirks2 & SDHCI_QUIRK2_BROKEN_HISPD))
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c722cd2..3d0fdda 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -424,6 +424,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
/* Broken Clock divider zero in controller */
#define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15)
+/* Highspeed is broken even if it appears otherwise */
+#define SDHCI_QUIRK2_BROKEN_HISPD (1<<16)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
--
2.7.4
^ permalink raw reply related
* [RFC 0/2] Add device tree property and quirk for supporting sdhci
From: Zach Brown @ 2016-09-23 20:01 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A
Cc: adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, zach.brown-acOepvfBmUk
Some board configurations can not support sd highspeed mode due to the distance
between the card slot and the controller. The card and controller report that
they are capable of highspeed however, so we need a mechanism for specifying
that the setup is incapable of supporting highspeed mode.
The first patch adds documentation about a new devicetree property
sd-broken-highspeed.
The second patch keeps the sd controller and card from going into highspeed
mode when the property is set.
Chen Yee Chew (1):
sdhci: Prevent SD from doing high-speed timing when
sd-broken-highspeed property is set
Zach Brown (1):
sdhci: Add device tree property sd-broken-highspeed
Documentation/devicetree/bindings/mmc/mmc.txt | 2 ++
arch/arm/boot/dts/ni-77D5.dts | 1 -
drivers/mmc/host/sdhci-pltfm.c | 3 +++
drivers/mmc/host/sdhci.c | 3 ++-
drivers/mmc/host/sdhci.h | 2 ++
5 files changed, 9 insertions(+), 2 deletions(-)
--
2.7.4
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^ permalink raw reply
* Re: [PATCH v3 2/2] ARM64: dts: meson-gxbb: add MMC support
From: Rob Herring @ 2016-09-23 13:45 UTC (permalink / raw)
To: Kevin Hilman
Cc: Ulf Hansson, linux-mmc, linux-amlogic, linux-arm-kernel,
devicetree, Victor Wan, Jerry Cao, Xing Wu, yonghui.yu
In-Reply-To: <20160914004314.682-3-khilman@baylibre.com>
On Tue, Sep 13, 2016 at 05:43:14PM -0700, Kevin Hilman wrote:
> Add binding and basic support for the SD/eMMC controller on Amlogic
> S905/GXBB devices.
>
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
> .../devicetree/bindings/mmc/amlogic,meson-gxbb.txt | 29 ++++++++
> .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 87 ++++++++++++++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 78 +++++++++++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 37 ++++++++-
> 4 files changed, 230 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt
Some nits below, otherwise:
Acked-by: Rob Herring <robh@kernel.org>
>
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt
> new file mode 100644
> index 000000000000..39cbe528b7de
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gxbb.txt
> @@ -0,0 +1,29 @@
> +Amlogic SD / eMMC controller for S905/GXBB family SoCs
> +
> +The MMC 5.1 compliant host controller on Amlogic provides the
> +interface for SD, eMMC and SDIO devices.
> +
> +This file documents the properties in addition to those available in
> +the MMC core bindings, documented by mmc.txt.
> +
> +Required properties:
> +- compatible : contains "amlogic,meson-gxbb-mmc"
> +- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
> +- clock-names: Should contain the following:
> + "core" - Main peripheral bus clock
> + "clkin0" - Parent clock of internal mux
> + "clkin1" - Other parent clock of internal mux
> + The driver has an interal mux clock which switches between clkin0 and clkin1 depending on the
> + clock rate requested by the MMC core.
> +
> +Example:
> +
> + sd_emmc_a: mmc@70000 {
> + compatible = "amlogic,meson-gxbb-mmc";
> + reg = <0x0 0x70000 0x0 0x2000>;
> + interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "core", "clkin0", "clkin1";
> + pinctrl-0 = <&emmc_pins>;
> + };
> +
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> index 90a84c514d3d..2a9303e7fab8 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> @@ -73,6 +73,56 @@
> default-state = "off";
> };
> };
> +
> + tflash_vdd: regulator-tflash_vdd {
Use '-' not '_' in node names.
> + /*
> + * signal name from schematics: TFLASH_VDD_EN
> + */
> + compatible = "regulator-fixed";
> +
> + regulator-name = "TFLASH_VDD";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&gpio_ao GPIOAO_12 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + tf_io: gpio-regulator-tf_io {
ditto
> + compatible = "regulator-gpio";
> +
> + regulator-name = "TF_IO";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> +
> + /*
> + * signal name from schematics: TF_3V3N_1V8_EN
> + */
> + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>;
> + gpios-states = <0>;
> +
> + states = <3300000 0
> + 1800000 1>;
> + };
> +
> + vcc1v8: regulator-vcc1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC1V8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vcc3v3: regulator-vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VCC3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + emmc_pwrseq: emmc-pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
> + };
> };
>
> &uart_AO {
> @@ -87,3 +137,40 @@
> pinctrl-names = "default";
> };
>
> +/* SD */
> +&sd_emmc_b {
> + status = "okay";
> + pinctrl-0 = <&sdcard_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <4>;
> + cap-sd-highspeed;
> + max-frequency = <100000000>;
> + disable-wp;
> +
> + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> +
> + vmmc-supply = <&tflash_vdd>;
> + vqmmc-supply = <&tf_io>;
> +};
> +
> +/* eMMC */
> +&sd_emmc_c {
> + status = "okay";
> + pinctrl-0 = <&emmc_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <8>;
> + cap-sd-highspeed;
> + max-frequency = <200000000>;
> + non-removable;
> + disable-wp;
> + cap-mmc-highspeed;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> +
> + mmc-pwrseq = <&emmc_pwrseq>;
> + vmmc-supply = <&vcc3v3>;
> + vqmmc-supply = <&vcc1v8>;
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
> index f4f30f674b4c..77c4d5eb48a2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
> @@ -57,6 +57,47 @@
> device_type = "memory";
> reg = <0x0 0x0 0x0 0x40000000>;
> };
> +
> + vddio_card: gpio-regulator {
> + compatible = "regulator-gpio";
> +
> + regulator-name = "VDDIO_CARD";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
> + gpios-states = <1>;
> +
> + /* Based on P200 schematics, signal CARD_1.8V/3.3V_CTR */
> + states = <1800000 0
> + 3300000 1>;
> + };
> +
> + vddio_boot: regulator-vddio_boot {
ditto
> + compatible = "regulator-fixed";
> + regulator-name = "VDDIO_BOOT";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vddao_3v3: regulator-vddao_3v3 {
ditto
> + compatible = "regulator-fixed";
> + regulator-name = "VDDAO_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vcc_3v3: regulator-vcc_3v3 {
ditto
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + emmc_pwrseq: emmc-pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
> + };
> };
>
> /* This UART is brought out to the DB9 connector */
> @@ -72,3 +113,40 @@
> pinctrl-names = "default";
> };
>
> +/* SD card */
> +&sd_emmc_b {
> + status = "okay";
> + pinctrl-0 = <&sdcard_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <4>;
> + cap-sd-highspeed;
> + max-frequency = <100000000>;
> + disable-wp;
> +
> + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> +
> + vmmc-supply = <&vddao_3v3>;
> + vqmmc-supply = <&vddio_card>;
> +};
> +
> +/* eMMC */
> +&sd_emmc_c {
> + status = "okay";
> + pinctrl-0 = <&emmc_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <8>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + max-frequency = <200000000>;
> + non-removable;
> + disable-wp;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> +
> + mmc-pwrseq = <&emmc_pwrseq>;
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&vddio_boot>;
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index e502c24b0ac7..3723007146ac 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -45,6 +45,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/gpio/meson-gxbb-gpio.h>
> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
> +#include <dt-bindings/clock/gxbb-clkc.h>
>
> / {
> compatible = "amlogic,meson-gxbb";
> @@ -246,7 +247,8 @@
> mux {
> groups = "emmc_nand_d07",
> "emmc_cmd",
> - "emmc_clk";
> + "emmc_clk",
> + "emmc_ds";
> function = "emmc";
> };
> };
> @@ -329,6 +331,39 @@
> #address-cells = <2>;
> #size-cells = <2>;
> ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
> +
> + sd_emmc_a: mmc@70000 {
> + compatible = "amlogic,meson-gxbb-mmc";
> + reg = <0x0 0x70000 0x0 0x2000>;
> + interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&clkc CLKID_SD_EMMC_A>,
> + <&xtal>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "core", "clkin0", "clkin1";
> + status = "disabled";
> + };
> +
> + sd_emmc_b: mmc@72000 {
> + compatible = "amlogic,meson-gxbb-mmc";
> + reg = <0x0 0x72000 0x0 0x2000>;
> + interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&clkc CLKID_SD_EMMC_B>,
> + <&xtal>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "core", "clkin0", "clkin1";
> + status = "disabled";
> + };
> +
> + sd_emmc_c: mmc@74000 {
> + compatible = "amlogic,meson-gxbb-mmc";
> + reg = <0x0 0x74000 0x0 0x2000>;
> + interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&clkc CLKID_SD_EMMC_C>,
> + <&xtal>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "core", "clkin0", "clkin1";
> + status = "disabled";
> + };
> };
>
> ethmac: ethernet@c9410000 {
> --
> 2.9.3
>
^ permalink raw reply
* [GIT PULL] MMC fix for v.4.8 rc8
From: Ulf Hansson @ 2016-09-23 10:28 UTC (permalink / raw)
To: Linus Torvalds, linux-kernel@vger.kernel.org, linux-mmc; +Cc: Jaehoon Chung
Hi Linus,
Here's is yet another mmc fix, intended for v4.8 rc8. It's based on v4.8-rc7.
Details are as usual found in the signed tag. Please pull this in!
Kind regards
Ulf Hansson
The following changes since commit 3be7988674ab33565700a37b210f502563d932e6:
Linux 4.8-rc7 (2016-09-18 17:27:41 -0700)
are available in the git repository at:
git://git.linaro.org/people/ulf.hansson/mmc.git tags/mmc-v4.8-rc7
for you to fetch changes up to 005d675aa1909ad70456dec8c5b0ba9b60b52d24:
mmc: dw_mmc: fix the spamming log message (2016-09-22 09:34:13 +0200)
----------------------------------------------------------------
MMC host:
- dw_mmc: fix the spamming log message
----------------------------------------------------------------
Jaehoon Chung (1):
mmc: dw_mmc: fix the spamming log message
drivers/mmc/host/dw_mmc.c | 14 +++++++++-----
drivers/mmc/host/dw_mmc.h | 3 +++
2 files changed, 12 insertions(+), 5 deletions(-)
^ permalink raw reply
* Re: [PATCH v3] mmc: sdhci-msm: Add pm_runtime and system PM support
From: Ulf Hansson @ 2016-09-23 10:07 UTC (permalink / raw)
To: Ritesh Harjani
Cc: Pramod Gurav, Georgi Djakov, Adrian Hunter, linux-mmc,
open list:ARM/QUALCOMM SUPPORT, open list, Stephen Boyd
In-Reply-To: <ffaebf0e-9338-3bda-b45d-16ad76b4f586@codeaurora.org>
[...]
>>>> Is there anything else needed in msm sdhci driver so that the auto
>>>> tuning is taken care of?
>>>
>>>
>>> I am not familiar with any other than sdhci-esdhc-imx which supports
>>> the SDHCI_TUNING_MODE_3. I may be wrong though.
>>>
>>> In the sdhci-esdhc-imx case, enabling of auto tuning seems to be done
>>> in esdhc_post_tuning(), where a vendor specific register
>>> (ESDHC_MIX_CTRL) is being written to. Perhaps something similar in
>>> your case?
>>>
>> Thanks Ulf for the comments. Will check this and see if there is
>> something of this sort we have to do to achieve auto tuning.
>> Adding Ritesh who has been posting some SDHCI MSM patches recently in
>> case he knows about this.
>
>
> Internally, we don't use this Auto re-tuning and rely on explicit re-tune by
> host driver.
>
> Question though -
> 1. why do we need to call sdhci_runtime_resume/suspend from
> sdhci_msm_runtime_suspend/resume?
> From what I see is, sdhci_runtime_susend/resume will do reset and re-program
> of host->pwr and host->clk because of which a retune will be required for
> the next command after runtime resume.
>
> We can *only* disable and enable the clocks in
> sdhci_msm_runtime_suspend/resume?
> Thoughts? With this, I suppose you would not see any issue.
I see.
I assumes that means saving/restoring register context will
automatically handled by some other outer logic, when doing clock
gating/ungating?
In other words, if the controller has valid tuning values, those will
be re-used and restored when clock ungating happens?
>
>
> Though for this issue, since internally also auto retuning is never used, we
> can have this mode disabled. I can once again check with HW team to get more
> details about this mode for MSM controller.
>
>>
>> Regards,
>> Pramod
>>
>
Kind regards
Uffe
^ permalink raw reply
* Re: [RESEDN PATCH v2 3/4] mmc: sdhci: Don't try to switch to unsupported voltage
From: Shawn Lin @ 2016-09-23 8:07 UTC (permalink / raw)
To: Adrian Hunter
Cc: shawn.lin, Ulf Hansson, Jaehoon Chung, linux-mmc, linux-kernel,
linux-rockchip, Ziyuan Xu
In-Reply-To: <785df157-dadc-4dd3-76e9-aea3a0f031a5@intel.com>
在 2016/9/23 15:12, Adrian Hunter 写道:
> On 23/09/16 03:12, Shawn Lin wrote:
>> From: Ziyuan Xu <xzy.xu@rock-chips.com>
>>
>> Sdhci shouldn't switch to the unsupported voltage if claiming
>> that it can not support the requested voltage. Let's fix it.
>>
>> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>> ---
>>
>> Changes in v2: None
>>
>> drivers/mmc/host/sdhci.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>> index 4805566..b1f1edd 100644
>> --- a/drivers/mmc/host/sdhci.c
>> +++ b/drivers/mmc/host/sdhci.c
>> @@ -1845,7 +1845,8 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>>
>> switch (ios->signal_voltage) {
>> case MMC_SIGNAL_VOLTAGE_330:
>> - if (!(host->flags & SDHCI_SIGNALING_330))
>> + if (!(host->flags & SDHCI_SIGNALING_330) ||
>> + !(host->caps & SDHCI_CAN_VDD_330))
>
> You are mixing signal voltage and supply voltage here. Note, I don't
Oh, I see what you mean, driver could still set 3.3 voltage supply
even they don't support 3V3 signal voltage.
> believe all drivers set the capabilities correctly when they are using
> regulators, but in any case this is not the place in the code to make such
> assumptions.
Indeed, there is a risk of breaking some drivers if they don't set the
capabilities correctly.
So, I think we could drop this patch since patch 4 is actually what we
need in order to slove our problem. :)
>
> Better for the driver to remove SDHCI_SIGNALING_330 from flags when it is
> not supported.
>
>> return -EINVAL;
>> /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
>> ctrl &= ~SDHCI_CTRL_VDD_180;
>> @@ -1872,7 +1873,8 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>>
>> return -EAGAIN;
>> case MMC_SIGNAL_VOLTAGE_180:
>> - if (!(host->flags & SDHCI_SIGNALING_180))
>> + if (!(host->flags & SDHCI_SIGNALING_180) ||
>> + !(host->caps & SDHCI_CAN_VDD_180))
>
> You are mixing signal voltage and supply voltage here, and this is not
> correct: not being able to do 1.8V supply does not mean you can't do 1.8V
> signaling. The SDHCI way of determining supported signal voltages is based
> on supported transfer modes.
>
> If the driver can't get the transfer modes correct (e.g. we still don't have
> MMC_CAP2_3_3V_ONLY_DDR or equivalent), remove SDHCI_SIGNALING_180 from the
> flags.
>
>> return -EINVAL;
>> if (!IS_ERR(mmc->supply.vqmmc)) {
>> ret = mmc_regulator_set_vqmmc(mmc, ios);
>>
>
>
>
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* Re: [RESEDN PATCH v2 3/4] mmc: sdhci: Don't try to switch to unsupported voltage
From: Adrian Hunter @ 2016-09-23 7:12 UTC (permalink / raw)
To: Shawn Lin
Cc: Ulf Hansson, Jaehoon Chung, linux-mmc, linux-kernel,
linux-rockchip, Ziyuan Xu
In-Reply-To: <1474589577-11193-3-git-send-email-shawn.lin@rock-chips.com>
On 23/09/16 03:12, Shawn Lin wrote:
> From: Ziyuan Xu <xzy.xu@rock-chips.com>
>
> Sdhci shouldn't switch to the unsupported voltage if claiming
> that it can not support the requested voltage. Let's fix it.
>
> Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> Changes in v2: None
>
> drivers/mmc/host/sdhci.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 4805566..b1f1edd 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1845,7 +1845,8 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>
> switch (ios->signal_voltage) {
> case MMC_SIGNAL_VOLTAGE_330:
> - if (!(host->flags & SDHCI_SIGNALING_330))
> + if (!(host->flags & SDHCI_SIGNALING_330) ||
> + !(host->caps & SDHCI_CAN_VDD_330))
You are mixing signal voltage and supply voltage here. Note, I don't
believe all drivers set the capabilities correctly when they are using
regulators, but in any case this is not the place in the code to make such
assumptions.
Better for the driver to remove SDHCI_SIGNALING_330 from flags when it is
not supported.
> return -EINVAL;
> /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
> ctrl &= ~SDHCI_CTRL_VDD_180;
> @@ -1872,7 +1873,8 @@ static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
>
> return -EAGAIN;
> case MMC_SIGNAL_VOLTAGE_180:
> - if (!(host->flags & SDHCI_SIGNALING_180))
> + if (!(host->flags & SDHCI_SIGNALING_180) ||
> + !(host->caps & SDHCI_CAN_VDD_180))
You are mixing signal voltage and supply voltage here, and this is not
correct: not being able to do 1.8V supply does not mean you can't do 1.8V
signaling. The SDHCI way of determining supported signal voltages is based
on supported transfer modes.
If the driver can't get the transfer modes correct (e.g. we still don't have
MMC_CAP2_3_3V_ONLY_DDR or equivalent), remove SDHCI_SIGNALING_180 from the
flags.
> return -EINVAL;
> if (!IS_ERR(mmc->supply.vqmmc)) {
> ret = mmc_regulator_set_vqmmc(mmc, ios);
>
^ permalink raw reply
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