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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3365e60a67bsm24910871fa.73.2025.08.26.18.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 18:20:22 -0700 (PDT) Date: Wed, 27 Aug 2025 04:20:20 +0300 From: Dmitry Baryshkov To: Wasim Nazir Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Richard Cochran , kernel@oss.qualcomm.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, netdev@vger.kernel.org, Monish Chunara Subject: Re: [PATCH 2/5] arm64: dts: qcom: lemans: Add SDHC controller and SDC pin configuration Message-ID: References: <20250826-lemans-evk-bu-v1-0-08016e0d3ce5@oss.qualcomm.com> <20250826-lemans-evk-bu-v1-2-08016e0d3ce5@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250826-lemans-evk-bu-v1-2-08016e0d3ce5@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfXwWWK6Jogm1SE QXeGxkYMwCOBbxw6JCkB8/jvmxtT4J8O3w5RMFoufTUVdnYOevx1HFwCApSUxrofo5ZcZKYxVId S4dI6zPVjo4GRK9RQI1Sj9yWj5WkJwf+xecFvU4Hxd5aU+6GXCtRiN3DxmCmMjQR/28B8IxKN5J uojkxOaN9ZRXq3IFpXo/GglrjgWH6eLVeJeba8pwO1dfa4v/esJCZcoSh/I2LcQZ7MF05OeOulc i8EQKih9jVV5ZGUcbCX7Ts/h6mUZllPQCY/gCa7Qy80Xd2APkoPGuAaadXtvwSWvy1u7Iar7KDs tlXYIwQR485Xozu/QANcHcAnNocsZw19G2NGxpsr7JWOs1i1DkKvShzGlWvxhUCHWgy4BGDdIky 6NOLvMSd X-Authority-Analysis: v=2.4 cv=Lco86ifi c=1 sm=1 tr=0 ts=68ae5d58 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=xnlQaYUteIq3HUSXtOEA:9 a=CjuIK1q_8ugA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: kQrKGV1_KwsTzUpw6pn4JKchSanFwYIo X-Proofpoint-ORIG-GUID: kQrKGV1_KwsTzUpw6pn4JKchSanFwYIo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 clxscore=1015 malwarescore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 On Tue, Aug 26, 2025 at 11:51:01PM +0530, Wasim Nazir wrote: > From: Monish Chunara > > Introduce the SDHC v5 controller node for the Lemans platform. > This controller supports either eMMC or SD-card, but only one > can be active at a time. SD-card is the preferred configuration > on Lemans targets, so describe this controller. > > Define the SDC interface pins including clk, cmd, and data lines > to enable proper communication with the SDHC controller. > > Signed-off-by: Monish Chunara > Co-developed-by: Wasim Nazir > Signed-off-by: Wasim Nazir > --- > arch/arm64/boot/dts/qcom/lemans.dtsi | 70 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 70 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > index 99a566b42ef2..a5a3cdba47f3 100644 > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > @@ -3834,6 +3834,36 @@ apss_tpdm2_out: endpoint { > }; > }; > > + sdhc: mmc@87c4000 { > + compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x087c4000 0x0 0x1000>; > + > + interrupts = , > + ; > + interrupt-names = "hc_irq", "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>; > + clock-names = "iface", "core"; > + > + interconnects = <&aggre1_noc MASTER_SDC 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDC1 0>; > + interconnect-names = "sdhc-ddr", "cpu-sdhc"; > + > + iommus = <&apps_smmu 0x0 0x0>; > + dma-coherent; > + > + resets = <&gcc GCC_SDCC1_BCR>; > + > + no-sdio; > + no-mmc; > + bus-width = <4>; This is the board configuration, it should be defined in the EVK DTS. > + qcom,dll-config = <0x0007642c>; > + qcom,ddr-config = <0x80040868>; > + > + status = "disabled"; > + }; > + > usb_0_hsphy: phy@88e4000 { > compatible = "qcom,sa8775p-usb-hs-phy", > "qcom,usb-snps-hs-5nm-phy"; > @@ -5643,6 +5673,46 @@ qup_uart21_rx: qup-uart21-rx-pins { > function = "qup3_se0"; > }; > }; > + > + sdc_default: sdc-default-state { > + clk-pins { > + pins = "sdc1_clk"; > + bias-disable; > + drive-strength = <16>; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + }; > + > + sdc_sleep: sdc-sleep-state { > + clk-pins { > + pins = "sdc1_clk"; > + drive-strength = <2>; > + bias-bus-hold; > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + drive-strength = <2>; > + bias-bus-hold; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + drive-strength = <2>; > + bias-bus-hold; > + }; > + }; > }; > > sram: sram@146d8000 { > > -- > 2.51.0 > -- With best wishes Dmitry