From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
Brian Gerst <brgerst@gmail.com>,
Chris Metcalf <cmetcalf@mellanox.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Liang Z Li <liang.z.li@intel.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Huang Rui <ray.huang@amd.com>, Jiri Slaby <jslaby@suse.cz>,
Jonathan Corbet <corbet@lwn.net>,
"Michael S. Tsirkin" <mst@redhat.com>,
Paul Gortmaker <paul.gortmaker@windriver.com>,
Vlastimil Babka <vbabka@suse.cz>, Chen Yucong <slaoub@gmail.com>,
Alexandre Julliard <julliard@winehq.org>, Fenghua Yu <>
Subject: Re: [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions
Date: Wed, 25 Jan 2017 21:54:50 -0800 [thread overview]
Message-ID: <1485410090.41148.50.camel@ranerica-desktop> (raw)
In-Reply-To: <145900b0-b386-e32c-cd79-cf7c47c14616@zytor.com>
On Wed, 2017-01-25 at 12:38 -0800, H. Peter Anvin wrote:
> On 01/25/17 12:23, Ricardo Neri wrote:
> > + case UMIP_SMSW:
> > + dummy_value = CR0_STATE;
>
> Unless the user space process is running in 64-bit mode this value
> should be & 0xffff.
But wouldn't that prevent the bits CR0[63:16] or CR0[31:16] from being
copied when a register operand is used? According to the Intel Software
Development manual, SMSW returns
SMSW r16 operand size 16, store CR0[15:0] in r16
SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64
The number of bytes returned by the emulated results is controlled by
the data_size variable. If it finds that the result will be saved in a
memory location, it will only copy CR0[15:0], which is the expected
behavior of SMSW if the result is to be copied in memory.
> I'm not sure if we should even support fixing up
> UMIP instructions in 64-bit mode.
Probably not. The whole point of the emulation was to support
virtual-8086 mode and 32-bit mode.
>
> Also, please put an explicit /* fall through */ here.
Will do.
>
> > + /*
> > + * These two instructions return a 16-bit value. We return
> > + * all zeros. This is equivalent to a null descriptor for
> > + * str and sldt.
> > + */
> > + case UMIP_SLDT:
> > + case UMIP_STR:
> > + /* if operand is a register, it is zero-extended*/
> > + if (X86_MODRM_MOD(insn->modrm.value) == 3) {
> > + memset(data, 0, insn->opnd_bytes);
> > + *data_size = insn->opnd_bytes;
> > + /* if not, only the two least significant bytes are copied */
> > + } else {
> > + *data_size = 2;
> > + }
> > + memcpy(data, &dummy_value, sizeof(dummy_value));
> > + break;
The code above controls how many bytes are copied as the result of SMSW.
> > + default:
> > + return -EINVAL;
> > + }
> > + return 0;
>
>
> > +bool fixup_umip_exception(struct pt_regs *regs)
> > +{
> > + struct insn insn;
> > + unsigned char buf[MAX_INSN_SIZE];
> > + /* 10 bytes is the maximum size of the result of UMIP instructions */
> > + unsigned char dummy_data[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
> > +#ifdef CONFIG_X86_64
> > + int x86_64 = user_64bit_mode(regs);
> > +#else
> > + int x86_64 = 0;
> > +#endif
>
> Again, could we simply do:
>
> if (user_64bit_mode(regs))
> return false;
>
> or are there known users of these instructions *in 64-bit mode*?
I am not aware of any. In that case, I will make this code return in
this case.
Thanks and BR,
Ricardo
>
> -hpa
>
>
next prev parent reply other threads:[~2017-01-26 5:54 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-25 20:23 [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 01/10] x86/mpx: Do not use SIB index if index points to R/ESP Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 02/10] x86/mpx: Fail decoding when SIB baseR/EBP is and no displacement is used Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel Ricardo Neri
2017-01-26 2:23 ` Masami Hiramatsu
2017-01-25 20:23 ` [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM Ricardo Neri
2017-01-26 2:11 ` Masami Hiramatsu
2017-01-26 6:07 ` Ricardo Neri
2017-01-27 7:53 ` Masami Hiramatsu
2017-02-01 1:01 ` Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings Ricardo Neri
2017-01-25 21:58 ` Andy Lutomirski
2017-01-25 22:04 ` H. Peter Anvin
2017-01-26 5:50 ` Ricardo Neri
2017-01-26 17:05 ` Andy Lutomirski
2017-01-27 3:44 ` Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 06/10] x86/cpufeature: Add User-Mode Instruction Prevention definitions Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions Ricardo Neri
2017-01-25 20:38 ` H. Peter Anvin
2017-01-26 5:54 ` Ricardo Neri [this message]
2017-01-25 20:23 ` [v3 PATCH 08/10] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 09/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 10/10] selftests/x86: Add tests for " Ricardo Neri
2017-01-25 20:34 ` [v3 PATCH 00/10] x86: Enable " H. Peter Anvin
2017-01-26 5:51 ` Ricardo Neri
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