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From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: Ingo Molnar <mingo@redhat.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@suse.de>
Cc: Peter Zijlstra <peterz@infradead.org>,
	Andrew Morton <akpm@linux-foundation.org>,
	Brian Gerst <brgerst@gmail.com>,
	Chris Metcalf <cmetcalf@mellanox.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Liang Z Li <liang.z.li@intel.com>,
	Masami Hiramatsu <mhiramat@kernel.org>,
	Huang Rui <ray.huang@amd.com>, Jiri Slaby <jslaby@suse.cz>,
	Jonathan Corbet <corbet@lwn.net>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Paul Gortmaker <paul.gortmaker@windriver.com>,
	Vlastimil Babka <vbabka@suse.cz>, Chen Yucong <slaoub@gmail.com>,
	Alexandre Julliard <julliard@winehq.org>,
	Stas Sergeev <stsp@list.ru>, Fenghua Yu <fenghua.yu@intel.com>,
	"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
	Shuah Khan <shuah@kernel.org>,
	linux-kernel@vger.kern
Subject: [v5 03/20] x86/mpx: Do not use R/EBP as base in the SIB byte with Mod = 0
Date: Fri,  3 Mar 2017 13:41:15 -0800	[thread overview]
Message-ID: <20170303214132.77244-4-ricardo.neri-calderon@linux.intel.com> (raw)
In-Reply-To: <20170303214132.77244-1-ricardo.neri-calderon@linux.intel.com>

Section 2.2.1.2 of the Intel 64 and IA-32 Architectures Software
Developer's Manual volume 2A states that when a SIB byte is used and the
base of the SIB byte points to R/EBP (i.e., base = 5) and the mod part
of the ModRM byte is zero, the value of such register will not be used
as part of the address computation. To signal this, a -EDOM error is
returned to indicate callers that they should ignore the value.

Also, for this particular case, a displacement of 32-bits should follow
the SIB byte if the mod part of ModRM is equal to zero. The instruction
decoder ensures that this is the case.

Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Adam Buchbinder <adam.buchbinder@gmail.com>
Cc: Colin Ian King <colin.king@canonical.com>
Cc: Lorenzo Stoakes <lstoakes@gmail.com>
Cc: Qiaowei Ren <qiaowei.ren@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Nathan Howard <liverlint@gmail.com>
Cc: Adan Hawthorn <adanhawthorn@gmail.com>
Cc: Joe Perches <joe@perches.com>
Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
Cc: x86@kernel.org
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
 arch/x86/mm/mpx.c | 29 ++++++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/arch/x86/mm/mpx.c b/arch/x86/mm/mpx.c
index d9e92d6..ef7eb67 100644
--- a/arch/x86/mm/mpx.c
+++ b/arch/x86/mm/mpx.c
@@ -121,6 +121,17 @@ static int get_reg_offset(struct insn *insn, struct pt_regs *regs,
 
 	case REG_TYPE_BASE:
 		regno = X86_SIB_BASE(insn->sib.value);
+		/*
+		 * If mod is 0 and register R/EBP (regno=5) is indicated in the
+		 * base part of the SIB byte, the value of such register should
+		 * not be used in the address computation. Also, a 32-bit
+		 * displacement is expected in this case; the instruction
+		 * decoder takes care of it. This is true for both R13 and
+		 * R/EBP as REX.B will not be decoded.
+		 */
+		if (regno == 5 && X86_MODRM_MOD(insn->modrm.value) == 0)
+			return -EDOM;
+
 		if (X86_REX_B(insn->rex_prefix.value))
 			regno += 8;
 		break;
@@ -161,16 +172,21 @@ static void __user *mpx_get_addr_ref(struct insn *insn, struct pt_regs *regs)
 		eff_addr = regs_get_register(regs, addr_offset);
 	} else {
 		if (insn->sib.nbytes) {
+			/*
+			 * Negative values in the base and index offset means
+			 * an error when decoding the SIB byte. Except -EDOM,
+			 * which means that the registers should not be used
+			 * in the address computation.
+			 */
 			base_offset = get_reg_offset(insn, regs, REG_TYPE_BASE);
-			if (base_offset < 0)
+			if (unlikely(base_offset == -EDOM))
+				base = 0;
+			else if (unlikely(base_offset < 0))
 				goto out_err;
+			else
+				base = regs_get_register(regs, base_offset);
 
 			indx_offset = get_reg_offset(insn, regs, REG_TYPE_INDEX);
-			/*
-			 * A negative offset generally means a error, except
-			 * -EDOM, which means that the contents of the register
-			 * should not be used as index.
-			 */
 			if (unlikely(indx_offset == -EDOM))
 				indx = 0;
 			else if (unlikely(indx_offset < 0))
@@ -178,7 +194,6 @@ static void __user *mpx_get_addr_ref(struct insn *insn, struct pt_regs *regs)
 			else
 				indx = regs_get_register(regs, indx_offset);
 
-			base = regs_get_register(regs, base_offset);
 			eff_addr = base + indx * (1 << X86_SIB_SCALE(sib));
 		} else {
 			addr_offset = get_reg_offset(insn, regs, REG_TYPE_RM);
-- 
2.9.3


  parent reply	other threads:[~2017-03-03 21:41 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-03 21:41 [v5 00/20] x86: Enable User-Mode Instruction Prevention Ricardo Neri
2017-03-03 21:41 ` [v5 01/20] x86/mpx: Use signed variables to compute effective addresses Ricardo Neri
2017-03-03 21:41 ` [v5 02/20] x86/mpx: Do not use SIB index if index points to R/ESP Ricardo Neri
2017-03-03 21:41 ` Ricardo Neri [this message]
2017-03-03 21:41 ` [v5 04/20] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel Ricardo Neri
2017-03-03 21:41 ` [v5 05/20] x86/insn-eval: Add utility functions to get register offsets Ricardo Neri
2017-03-03 21:41 ` [v5 06/20] x86/insn-eval: Add utility functions to get segment selector Ricardo Neri
2017-03-03 21:41 ` [v5 07/20] x86/insn-eval: Add utility function to get segment descriptor Ricardo Neri
2017-03-03 21:41 ` [v5 08/20] x86/insn-eval: Add utility function to get segment descriptor base address Ricardo Neri
2017-03-03 21:41 ` [v5 09/20] x86/insn-eval: Add functions to get default operand and address sizes Ricardo Neri
2017-03-03 21:41 ` [v5 10/20] x86/insn-eval: Do not use R/EBP as base if mod in ModRM is zero Ricardo Neri
2017-03-03 21:41 ` [v5 11/20] insn/eval: Incorporate segment base in address computation Ricardo Neri
2017-03-03 21:41 ` [v5 12/20] x86/insn: Support both signed 32-bit and 64-bit effective addresses Ricardo Neri
2017-03-03 21:41 ` [v5 13/20] x86/insn-eval: Add support to resolve 16-bit addressing encodings Ricardo Neri
2017-03-03 21:41 ` [v5 14/20] x86/insn-eval: Add wrapper function for 16-bit and 32-bit address encodings Ricardo Neri
2017-03-03 21:41 ` [v5 15/20] x86/cpufeature: Add User-Mode Instruction Prevention definitions Ricardo Neri
2017-03-03 21:41 ` [v5 16/20] x86: Add emulation code for UMIP instructions Ricardo Neri
2017-03-03 21:41 ` [v5 17/20] x86/umip: Force a page fault when unable to copy emulated result to user Ricardo Neri
2017-03-05 16:18   ` Andy Lutomirski
2017-03-07  0:26     ` Ricardo Neri
2017-03-03 21:41 ` [v5 18/20] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri
2017-03-03 21:41 ` [v5 19/20] x86: Enable User-Mode Instruction Prevention Ricardo Neri
2017-03-03 21:41 ` [v5 20/20] selftests/x86: Add tests for " Ricardo Neri

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