From: "H. Peter Anvin" <hpa@zytor.com>
To: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andy Lutomirski <luto@kernel.org>, Borislav Petkov <bp@suse.de>
Cc: Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
Brian Gerst <brgerst@gmail.com>,
Chris Metcalf <cmetcalf@mellanox.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Liang Z Li <liang.z.li@intel.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Huang Rui <ray.huang@amd.com>, Jiri Slaby <jslaby@suse.cz>,
Jonathan Corbet <corbet@lwn.net>,
"Michael S. Tsirkin" <mst@redhat.com>,
Paul Gortmaker <paul.gortmaker@windriver.com>,
Vlastimil Babka <vbabka@suse.cz>, Chen Yucong <slaoub@gmail.com>,
Alexandre Julliard <julliard@winehq.org>,
Fenghua Yu <fenghua.yu@intel.com>, Stas Sergeev <stsp@list.ru>,
"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
Shuah Khan <shuah@kernel.org>,
linux-kernel@vger.kern
Subject: Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention
Date: Wed, 25 Jan 2017 12:34:07 -0800 [thread overview]
Message-ID: <98393c2c-4d1e-d8bb-b693-ec26ea919a4c@zytor.com> (raw)
In-Reply-To: <20170125202353.101059-1-ricardo.neri-calderon@linux.intel.com>
On 01/25/17 12:23, Ricardo Neri wrote:
> * SMSW returns the value with which the CR0 register is programmed in
> head_32/64.S at boot time. This is, the following bits are enabed:
> CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
> Extension Type, which will always be 1 in recent processors with UMIP;
> CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment
> Mask. Additionally, in x86_64, CR0.31 for Paging is set.
SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd.
-hpa
next prev parent reply other threads:[~2017-01-25 20:34 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-25 20:23 [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 01/10] x86/mpx: Do not use SIB index if index points to R/ESP Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 02/10] x86/mpx: Fail decoding when SIB baseR/EBP is and no displacement is used Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 03/10] x86/mpx, x86/insn: Relocate insn util functions to a new insn-kernel Ricardo Neri
2017-01-26 2:23 ` Masami Hiramatsu
2017-01-25 20:23 ` [v3 PATCH 04/10] x86/insn-kernel: Add a function to obtain register offset in ModRM Ricardo Neri
2017-01-26 2:11 ` Masami Hiramatsu
2017-01-26 6:07 ` Ricardo Neri
2017-01-27 7:53 ` Masami Hiramatsu
2017-02-01 1:01 ` Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 05/10] x86/insn-kernel: Add support to resolve 16-bit addressing encodings Ricardo Neri
2017-01-25 21:58 ` Andy Lutomirski
2017-01-25 22:04 ` H. Peter Anvin
2017-01-26 5:50 ` Ricardo Neri
2017-01-26 17:05 ` Andy Lutomirski
2017-01-27 3:44 ` Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 06/10] x86/cpufeature: Add User-Mode Instruction Prevention definitions Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 07/10] x86: Add emulation code for UMIP instructions Ricardo Neri
2017-01-25 20:38 ` H. Peter Anvin
2017-01-26 5:54 ` Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 08/10] x86/traps: Fixup general protection faults caused by UMIP Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 09/10] x86: Enable User-Mode Instruction Prevention Ricardo Neri
2017-01-25 20:23 ` [v3 PATCH 10/10] selftests/x86: Add tests for " Ricardo Neri
2017-01-25 20:34 ` H. Peter Anvin [this message]
2017-01-26 5:51 ` [v3 PATCH 00/10] x86: Enable " Ricardo Neri
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