RE: nandtest error

Tee Zhen Cong
2015-05-06T06:02:37Z

Hi Jeff, Han Xu,
After changing the ECC strength for the kernel, I had manage to erase, read
and write the NAND flash successfully in kernel. However, the intention is
for the mx6SOLO to boot from NAND.
Now I am facing problem where the uboot is not able to boot to kernel
correctly. It seems like in the u-boot 2009.08, there are some places where
it only set the address space to 32 bits (4GB NAND is 33 bit address space).
For example, in the cmd_nand.c, there is a FIXME stating that currently the
uboot cmd_nand does not support 64bit address space!
Another example is at the gpmi_nfc_mil.c, where there is a comment stating
"limit to 2G size due to Kernel. Larger 4G space support, need fix it later"
in function gpmi_nfc_scan_bbt.
There are many other places where the variables are set to 32 bits only.
I had applied one of the patch as below:
https://github.com/linksprite/u-boot-acadia1.0-beta/blob/master/u-boot-acadi
a1.0-beta/patches/0195-NAND-Update-to-support-64-bit-device-size.patch
however, this patch only helps the uboot to recognize the NAND flash. It
does not fix the 32 bit addressing issue.
May I know is there any patch on u-boot 2009.08 that is able to solve this
issue?

Thank you.

Regards,
zc

-----Original Message-----
From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
Jeff Lauruhn (jlauruhn)
Sent: Thursday, 30 April, 2015 11:57 PM
To: Tee Zhen Cong; 'Han Xu'
Cc: linux-mtd@lists.infradead.org
Subject: RE: nandtest error

Awesome! Great news.

Jeff Lauruhn
NAND Application Engineer
Embedded Business Unit
Micron Technology, Inc

-----Original Message-----
From: Tee Zhen Cong [mailto:zc.tee@teraoka.com.sg]
Sent: Thursday, April 30, 2015 1:05 AM
To: Jeff Lauruhn (jlauruhn); 'Han Xu'
Cc: linux-mtd@lists.infradead.org
Subject: RE: nandtest error

Hi Jeff,
It's related to the ECC strength issue limitation as mentioned by Han Xu. I
changed some parameter so that the ECC strength calculated is less than 40,
and the problem is solved.

Thanks Han Xu for the hint, and thanks Jeff for the explanation!

Regards,
zc

-----Original Message-----
From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
Jeff Lauruhn (jlauruhn)
Sent: Thursday, 30 April, 2015 10:06 AM
To: Tee Zhen Cong; 'Han Xu'
Cc: linux-mtd@lists.infradead.org
Subject: RE: nandtest error

Hello zc;
The MT29F16G08CBACA is a 70 series part (25nm), 24 bit/1080 bytes of ECC vs
MT29F32G08CBADA 80 series (20nm) 40 bits/1117 bytes of ECC, these are very
different parts. ECC of 40 bits/1117 bytes will correct 320 bits per page
and 81920 bits per block so if I read this correctly 31 of 81920 bits have
flipped in this case. My point here is that with ECC correction this device
will be good past the 3000 P/E cycles guaranteed, but if you look at any raw
NAND without ECC correction you will very likely see some flipped bits.
This is normal NAND behavior, especially on smaller nodes.

Jeff Lauruhn
NAND Application Engineer
Embedded Business Unit
Micron Technology, Inc

-----Original Message-----
From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
Tee Zhen Cong
Sent: Wednesday, April 29, 2015 6:29 PM
To: Jeff Lauruhn (jlauruhn); 'Han Xu'
Cc: linux-mtd@lists.infradead.org
Subject: RE: nandtest error

Hi Jeff,
The flipped bits is found in the first 2Mbytes (1st block) of the NAND. It
stops at the first block where errors are detected. I am not so sure what is
happening in the nandtest application. It seems like a standard linux test
tool for nand where many ppl use. So I use it for my test as well.
As far as I see, it erase, write then read back the NAND block by block, and
see if the read back bytes are the same with the written bytes.
In my opinion, the flipped bits is not normal. I got another board with a
useable 16GBit NAND (MT29F16G08CBACA). Using the nandtest application, it
returns successful without any flipped bit. Same kernel, same software. Only
different NAND.

Regards,
zc

-----Original Message-----
From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
Jeff Lauruhn (jlauruhn)
Sent: Thursday, 30 April, 2015 5:12 AM
To: Han Xu; Tee Zhen Cong
Cc: linux-mtd@lists.infradead.org
Subject: RE: nandtest error

When you read the data back are you reading the raw data? Some amount of
bit flipping is normal NAND Flash behavior. ECC correction is required on
all contemporary NAND to some degree to correct bit flips. This Micron
device is designed to return a "FAIL" status only when the number of bad
bits in any page exceeds 40bits/1117 bytes.

I need to understand what nandtest is actually doing. If I read this right,
if found 32 flipped bits in a 32 gigabit device. That's actually very good.

Jeff Lauruhn
NAND Application Engineer
Embedded Business Unit
Micron Technology, Inc

-----Original Message-----
From: linux-mtd [mailto:linux-mtd-bounces@lists.infradead.org] On Behalf Of
Han Xu