DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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For some reason I am confused: I get the feeling that what I'm trying to
understand is obvious - I just can't see the forest for the trees.  Will
someone help me understand?

cfi_cmdset_0002.c has several functions that use dq5 and dq6 for
monitoring the status of erase and write operations:

dq6 =3D CMD(1<<6);
dq5 =3D CMD(1<<5);

Apparently, from the code dq6 toggles during erase/read operations and
dq5 is low until the erase/read operation times out and then goes high
(somewhat like a watchdog bit).

My understanding,@least for the SST 49LF040 and PMC Pm49L004 is that
dq6 toggles during erase/write and dq7 is inverted until the erase/write
operation completes.  This causes me to expect to see the following code
rather than what is written above (not to mention that most everything
in do_write_one_word() should be adapted for dq7 invert):

dq7 =3D CMD(1<<7); /* invert */
dq6 =3D CMD(1<<6); /* toggle */

The differences give me the feeling that there really are two different
classes of cfi_cmdset_0002 - those devices that have a dq5 watchdog and
those devices that don't have the watchdog, but have a bit inverter on
dq7.

Am I not understanding what happens on bits 0-5 during an erase/write
operation?  The PMC and SST chips don't mention a thing about dq5
behavior.  If they don't have the dq5 watchdog timer then they will
behave in an undefined way (depending on the state of bit 5 in the
written word) with the current dq5 checking.  This explains the many
warnings I see with the SST and PMC chips in do_write_oneword(),

"Warning: DQ5 raised while program operation was in progress, however
operation completed OK"

Around here we refer to this as the "Dairy Queen 5" warning.

Obviosly, during an erase that completes prior to dq5 being read-back,
dq5 will be high and the current algorithm is erroneously correct.  This
can explain why I have not seen the same message in do_erase_oneblock().

Furthermore, the SST documentation on page 10 refers to "spurios
rejection" of good writes - differentiating between a write that
succeeds that appears to fail and a write that fails.  It says that a
write that appears to fail needs to be read back two more times
successfully to filter out spurious rejection.

Comments?  What should change to improve the operation completion
check?  Should cfi_cmdset_0002 be adapted to handle multiple types of
polling or should another command set be written?

--=20
Thayne Harbaugh
Linux Networx

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[John Burch]

> -----Original Message-----
> From: linux-mtd-admin at lists.infradead.org=20
> [mailto:linux-mtd-admin at lists.infradead.org] On Behalf Of=20
> Thayne Harbaugh
> Sent: Tuesday, March 11, 2003 7:25 PM
> To: linux-mtd at lists.infradead.org
> Subject: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)
>=20
>=20
> For some reason I am confused: I get the feeling that what=20
> I'm trying to understand is obvious - I just can't see the=20
> forest for the trees.  Will someone help me understand?
>=20
> cfi_cmdset_0002.c has several functions that use dq5 and dq6=20
> for monitoring the status of erase and write operations:
>=20
> dq6 =3D CMD(1<<6);
> dq5 =3D CMD(1<<5);
>=20
> Apparently, from the code dq6 toggles during erase/read=20
> operations and dq5 is low until the erase/read operation=20
> times out and then goes high (somewhat like a watchdog bit).
>=20
> My understanding, at least for the SST 49LF040 and PMC=20
> Pm49L004 is that dq6 toggles during erase/write and dq7 is=20
> inverted until the erase/write operation completes.  This=20
> causes me to expect to see the following code rather than=20
> what is written above (not to mention that most everything in=20
> do_write_one_word() should be adapted for dq7 invert):
>=20
> dq7 =3D CMD(1<<7); /* invert */
> dq6 =3D CMD(1<<6); /* toggle */
>=20
> The differences give me the feeling that there really are two=20
> different classes of cfi_cmdset_0002 - those devices that=20
> have a dq5 watchdog and those devices that don't have the=20
> watchdog, but have a bit inverter on dq7.
>=20
> Am I not understanding what happens on bits 0-5 during an=20
> erase/write operation?  The PMC and SST chips don't mention a=20
> thing about dq5 behavior.  If they don't have the dq5=20
> watchdog timer then they will behave in an undefined way=20
> (depending on the state of bit 5 in the written word) with=20
> the current dq5 checking.  This explains the many warnings I=20
> see with the SST and PMC chips in do_write_oneword(),
>=20
> "Warning: DQ5 raised while program operation was in progress,=20
> however operation completed OK"
>=20
> Around here we refer to this as the "Dairy Queen 5" warning.
>=20
> Obviosly, during an erase that completes prior to dq5 being=20
> read-back, dq5 will be high and the current algorithm is=20
> erroneously correct.  This can explain why I have not seen=20
> the same message in do_erase_oneblock().
>=20
> Furthermore, the SST documentation on page 10 refers to=20
> "spurios rejection" of good writes - differentiating between=20
> a write that succeeds that appears to fail and a write that=20
> fails.  It says that a write that appears to fail needs to be=20
> read back two more times successfully to filter out spurious=20
> rejection.
>=20
> Comments?  What should change to improve the operation=20
> completion check?  Should cfi_cmdset_0002 be adapted to=20
> handle multiple types of polling or should another command=20
> set be written?

The attached app note from AMD explains things in detail relative
to AMD devices.  I'm not sure how it applies to PMC and SST
devices or not.  It seems as though DQ7 polling or DQ6 polling,
by themselves, give a simple pass/fail/busy result; while DQ7 or DQ6
polling in combination with DQ5 and DQ2 polling give pass/fail/
erase suspended/timeout/busy result.

John

>=20
> --=20
> Thayne Harbaugh
> Linux Networx
>=20

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Steve Wahl]

Thayne, 

I have a patch that I was given permission to check in, but never got
around to it, that covers a similar "DQ5 raised" problem.

I would wager you are running into the same problem I did, and that
your chips compatibly support DQ5, if not as a watchdog, at least by
holding it low while programming.

Can you look at my previous posts on this, try my patch (if you don't
have interleaved chips -- contact me if you do), and see if it works
for you?

http://lists.infradead.org/pipermail/linux-mtd/2003-January/006780.html

--> Steve


On Tue, Mar 11, 2003 at 05:25:15PM -0700, Thayne Harbaugh wrote:
> For some reason I am confused: I get the feeling that what I'm trying to
> understand is obvious - I just can't see the forest for the trees.  Will
> someone help me understand?
> 
> cfi_cmdset_0002.c has several functions that use dq5 and dq6 for
> monitoring the status of erase and write operations:
> 
> dq6 = CMD(1<<6);
> dq5 = CMD(1<<5);
> 
> Apparently, from the code dq6 toggles during erase/read operations and
> dq5 is low until the erase/read operation times out and then goes high
> (somewhat like a watchdog bit).
> 
> My understanding, at least for the SST 49LF040 and PMC Pm49L004 is that
> dq6 toggles during erase/write and dq7 is inverted until the erase/write
> operation completes.  This causes me to expect to see the following code
> rather than what is written above (not to mention that most everything
> in do_write_one_word() should be adapted for dq7 invert):
> 
> dq7 = CMD(1<<7); /* invert */
> dq6 = CMD(1<<6); /* toggle */
> 
> The differences give me the feeling that there really are two different
> classes of cfi_cmdset_0002 - those devices that have a dq5 watchdog and
> those devices that don't have the watchdog, but have a bit inverter on
> dq7.
> 
> Am I not understanding what happens on bits 0-5 during an erase/write
> operation?  The PMC and SST chips don't mention a thing about dq5
> behavior.  If they don't have the dq5 watchdog timer then they will
> behave in an undefined way (depending on the state of bit 5 in the
> written word) with the current dq5 checking.  This explains the many
> warnings I see with the SST and PMC chips in do_write_oneword(),
> 
> "Warning: DQ5 raised while program operation was in progress, however
> operation completed OK"
> 
> Around here we refer to this as the "Dairy Queen 5" warning.
> 
> Obviosly, during an erase that completes prior to dq5 being read-back,
> dq5 will be high and the current algorithm is erroneously correct.  This
> can explain why I have not seen the same message in do_erase_oneblock().
> 
> Furthermore, the SST documentation on page 10 refers to "spurios
> rejection" of good writes - differentiating between a write that
> succeeds that appears to fail and a write that fails.  It says that a
> write that appears to fail needs to be read back two more times
> successfully to filter out spurious rejection.
> 
> Comments?  What should change to improve the operation completion
> check?  Should cfi_cmdset_0002 be adapted to handle multiple types of
> polling or should another command set be written?
> 
> -- 
> Thayne Harbaugh
> Linux Networx

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Wed, 2003-03-12 at 08:44, John Burch wrote:
> > -----Original Message-----
> > From: linux-mtd-admin at lists.infradead.org=20
> > [mailto:linux-mtd-admin at lists.infradead.org] On Behalf Of=20
> > Thayne Harbaugh
> > Sent: Tuesday, March 11, 2003 7:25 PM
> > To: linux-mtd at lists.infradead.org
> > Subject: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)
> >=20
> >=20

<snip>

>=20
> The attached app note

Attachment?

> from AMD explains things in detail relative
> to AMD devices.

<snip>

>=20
> John
>=20
> >=20
> > --=20
> > Thayne Harbaugh
> > Linux Networx
> >=20
>=20
>=20
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--=20
Thayne Harbaugh
Linux Networx

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[John Burch]

This is a multi-part message in MIME format.

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AMD's own method from code they provide is shown below...

By the way, AMD specifically mentions having to check DQ6/7 again
after DQ5=3D1 because of the possibility that DQ5=3D1 simultaneous with
toggling stopping.  The app note I referred to before (attached this
time)
describes this in some detail.  The status register (including DQ5)
won't reflect actual data until a reset command is issued, so I think
the concern about DQ5=3D1 because erased data (0xff) is read instead
of status is not valid.

John

>From AMD's cfiflash.c:

/*********************************************************************/
/* Flash_status utilizes the DQ6, DQ5, and DQ3 polling algorithms    */
/* described in the flash data book.  It can quickly ascertain the   */
/* operational status of the flash device, and return an             */
/* appropriate status code (defined in flash.h)                      */
/*********************************************************************/
=20
int flash_status(word far *fp)
{
	 unsigned char d, t;
	 int retry =3D 1;

again:

	 d =3D *fp;        /* read data */
	 t =3D d ^ *fp;    /* read it again and see what toggled */

	 if (t =3D=3D 0) {           /* no toggles, nothing's happening */
		return STATUS_READY;
	 }
	 else if (t =3D=3D 0x04) { /* erase-suspend */
		if (retry--) goto again;    /* may have been write
completion */
		return STATUS_ERSUSP;
	 }
	 else if (t & 0x40) {
		if (d & 0x20) {     /* timeout */
		  return STATUS_TIMEOUT;
		}
		else {
		  return STATUS_BUSY;
		}
	 }

	 if (retry--) goto again;    /* may have been write completion
*/

	 return STATUS_ERROR;
}



> -----Original Message-----
> From: linux-mtd-admin at lists.infradead.org=20
> [mailto:linux-mtd-admin at lists.infradead.org] On Behalf Of Steve Wahl
> Sent: Wednesday, March 12, 2003 11:28 AM
> To: Thayne Harbaugh
> Cc: linux-mtd at lists.infradead.org
> Subject: Re: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy=20
> Queen 5 warning)
>=20
>=20
> Thayne,=20
>=20
> I have a patch that I was given permission to check in, but=20
> never got around to it, that covers a similar "DQ5 raised" problem.
>=20
> I would wager you are running into the same problem I did,=20
> and that your chips compatibly support DQ5, if not as a=20
> watchdog, at least by holding it low while programming.
>=20
> Can you look at my previous posts on this, try my patch (if=20
> you don't have interleaved chips -- contact me if you do),=20
> and see if it works for you?
>=20
> http://lists.infradead.org/pipermail/linux-mtd/2003-January/00
> 6780.html
>=20
> --> Steve
>=20
>=20
> On Tue, Mar 11, 2003 at 05:25:15PM -0700, Thayne Harbaugh wrote:
> > For some reason I am confused: I get the feeling that what=20
> I'm trying=20
> > to understand is obvious - I just can't see the forest for=20
> the trees. =20
> > Will someone help me understand?
> >=20
> > cfi_cmdset_0002.c has several functions that use dq5 and dq6 for=20
> > monitoring the status of erase and write operations:
> >=20
> > dq6 =3D CMD(1<<6);
> > dq5 =3D CMD(1<<5);
> >=20
> > Apparently, from the code dq6 toggles during erase/read=20
> operations and=20
> > dq5 is low until the erase/read operation times out and=20
> then goes high=20
> > (somewhat like a watchdog bit).
> >=20
> > My understanding, at least for the SST 49LF040 and PMC Pm49L004 is=20
> > that dq6 toggles during erase/write and dq7 is inverted until the=20
> > erase/write operation completes.  This causes me to expect=20
> to see the=20
> > following code rather than what is written above (not to=20
> mention that=20
> > most everything in do_write_one_word() should be adapted for dq7=20
> > invert):
> >=20
> > dq7 =3D CMD(1<<7); /* invert */
> > dq6 =3D CMD(1<<6); /* toggle */
> >=20
> > The differences give me the feeling that there really are two=20
> > different classes of cfi_cmdset_0002 - those devices that=20
> have a dq5=20
> > watchdog and those devices that don't have the watchdog, but have a=20
> > bit inverter on dq7.
> >=20
> > Am I not understanding what happens on bits 0-5 during an=20
> erase/write=20
> > operation?  The PMC and SST chips don't mention a thing about dq5=20
> > behavior.  If they don't have the dq5 watchdog timer then they will=20
> > behave in an undefined way (depending on the state of bit 5 in the=20
> > written word) with the current dq5 checking.  This explains=20
> the many=20
> > warnings I see with the SST and PMC chips in do_write_oneword(),
> >=20
> > "Warning: DQ5 raised while program operation was in=20
> progress, however=20
> > operation completed OK"
> >=20
> > Around here we refer to this as the "Dairy Queen 5" warning.
> >=20
> > Obviosly, during an erase that completes prior to dq5 being=20
> read-back,=20
> > dq5 will be high and the current algorithm is erroneously correct. =20
> > This can explain why I have not seen the same message in=20
> > do_erase_oneblock().
> >=20
> > Furthermore, the SST documentation on page 10 refers to "spurios=20
> > rejection" of good writes - differentiating between a write that=20
> > succeeds that appears to fail and a write that fails.  It=20
> says that a=20
> > write that appears to fail needs to be read back two more times=20
> > successfully to filter out spurious rejection.
> >=20
> > Comments?  What should change to improve the operation completion=20
> > check?  Should cfi_cmdset_0002 be adapted to handle=20
> multiple types of=20
> > polling or should another command set be written?
> >=20
> > --
> > Thayne Harbaugh
> > Linux Networx
>=20
>=20
>=20
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>=20

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------=_NextPart_000_0028_01C2E890.9DBAE0C0--

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Steve Wahl]

On Wed, Mar 12, 2003 at 12:12:12PM -0500, John Burch wrote:
> AMD's own method from code they provide is shown below...
> 
> By the way, AMD specifically mentions having to check DQ6/7 again
> after DQ5=1 because of the possibility that DQ5=1 simultaneous with
> toggling stopping.  The app note I referred to before (attached this
> time) describes this in some detail.  

I agree with this.

> The status register (including DQ5) won't reflect actual data until
> a reset command is issued,

This I think is a misunderstanding or misstatement on your part.  The
reads WILL return to actual data without a reset upon successful
completion of the operation.  Only on a failure does software need to
issue the reset to return to reading data!

The app note you attached agrees with me on this.

> so I think the concern about DQ5=1 because erased data (0xff) is
> read instead of status is not valid.

I disagree.  This concern is indeed valid, and is the primary reason
you must check for toggling AFTER noticing DQ5=1 in the first place.

Note that cfiflash below does not handle interleave nor bit
endianness, so you can't adopt it directly.

--> Steve

> John
> 
> >From AMD's cfiflash.c:
> 
> /*********************************************************************/
> /* Flash_status utilizes the DQ6, DQ5, and DQ3 polling algorithms    */
> /* described in the flash data book.  It can quickly ascertain the   */
> /* operational status of the flash device, and return an             */
> /* appropriate status code (defined in flash.h)                      */
> /*********************************************************************/
>  
> int flash_status(word far *fp)
> {
> 	 unsigned char d, t;
> 	 int retry = 1;
> 
> again:
> 
> 	 d = *fp;        /* read data */
> 	 t = d ^ *fp;    /* read it again and see what toggled */
> 
> 	 if (t == 0) {           /* no toggles, nothing's happening */
> 		return STATUS_READY;
> 	 }
> 	 else if (t == 0x04) { /* erase-suspend */
> 		if (retry--) goto again;    /* may have been write
> completion */
> 		return STATUS_ERSUSP;
> 	 }
> 	 else if (t & 0x40) {
> 		if (d & 0x20) {     /* timeout */
> 		  return STATUS_TIMEOUT;
> 		}
> 		else {
> 		  return STATUS_BUSY;
> 		}
> 	 }
> 
> 	 if (retry--) goto again;    /* may have been write completion
> */
> 
> 	 return STATUS_ERROR;
> }
> 
> 
> 
> > -----Original Message-----
> > From: linux-mtd-admin at lists.infradead.org 
> > [mailto:linux-mtd-admin at lists.infradead.org] On Behalf Of Steve Wahl
> > Sent: Wednesday, March 12, 2003 11:28 AM
> > To: Thayne Harbaugh
> > Cc: linux-mtd at lists.infradead.org
> > Subject: Re: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy 
> > Queen 5 warning)
> > 
> > 
> > Thayne, 
> > 
> > I have a patch that I was given permission to check in, but 
> > never got around to it, that covers a similar "DQ5 raised" problem.
> > 
> > I would wager you are running into the same problem I did, 
> > and that your chips compatibly support DQ5, if not as a 
> > watchdog, at least by holding it low while programming.
> > 
> > Can you look at my previous posts on this, try my patch (if 
> > you don't have interleaved chips -- contact me if you do), 
> > and see if it works for you?
> > 
> > http://lists.infradead.org/pipermail/linux-mtd/2003-January/00
> > 6780.html
> > 
> > --> Steve
> > 
> > 
> > On Tue, Mar 11, 2003 at 05:25:15PM -0700, Thayne Harbaugh wrote:
> > > For some reason I am confused: I get the feeling that what 
> > I'm trying 
> > > to understand is obvious - I just can't see the forest for 
> > the trees.  
> > > Will someone help me understand?
> > > 
> > > cfi_cmdset_0002.c has several functions that use dq5 and dq6 for 
> > > monitoring the status of erase and write operations:
> > > 
> > > dq6 = CMD(1<<6);
> > > dq5 = CMD(1<<5);
> > > 
> > > Apparently, from the code dq6 toggles during erase/read 
> > operations and 
> > > dq5 is low until the erase/read operation times out and 
> > then goes high 
> > > (somewhat like a watchdog bit).
> > > 
> > > My understanding, at least for the SST 49LF040 and PMC Pm49L004 is 
> > > that dq6 toggles during erase/write and dq7 is inverted until the 
> > > erase/write operation completes.  This causes me to expect 
> > to see the 
> > > following code rather than what is written above (not to 
> > mention that 
> > > most everything in do_write_one_word() should be adapted for dq7 
> > > invert):
> > > 
> > > dq7 = CMD(1<<7); /* invert */
> > > dq6 = CMD(1<<6); /* toggle */
> > > 
> > > The differences give me the feeling that there really are two 
> > > different classes of cfi_cmdset_0002 - those devices that 
> > have a dq5 
> > > watchdog and those devices that don't have the watchdog, but have a 
> > > bit inverter on dq7.
> > > 
> > > Am I not understanding what happens on bits 0-5 during an 
> > erase/write 
> > > operation?  The PMC and SST chips don't mention a thing about dq5 
> > > behavior.  If they don't have the dq5 watchdog timer then they will 
> > > behave in an undefined way (depending on the state of bit 5 in the 
> > > written word) with the current dq5 checking.  This explains 
> > the many 
> > > warnings I see with the SST and PMC chips in do_write_oneword(),
> > > 
> > > "Warning: DQ5 raised while program operation was in 
> > progress, however 
> > > operation completed OK"
> > > 
> > > Around here we refer to this as the "Dairy Queen 5" warning.
> > > 
> > > Obviosly, during an erase that completes prior to dq5 being 
> > read-back, 
> > > dq5 will be high and the current algorithm is erroneously correct.  
> > > This can explain why I have not seen the same message in 
> > > do_erase_oneblock().
> > > 
> > > Furthermore, the SST documentation on page 10 refers to "spurios 
> > > rejection" of good writes - differentiating between a write that 
> > > succeeds that appears to fail and a write that fails.  It 
> > says that a 
> > > write that appears to fail needs to be read back two more times 
> > > successfully to filter out spurious rejection.
> > > 
> > > Comments?  What should change to improve the operation completion 
> > > check?  Should cfi_cmdset_0002 be adapted to handle 
> > multiple types of 
> > > polling or should another command set be written?
> > > 
> > > --
> > > Thayne Harbaugh
> > > Linux Networx
> > 
> > 
> > 
> > ______________________________________________________
> > Linux MTD discussion mailing list
> > http://lists.infradead.org/mailman/listinfo/linux-mtd/
> > 

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[John Burch]

> -----Original Message-----
> From: Steve Wahl [mailto:swahl at brecis.com]=20
> Sent: Wednesday, March 12, 2003 4:43 PM
> To: John Burch
> Cc: 'Thayne Harbaugh'; linux-mtd at lists.infradead.org
> Subject: Re: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy=20
> Queen 5 warning)
>=20
>=20
> On Wed, Mar 12, 2003 at 12:12:12PM -0500, John Burch wrote:
> > AMD's own method from code they provide is shown below...
> >=20
> > By the way, AMD specifically mentions having to check DQ6/7 again=20
> > after DQ5=3D1 because of the possibility that DQ5=3D1 simultaneous =
with=20
> > toggling stopping.  The app note I referred to before (attached this
> > time) describes this in some detail.
>=20
> I agree with this.
>=20
> > The status register (including DQ5) won't reflect actual=20
> data until a=20
> > reset command is issued,
>=20
> This I think is a misunderstanding or misstatement on your=20
> part.  The reads WILL return to actual data without a reset=20
> upon successful completion of the operation.  Only on a=20
> failure does software need to issue the reset to return to=20
> reading data!
>=20
> The app note you attached agrees with me on this.

You are correct, sir.

>=20
> > so I think the concern about DQ5=3D1 because erased data=20
> (0xff) is read=20
> > instead of status is not valid.
>=20
> I disagree.  This concern is indeed valid, and is the primary=20
> reason you must check for toggling AFTER noticing DQ5=3D1 in=20
> the first place.

You're right, again.  I'd focused in on the error case where a
reset has to be issued when DQ5 goes high due to an actual
timeout, and not the normal case where the device returns to
"read" mode automatically upon successful completion of the
command.  Thanks for straightening me out.

>=20
> Note that cfiflash below does not handle interleave nor bit=20
> endianness, so you can't adopt it directly.
>=20
> --> Steve
>=20
> > John
> >=20
> > >From AMD's cfiflash.c:
> >=20
> >=20
> /*************************************************************
> ********/
> > /* Flash_status utilizes the DQ6, DQ5, and DQ3 polling=20
> algorithms    */
> > /* described in the flash data book.  It can quickly=20
> ascertain the   */
> > /* operational status of the flash device, and return an   =20
>          */
> > /* appropriate status code (defined in flash.h)            =20
>          */
> >=20
> /*********************************************************************
> > /
> > =20
> > int flash_status(word far *fp)
> > {
> > 	 unsigned char d, t;
> > 	 int retry =3D 1;
> >=20
> > again:
> >=20
> > 	 d =3D *fp;        /* read data */
> > 	 t =3D d ^ *fp;    /* read it again and see what toggled */
> >=20
> > 	 if (t =3D=3D 0) {           /* no toggles, nothing's happening */
> > 		return STATUS_READY;
> > 	 }
> > 	 else if (t =3D=3D 0x04) { /* erase-suspend */
> > 		if (retry--) goto again;    /* may have been write
> > completion */
> > 		return STATUS_ERSUSP;
> > 	 }
> > 	 else if (t & 0x40) {
> > 		if (d & 0x20) {     /* timeout */
> > 		  return STATUS_TIMEOUT;
> > 		}
> > 		else {
> > 		  return STATUS_BUSY;
> > 		}
> > 	 }
> >=20
> > 	 if (retry--) goto again;    /* may have been write completion
> > */
> >=20
> > 	 return STATUS_ERROR;
> > }
> >=20
> >=20
> >=20
> > > -----Original Message-----
> > > From: linux-mtd-admin at lists.infradead.org
> > > [mailto:linux-mtd-admin at lists.infradead.org] On Behalf Of=20
> Steve Wahl
> > > Sent: Wednesday, March 12, 2003 11:28 AM
> > > To: Thayne Harbaugh
> > > Cc: linux-mtd at lists.infradead.org
> > > Subject: Re: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy=20
> > > Queen 5 warning)
> > >=20
> > >=20
> > > Thayne,
> > >=20
> > > I have a patch that I was given permission to check in, but
> > > never got around to it, that covers a similar "DQ5=20
> raised" problem.
> > >=20
> > > I would wager you are running into the same problem I did,
> > > and that your chips compatibly support DQ5, if not as a=20
> > > watchdog, at least by holding it low while programming.
> > >=20
> > > Can you look at my previous posts on this, try my patch (if
> > > you don't have interleaved chips -- contact me if you do),=20
> > > and see if it works for you?
> > >=20
> > > http://lists.infradead.org/pipermail/linux-mtd/2003-January/00
> > > 6780.html
> > >=20
> > > --> Steve
> > >=20
> > >=20
> > > On Tue, Mar 11, 2003 at 05:25:15PM -0700, Thayne Harbaugh wrote:
> > > > For some reason I am confused: I get the feeling that what
> > > I'm trying
> > > > to understand is obvious - I just can't see the forest for
> > > the trees.
> > > > Will someone help me understand?
> > > >=20
> > > > cfi_cmdset_0002.c has several functions that use dq5 and dq6 for
> > > > monitoring the status of erase and write operations:
> > > >=20
> > > > dq6 =3D CMD(1<<6);
> > > > dq5 =3D CMD(1<<5);
> > > >=20
> > > > Apparently, from the code dq6 toggles during erase/read
> > > operations and
> > > > dq5 is low until the erase/read operation times out and
> > > then goes high
> > > > (somewhat like a watchdog bit).
> > > >=20
> > > > My understanding, at least for the SST 49LF040 and PMC=20
> Pm49L004 is
> > > > that dq6 toggles during erase/write and dq7 is inverted=20
> until the=20
> > > > erase/write operation completes.  This causes me to expect=20
> > > to see the
> > > > following code rather than what is written above (not to
> > > mention that
> > > > most everything in do_write_one_word() should be adapted for dq7
> > > > invert):
> > > >=20
> > > > dq7 =3D CMD(1<<7); /* invert */
> > > > dq6 =3D CMD(1<<6); /* toggle */
> > > >=20
> > > > The differences give me the feeling that there really are two
> > > > different classes of cfi_cmdset_0002 - those devices that=20
> > > have a dq5
> > > > watchdog and those devices that don't have the=20
> watchdog, but have=20
> > > > a
> > > > bit inverter on dq7.
> > > >=20
> > > > Am I not understanding what happens on bits 0-5 during an
> > > erase/write
> > > > operation?  The PMC and SST chips don't mention a thing=20
> about dq5
> > > > behavior.  If they don't have the dq5 watchdog timer=20
> then they will=20
> > > > behave in an undefined way (depending on the state of=20
> bit 5 in the=20
> > > > written word) with the current dq5 checking.  This explains=20
> > > the many
> > > > warnings I see with the SST and PMC chips in do_write_oneword(),
> > > >=20
> > > > "Warning: DQ5 raised while program operation was in
> > > progress, however
> > > > operation completed OK"
> > > >=20
> > > > Around here we refer to this as the "Dairy Queen 5" warning.
> > > >=20
> > > > Obviosly, during an erase that completes prior to dq5 being
> > > read-back,
> > > > dq5 will be high and the current algorithm is=20
> erroneously correct.
> > > > This can explain why I have not seen the same message in=20
> > > > do_erase_oneblock().
> > > >=20
> > > > Furthermore, the SST documentation on page 10 refers to "spurios
> > > > rejection" of good writes - differentiating between a=20
> write that=20
> > > > succeeds that appears to fail and a write that fails.  It=20
> > > says that a
> > > > write that appears to fail needs to be read back two more times
> > > > successfully to filter out spurious rejection.
> > > >=20
> > > > Comments?  What should change to improve the operation=20
> completion
> > > > check?  Should cfi_cmdset_0002 be adapted to handle=20
> > > multiple types of
> > > > polling or should another command set be written?
> > > >=20
> > > > --
> > > > Thayne Harbaugh
> > > > Linux Networx
> > >=20
> > >=20
> > >=20
> > > ______________________________________________________
> > > Linux MTD discussion mailing list=20
> > > http://lists.infradead.org/mailman/listinfo/linux-mtd/
> > >=20
>=20
>=20
>=20

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[David Woodhouse]

On Wed, 2003-03-12 at 21:43, Steve Wahl wrote:

> Note that cfiflash below does not handle interleave nor bit
> endianness, so you can't adopt it directly.

And under what licence is it available?

-- 
dwmw2

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Russ Dill]

On Thu, 2003-03-13 at 00:17, David Woodhouse wrote:
> On Wed, 2003-03-12 at 21:43, Steve Wahl wrote:
> 
> > Note that cfiflash below does not handle interleave nor bit
> > endianness, so you can't adopt it directly.
> 
> And under what licence is it available?

here is some GPL code written by someone who's never looked at the AMD
code (until the previous email)

http://cvs.sourceforge.net/cgi-bin/viewcvs.cgi/blob/blob/src/blob/amd32.c?rev=1.6&content-type=text/vnd.viewcvs-markup

its a little complex because it handles two chips in an interleaved
configuration.

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Wed, 2003-03-12 at 09:27, Steve Wahl wrote:
> Thayne,=20
>=20
> I have a patch that I was given permission to check in, but never got
> around to it, that covers a similar "DQ5 raised" problem.

Speaking of never getting around to things - I'm finally replying to
your email.

> I would wager you are running into the same problem I did, and that
> your chips compatibly support DQ5, if not as a watchdog, at least by
> holding it low while programming.

I have sent email to PMC and the official response is that the _only_
bits that reflect erase/write operation status are I/O7 and I/O6
(effectively DQ7 and DQ6).  I/O7 is inverted data during the operation
and I/O6 toggles.  The PMC response was that AMD status bits aren't
supported.  In practice, however, DQ5 is low during erase/write
operations.  I am uneasy about using undocumented features.

> Can you look at my previous posts on this, try my patch (if you don't
> have interleaved chips -- contact me if you do),

No, I don't have interleaved chips.

> and see if it works
> for you?
>=20
> http://lists.infradead.org/pipermail/linux-mtd/2003-January/006780.html

I have looked through your patch and agree that it addresses a legal
state that currently triggers a warning and should not.  I do know,
however, that several manufactures recommend that the final status
should be checked an additional two times before a success is reported.

> --> Steve
>=20
>=20
> On Tue, Mar 11, 2003 at 05:25:15PM -0700, Thayne Harbaugh wrote:
> > For some reason I am confused: I get the feeling that what I'm trying t=
o
> > understand is obvious - I just can't see the forest for the trees.  Wil=
l
> > someone help me understand?
> >=20
> > cfi_cmdset_0002.c has several functions that use dq5 and dq6 for
> > monitoring the status of erase and write operations:
> >=20
> > dq6 =3D CMD(1<<6);
> > dq5 =3D CMD(1<<5);
> >=20
> > Apparently, from the code dq6 toggles during erase/read operations and
> > dq5 is low until the erase/read operation times out and then goes high
> > (somewhat like a watchdog bit).
> >=20
> > My understanding, at least for the SST 49LF040 and PMC Pm49L004 is that
> > dq6 toggles during erase/write and dq7 is inverted until the erase/writ=
e
> > operation completes.  This causes me to expect to see the following cod=
e
> > rather than what is written above (not to mention that most everything
> > in do_write_one_word() should be adapted for dq7 invert):
> >=20
> > dq7 =3D CMD(1<<7); /* invert */
> > dq6 =3D CMD(1<<6); /* toggle */
> >=20
> > The differences give me the feeling that there really are two different
> > classes of cfi_cmdset_0002 - those devices that have a dq5 watchdog and
> > those devices that don't have the watchdog, but have a bit inverter on
> > dq7.
> >=20
> > Am I not understanding what happens on bits 0-5 during an erase/write
> > operation?  The PMC and SST chips don't mention a thing about dq5
> > behavior.  If they don't have the dq5 watchdog timer then they will
> > behave in an undefined way (depending on the state of bit 5 in the
> > written word) with the current dq5 checking.  This explains the many
> > warnings I see with the SST and PMC chips in do_write_oneword(),
> >=20
> > "Warning: DQ5 raised while program operation was in progress, however
> > operation completed OK"
> >=20
> > Around here we refer to this as the "Dairy Queen 5" warning.
> >=20
> > Obviosly, during an erase that completes prior to dq5 being read-back,
> > dq5 will be high and the current algorithm is erroneously correct.  Thi=
s
> > can explain why I have not seen the same message in do_erase_oneblock()=
.
> >=20
> > Furthermore, the SST documentation on page 10 refers to "spurios
> > rejection" of good writes - differentiating between a write that
> > succeeds that appears to fail and a write that fails.  It says that a
> > write that appears to fail needs to be read back two more times
> > successfully to filter out spurious rejection.
> >=20
> > Comments?  What should change to improve the operation completion
> > check?  Should cfi_cmdset_0002 be adapted to handle multiple types of
> > polling or should another command set be written?
> >=20
> > --=20
> > Thayne Harbaugh
> > Linux Networx
>=20
>=20
>=20
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--=20
Thayne Harbaugh
Linux Networx

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Wed, 2003-03-12 at 14:43, Steve Wahl wrote:
> On Wed, Mar 12, 2003 at 12:12:12PM -0500, John Burch wrote:

<snip>

> > The status register (including DQ5) won't reflect actual data until
> > a reset command is issued,
>=20
> This I think is a misunderstanding or misstatement on your part.  The
> reads WILL return to actual data without a reset upon successful
> completion of the operation.  Only on a failure does software need to
> issue the reset to return to reading data!

Big question: how is it know if status bits are being read or the real
data that was written to an address?  I have read many data sheets and I
don't recall any of them discussing this concern.

> --> Steve
>=20
> > John
> >=20
> > >From AMD's cfiflash.c:
> >=20
> > /*********************************************************************/
> > /* Flash_status utilizes the DQ6, DQ5, and DQ3 polling algorithms    */
> > /* described in the flash data book.  It can quickly ascertain the   */
> > /* operational status of the flash device, and return an             */
> > /* appropriate status code (defined in flash.h)                      */
> > /*********************************************************************/
> > =20
> > int flash_status(word far *fp)
> > {
> > 	 unsigned char d, t;
> > 	 int retry =3D 1;
> >=20
> > again:
> >=20
> > 	 d =3D *fp;        /* read data */
> > 	 t =3D d ^ *fp;    /* read it again and see what toggled */
> >=20
> > 	 if (t =3D=3D 0) {           /* no toggles, nothing's happening */
> > 		return STATUS_READY;
> > 	 }
> > 	 else if (t =3D=3D 0x04) { /* erase-suspend */
> > 		if (retry--) goto again;    /* may have been write
> > completion */
> > 		return STATUS_ERSUSP;
> > 	 }
> > 	 else if (t & 0x40) {
> > 		if (d & 0x20) {     /* timeout */
> > 		  return STATUS_TIMEOUT;
> > 		}
> > 		else {
> > 		  return STATUS_BUSY;
> > 		}
> > 	 }
> >=20
> > 	 if (retry--) goto again;    /* may have been write completion
> > */
> >=20
> > 	 return STATUS_ERROR;
> > }
> >=20
> >=20
> >=20
> > > -----Original Message-----
> > > From: linux-mtd-admin at lists.infradead.org=20
> > > [mailto:linux-mtd-admin at lists.infradead.org] On Behalf Of Steve Wahl
> > > Sent: Wednesday, March 12, 2003 11:28 AM
> > > To: Thayne Harbaugh
> > > Cc: linux-mtd at lists.infradead.org
> > > Subject: Re: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy=20
> > > Queen 5 warning)
> > >=20
> > >=20
> > > Thayne,=20
> > >=20
> > > I have a patch that I was given permission to check in, but=20
> > > never got around to it, that covers a similar "DQ5 raised" problem.
> > >=20
> > > I would wager you are running into the same problem I did,=20
> > > and that your chips compatibly support DQ5, if not as a=20
> > > watchdog, at least by holding it low while programming.
> > >=20
> > > Can you look at my previous posts on this, try my patch (if=20
> > > you don't have interleaved chips -- contact me if you do),=20
> > > and see if it works for you?
> > >=20
> > > http://lists.infradead.org/pipermail/linux-mtd/2003-January/00
> > > 6780.html
> > >=20
> > > --> Steve
> > >=20
> > >=20
> > > On Tue, Mar 11, 2003 at 05:25:15PM -0700, Thayne Harbaugh wrote:
> > > > For some reason I am confused: I get the feeling that what=20
> > > I'm trying=20
> > > > to understand is obvious - I just can't see the forest for=20
> > > the trees. =20
> > > > Will someone help me understand?
> > > >=20
> > > > cfi_cmdset_0002.c has several functions that use dq5 and dq6 for=20
> > > > monitoring the status of erase and write operations:
> > > >=20
> > > > dq6 =3D CMD(1<<6);
> > > > dq5 =3D CMD(1<<5);
> > > >=20
> > > > Apparently, from the code dq6 toggles during erase/read=20
> > > operations and=20
> > > > dq5 is low until the erase/read operation times out and=20
> > > then goes high=20
> > > > (somewhat like a watchdog bit).
> > > >=20
> > > > My understanding, at least for the SST 49LF040 and PMC Pm49L004 is=20
> > > > that dq6 toggles during erase/write and dq7 is inverted until the=20
> > > > erase/write operation completes.  This causes me to expect=20
> > > to see the=20
> > > > following code rather than what is written above (not to=20
> > > mention that=20
> > > > most everything in do_write_one_word() should be adapted for dq7=20
> > > > invert):
> > > >=20
> > > > dq7 =3D CMD(1<<7); /* invert */
> > > > dq6 =3D CMD(1<<6); /* toggle */
> > > >=20
> > > > The differences give me the feeling that there really are two=20
> > > > different classes of cfi_cmdset_0002 - those devices that=20
> > > have a dq5=20
> > > > watchdog and those devices that don't have the watchdog, but have a=
=20
> > > > bit inverter on dq7.
> > > >=20
> > > > Am I not understanding what happens on bits 0-5 during an=20
> > > erase/write=20
> > > > operation?  The PMC and SST chips don't mention a thing about dq5=20
> > > > behavior.  If they don't have the dq5 watchdog timer then they will=
=20
> > > > behave in an undefined way (depending on the state of bit 5 in the=20
> > > > written word) with the current dq5 checking.  This explains=20
> > > the many=20
> > > > warnings I see with the SST and PMC chips in do_write_oneword(),
> > > >=20
> > > > "Warning: DQ5 raised while program operation was in=20
> > > progress, however=20
> > > > operation completed OK"
> > > >=20
> > > > Around here we refer to this as the "Dairy Queen 5" warning.
> > > >=20
> > > > Obviosly, during an erase that completes prior to dq5 being=20
> > > read-back,=20
> > > > dq5 will be high and the current algorithm is erroneously correct. =
=20
> > > > This can explain why I have not seen the same message in=20
> > > > do_erase_oneblock().
> > > >=20
> > > > Furthermore, the SST documentation on page 10 refers to "spurios=20
> > > > rejection" of good writes - differentiating between a write that=20
> > > > succeeds that appears to fail and a write that fails.  It=20
> > > says that a=20
> > > > write that appears to fail needs to be read back two more times=20
> > > > successfully to filter out spurious rejection.
> > > >=20
> > > > Comments?  What should change to improve the operation completion=20
> > > > check?  Should cfi_cmdset_0002 be adapted to handle=20
> > > multiple types of=20
> > > > polling or should another command set be written?
> > > >=20
> > > > --
> > > > Thayne Harbaugh
> > > > Linux Networx
> > >=20
> > >=20
> > >=20
> > > ______________________________________________________
> > > Linux MTD discussion mailing list
> > > http://lists.infradead.org/mailman/listinfo/linux-mtd/
> > >=20
>=20
>=20
>=20
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--=20
Thayne Harbaugh
Linux Networx

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[John Burch]

> -----Original Message-----
> From: Thayne Harbaugh [mailto:tharbaugh at lnxi.com]=20
> Sent: Monday, March 17, 2003 10:54 AM
> To: Steve Wahl
> Cc: John Burch; linux-mtd at lists.infradead.org
> Subject: Re: DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy=20
> Queen 5 warning)
>=20
<snip>
>=20
>=20
> Big question: how is it know if status bits are being read or=20
> the real data that was written to an address?  I have read=20
> many data sheets and I don't recall any of them discussing=20
> this concern.

I believe that if DQ6 is not toggling, then you're reading
actual data.  If DQ6 is toggling and DQ5=3D0, then you're reading
Status and the device is still busy.  If DQ6 is toggling and DQ5=3D1,
You're still reading status and DQ6 must be checked again.
If toggling, operation timed out, you're still reading status, and
reset command must be issued. If not toggling, operation completed,
and you're reading data.  (At least this is how AMD describes it.)

John

<snip>

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Steve Wahl]

On Mon, Mar 17, 2003 at 08:54:21AM -0700, Thayne Harbaugh wrote:
> On Wed, 2003-03-12 at 14:43, Steve Wahl wrote:
> > On Wed, Mar 12, 2003 at 12:12:12PM -0500, John Burch wrote:
> 
> <snip>
> 
> > > The status register (including DQ5) won't reflect actual data until
> > > a reset command is issued,
> > 
> > This I think is a misunderstanding or misstatement on your part.  The
> > reads WILL return to actual data without a reset upon successful
> > completion of the operation.  Only on a failure does software need to
> > issue the reset to return to reading data!
> 
> Big question: how is it know if status bits are being read or the real
> data that was written to an address?  I have read many data sheets and I
> don't recall any of them discussing this concern.

Easy, at least in theory.  If two consecutive reads are the same, then
the DQ6 isn't toggling any longer, therfore you are reading data.

Only if the two consecutive reads are different can you assume that
you read the status register -- and you can only assume the FIRST read
was a status register, because the second read could have been after
changing to data mode.

But, outside of easy theories, there's a couple of gotchas in there.

I've read at least one data sheet that suggested that the switch from
the status register to the data "register" happens asyncronously to
processor reads, so it is possible, though very unlikely, to get some
bits from the status register and some bits from the actual data
within a single read -- if the read happens at the exact instance that
the chip is switching from one mode to the other.

I have never seen any code that takes this into account -- sample
code, data sheet flow charts, etc.  I think this may, however, have
something to do with what you wrote: "I do know, however, that several
manufactures recommend that the final status should be checked an
additional two times before a success is reported."  I'd be interested
to see specific data sheets or application notes that do this.


--> Steve

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Mon, 2003-03-17 at 09:19, Steve Wahl wrote:
> On Mon, Mar 17, 2003 at 08:54:21AM -0700, Thayne Harbaugh wrote:

<snip>

> > I do know, however, that several
> > manufactures recommend that the final status should be checked an
> > additional two times before a success is reported.


> I'd be interested
> to see specific data sheets or application notes that do this.

What I stated is not completely accurate.  Here is what SST states on
page 14 of _4_Mbit_LPC_Flash_SST49LF040_ in the Write Operation Status
Detection section:

The actual completion of the nonvolatile write is asynchronous with the
system; therefore, either a Data# Palling or Toggle Bit read may be
simultaneous with the completion of the Write cycle.  If this occurs,
the system may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6.  In order to prevent spurious
rejection, if an erroneous result occurs, the software routine should
include a loop to read the accessed location an additional two (2)
times.  If both reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.



>=20
>=20
> --> Steve
>=20
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--=20
Thayne Harbaugh
Linux Networx

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Mon, 2003-03-17 at 08:40, Thayne Harbaugh wrote:
> On Wed, 2003-03-12 at 09:27, Steve Wahl wrote:

<snip>

> > I would wager you are running into the same problem I did, and that
> > your chips compatibly support DQ5, if not as a watchdog, at least by
> > holding it low while programming.
>=20
> I have sent email to PMC and the official response is that the _only_
> bits that reflect erase/write operation status are I/O7 and I/O6
> (effectively DQ7 and DQ6).  I/O7 is inverted data during the operation
> and I/O6 toggles.  The PMC response was that AMD status bits aren't
> supported.  In practice, however, DQ5 is low during erase/write
> operations.  I am uneasy about using undocumented features.

I have been thinking about the above mentioned problem with DQ5.  I have
not seen DQ5 behavior documented in the SST49LF040 and Pm49FL00x
documentation and suspect that other chip documentation is similar. =20

Regardless of the current behavior of status bit 5 on these chips I
think the documentation should be followed.  This means that either the
cfi_cmdset_0002 driver needs to be adapted to work with the "simplified"
polling in _addition_ to the current polling of DQ5 (some switch is
added to poll correctly for a given device) or a new cfi_cmdset_xxxx is
written specifically for this simplified command set.

I'm not sure what would be a nice, clean way to switch polling
mechanisms, but I hesitate to duplicate code for a nearly identical
cfi_cmdset.

Thoughts?

--=20
Thayne Harbaugh
Linux Networx

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Steve Wahl]

On Mon, Mar 17, 2003 at 11:27:41AM -0700, Thayne Harbaugh wrote:
> On Mon, 2003-03-17 at 09:19, Steve Wahl wrote:
> > On Mon, Mar 17, 2003 at 08:54:21AM -0700, Thayne Harbaugh wrote:
> 
> <snip>
> 
> > > I do know, however, that several
> > > manufactures recommend that the final status should be checked an
> > > additional two times before a success is reported.
> 
> 
> > I'd be interested
> > to see specific data sheets or application notes that do this.
> 
> What I stated is not completely accurate.  Here is what SST states on
> page 14 of _4_Mbit_LPC_Flash_SST49LF040_ in the Write Operation Status
> Detection section:
> 
> The actual completion of the nonvolatile write is asynchronous with the
> system; therefore, either a Data# Palling or Toggle Bit read may be
> simultaneous with the completion of the Write cycle.  If this occurs,
> the system may possibly get an erroneous result, i.e., valid data may
> appear to conflict with either DQ7 or DQ6.  In order to prevent spurious
> rejection, if an erroneous result occurs, the software routine should
> include a loop to read the accessed location an additional two (2)
> times.  If both reads are valid, then the device has completed the Write
> cycle, otherwise the rejection is valid.

Ahh.  If I read this correctly, if you are about to report an error
you should read two more times to make sure it's still there.

So your original wording should be "the final status should be checked
an additional two times before a *failure* is reported."  You could
legally / reasonably report success the instant you detect it.

Do you agree?

It is somewhat funny that if this was followed, I wouldn't have run
into the "DQ5 detected, but things seem OK" warning (can't remember
the original wording, sorry). 

--> Steve

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

--=-WR4q0zDjS2E9vaYtdMRV
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Content-Transfer-Encoding: quoted-printable

On Tue, 2003-03-18 at 09:51, Steve Wahl wrote:
> On Mon, Mar 17, 2003 at 11:27:41AM -0700, Thayne Harbaugh wrote:
> > On Mon, 2003-03-17 at 09:19, Steve Wahl wrote:
> > > On Mon, Mar 17, 2003 at 08:54:21AM -0700, Thayne Harbaugh wrote:
> >=20
> > <snip>
> >=20
> > > > I do know, however, that several
> > > > manufactures recommend that the final status should be checked an
> > > > additional two times before a success is reported.
> >=20
> >=20
> > > I'd be interested
> > > to see specific data sheets or application notes that do this.
> >=20
> > What I stated is not completely accurate.  Here is what SST states on
> > page 14 of _4_Mbit_LPC_Flash_SST49LF040_ in the Write Operation Status
> > Detection section:
> >=20
> > The actual completion of the nonvolatile write is asynchronous with the
> > system; therefore, either a Data# Palling or Toggle Bit read may be
> > simultaneous with the completion of the Write cycle.  If this occurs,
> > the system may possibly get an erroneous result, i.e., valid data may
> > appear to conflict with either DQ7 or DQ6.  In order to prevent spuriou=
s
> > rejection, if an erroneous result occurs, the software routine should
> > include a loop to read the accessed location an additional two (2)
> > times.  If both reads are valid, then the device has completed the Writ=
e
> > cycle, otherwise the rejection is valid.
>=20
> Ahh.  If I read this correctly, if you are about to report an error
> you should read two more times to make sure it's still there.
>=20
> So your original wording should be "the final status should be checked
> an additional two times before a *failure* is reported."  You could
> legally / reasonably report success the instant you detect it.
>=20
> Do you agree?

Yes, that's exactly how I interpret it after re-reading it.  I have seen
this statement in more than one vendor's documentation.  This is also
the way I am writing my AMD simplified command set driver.

The part that I still scratch my head about is why it needs to read
correctly on _both_ reads.  Why is it not good enough to have success on
the last read?

> It is somewhat funny that if this was followed, I wouldn't have run
> into the "DQ5 detected, but things seem OK" warning (can't remember
> the original wording, sorry).=20

Yes, that would have eliminated the error.

>=20
> --> Steve
--=20
Thayne Harbaugh
Linux Networx

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Comment: For info see http://www.gnupg.org

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

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On Mon, 2003-03-17 at 11:38, Thayne Harbaugh wrote:

> I have been thinking about the above mentioned problem with DQ5.  I have
> not seen DQ5 behavior documented in the SST49LF040 and Pm49FL00x
> documentation and suspect that other chip documentation is similar.

I wonder if this DQ5 for non suspend/resume chips is documented in
JESD21C.  Does anyone know or ever have an idea where to begin digging
through all the JEDEC meeting notes, etc.?

> Regardless of the current behavior of status bit 5 on these chips I
> think the documentation should be followed.

It's just plain dangerous to follow non-documented behavior.

>   This means that either the
> cfi_cmdset_0002 driver needs to be adapted to work with the "simplified"
> polling in _addition_ to the current polling of DQ5 (some switch is
> added to poll correctly for a given device) or a new cfi_cmdset_xxxx is
> written specifically for this simplified command set.
>=20
> I'm not sure what would be a nice, clean way to switch polling
> mechanisms, but I hesitate to duplicate code for a nearly identical
> cfi_cmdset.

I have worked up a patch that adds a new cfi_cmdset to the mix.  This is
for devices that support a subset or a simplified AMD command set
without the suspend/resume commands and extra query bits.

I feel it's good because I don't feel comfortable trusting the behavior
of DQ5 being low during erase/write operations for devices that don't
support DQ5 and have undocumented behavior for bits other than DQ7 and
DQ6.  It throws out suspend and resume functions and polls exclusively
on DQ7 and DQ6.

I have called this a simplified AMD commandset (ugly name - give me
something better) and have pulled cfi_cmdset_0005 out of the hat (I'm
not sure how the command set numbers are chosen).

Jedec devices listed in jedec_probe.c:jedec_table[] that don't support
suspend resume are marked as P_ID_AMD_SIMPLIFIED (new entry in cfi.h).

I'm not sure why gen_probe.c/check_cmd_set() uses the hex numbers in the
switch statement rather than the P_ID_* #define's from cfi.h - I used
the #define.

  It likely could be simplified even more - take out feeble support for
interleaved chips (which I don't have and can't test and I'm not even
sure that the chips that work this way support interleaving).

Sometimes I wish all of the command sets shared more code - other times
I'm glad they are split.

Should I commit it to CVS?  It works for me(TM).

> Thoughts?

Sorry to reply to myself - I talk back to myself as well.

I still think that the current cfi_cmdset_0002.c needs a fix similar to
what Steve Wahl proposed.  Has that settled and will it be committed?

--=20
Thayne Harbaugh
Linux Networx

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diff -uNr mtd/drivers/mtd/chips/cfi_cmdset_0005.c mtd-amd_simplified/driver=
s/mtd/chips/cfi_cmdset_0005.c
--- mtd/drivers/mtd/chips/cfi_cmdset_0005.c	1969-12-31 17:00:00.000000000 -=
0700
+++ mtd-amd_simplified/drivers/mtd/chips/cfi_cmdset_0005.c	2003-03-18 16:51=
:05.000000000 -0700
@@ -0,0 +1,1027 @@
+/*
+ * Common Flash Interface support:
+ *   AMD Simplified command set (ID 0x0005)
+ *
+ * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
+ * Copyright (C) 2003 Linux Networx - adapted to AMD simplified
+ *     command set by Thayne Harbaugh.  This is nearly the same
+ *     as cfi_cmdset_0002 except for the polling mechanism for
+ *     erase/write operations and the removal of extra
+ *     functionality: erase suspend and resume.  Ideally this and
+ *     cfi_cmdset_0002 should share as much as possible.
+ *
+ * Although this looks like it was written for interleaved chips,
+ *     it has never been tested.  Ise at your own risk and send
+ *     in the patches.
+ *
+ * This code is GPL
+ *
+ * $Id$
+ *
+ */
+
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/cfi.h>
+
+
+static int cfi_amdsmpl_read (struct mtd_info *, loff_t, size_t, size_t *, =
u_char *);
+static int cfi_amdsmpl_write(struct mtd_info *, loff_t, size_t, size_t *, =
const u_char *);
+static int cfi_amdsmpl_erase_onesize(struct mtd_info *, struct erase_info =
*);
+static int cfi_amdsmpl_erase_varsize(struct mtd_info *, struct erase_info =
*);
+static void cfi_amdsmpl_sync (struct mtd_info *);
+static int cfi_amdsmpl_secsi_read (struct mtd_info *, loff_t, size_t, size=
_t *, u_char *);
+
+static void cfi_amdsmpl_destroy(struct mtd_info *);
+
+struct mtd_info *cfi_cmdset_0005(struct map_info *, int);
+static struct mtd_info *cfi_amdsmpl_setup (struct map_info *);
+
+
+static struct mtd_chip_driver cfi_amdsmpl_chipdrv =3D {
+	probe: NULL, /* Not usable directly */
+	destroy: cfi_amdsmpl_destroy,
+	name: "cfi_cmdset_0005",
+	module: THIS_MODULE
+};
+
+struct mtd_info *cfi_cmdset_0005(struct map_info *map, int primary)
+{
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	unsigned char bootloc;
+	int ofs_factor =3D cfi->interleave * cfi->device_type;
+	int i;
+	__u8 major, minor;
+	__u32 base =3D cfi->chips[0].start;
+
+	if (cfi->cfi_mode=3D=3DCFI_MODE_CFI){
+		__u16 adr =3D primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
+
+		cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL);
+	=09
+		major =3D cfi_read_query(map, base + (adr+3)*ofs_factor);
+		minor =3D cfi_read_query(map, base + (adr+4)*ofs_factor);
+	=09
+		printk(KERN_NOTICE " Amd/Fujitsu Extended Query Table v%c.%c at 0x%4.4X\=
n",
+		       major, minor, adr);
+				cfi_send_gen_cmd(0xf0, 0x55, base, map, cfi, cfi->device_type, NULL);
+	=09
+		cfi_send_gen_cmd(0xaa, 0x555, base, map, cfi, cfi->device_type, NULL);
+		cfi_send_gen_cmd(0x55, 0x2aa, base, map, cfi, cfi->device_type, NULL);
+		cfi_send_gen_cmd(0x90, 0x555, base, map, cfi, cfi->device_type, NULL);
+		cfi->mfr =3D cfi_read_query(map, base);
+		cfi->id =3D cfi_read_query(map, base + ofs_factor);   =20
+
+		/* Wheee. Bring me the head of someone at AMD. */
+		cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL);
+		bootloc =3D cfi_read_query(map, base + (adr+15)*ofs_factor);
+		if (bootloc =3D=3D 3 && cfi->cfiq->NumEraseRegions > 1) {
+			printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n=
", map->name);
+		=09
+			for (i=3D0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
+				int j =3D (cfi->cfiq->NumEraseRegions-1)-i;
+				__u32 swap;
+			=09
+				swap =3D cfi->cfiq->EraseRegionInfo[i];
+				cfi->cfiq->EraseRegionInfo[i] =3D cfi->cfiq->EraseRegionInfo[j];
+				cfi->cfiq->EraseRegionInfo[j] =3D swap;
+			}
+		}
+		switch (cfi->device_type) {
+		case CFI_DEVICETYPE_X8:
+			cfi->addr_unlock1 =3D 0x555;=20
+			cfi->addr_unlock2 =3D 0x2aa;=20
+			break;
+		case CFI_DEVICETYPE_X16:
+			cfi->addr_unlock1 =3D 0xaaa;
+			if (map->buswidth =3D=3D cfi->interleave) {
+				/* X16 chip(s) in X8 mode */
+				cfi->addr_unlock2 =3D 0x555;
+			} else {
+				cfi->addr_unlock2 =3D 0x554;
+			}
+			break;
+		case CFI_DEVICETYPE_X32:
+			cfi->addr_unlock1 =3D 0x1555;=20
+			cfi->addr_unlock2 =3D 0xaaa;=20
+			break;
+		default:
+			printk(KERN_NOTICE "Eep. Unknown cfi_cmdset_0005 device type %d\n", cfi=
->device_type);
+			return NULL;
+		}
+	} /* CFI mode */
+
+	for (i=3D0; i< cfi->numchips; i++) {
+		cfi->chips[i].word_write_time =3D 1<<cfi->cfiq->WordWriteTimeoutTyp;
+		cfi->chips[i].buffer_write_time =3D 1<<cfi->cfiq->BufWriteTimeoutTyp;
+		cfi->chips[i].erase_time =3D 1<<cfi->cfiq->BlockEraseTimeoutTyp;
+	}	=09
+=09
+	map->fldrv =3D &cfi_amdsmpl_chipdrv;
+
+	cfi_send_gen_cmd(0xf0, 0x55, base, map, cfi, cfi->device_type, NULL);
+	return cfi_amdsmpl_setup(map);
+}
+
+static struct mtd_info *cfi_amdsmpl_setup(struct map_info *map)
+{
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	struct mtd_info *mtd;
+	unsigned long devsize =3D (1<<cfi->cfiq->DevSize) * cfi->interleave;
+
+	mtd =3D kmalloc(sizeof(*mtd), GFP_KERNEL);
+	printk(KERN_NOTICE "number of %s chips: %d\n",=20
+		(cfi->cfi_mode =3D=3D CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
+
+	if (!mtd) {
+	  printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
+	  goto setup_err;
+	}
+
+	memset(mtd, 0, sizeof(*mtd));
+	mtd->priv =3D map;
+	mtd->type =3D MTD_NORFLASH;
+	/* Also select the correct geometry setup too */=20
+	mtd->size =3D devsize * cfi->numchips;
+=09
+	if (cfi->cfiq->NumEraseRegions =3D=3D 1) {
+		/* No need to muck about with multiple erase sizes */
+		mtd->erasesize =3D ((cfi->cfiq->EraseRegionInfo[0] >> 8) & ~0xff) * cfi-=
>interleave;
+	} else {
+		unsigned long offset =3D 0;
+		int i,j;
+
+		mtd->numeraseregions =3D cfi->cfiq->NumEraseRegions * cfi->numchips;
+		mtd->eraseregions =3D kmalloc(sizeof(struct mtd_erase_region_info) * mtd=
->numeraseregions, GFP_KERNEL);
+		if (!mtd->eraseregions) {=20
+			printk(KERN_WARNING "Failed to allocate memory for MTD erase region inf=
o\n");
+			goto setup_err;
+		}
+		=09
+		for (i=3D0; i<cfi->cfiq->NumEraseRegions; i++) {
+			unsigned long ernum, ersize;
+			ersize =3D ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interl=
eave;
+			ernum =3D (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
+		=09
+			if (mtd->erasesize < ersize) {
+				mtd->erasesize =3D ersize;
+			}
+			for (j=3D0; j<cfi->numchips; j++) {
+				mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset =3D (j*devs=
ize)+offset;
+				mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize =3D ersi=
ze;
+				mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks =3D ernu=
m;
+			}
+			offset +=3D (ersize * ernum);
+		}
+		if (offset !=3D devsize) {
+			/* Argh */
+			printk(KERN_WARNING "Sum of regions (%lx) !=3D total size of set of int=
erleaved chips (%lx)\n", offset, devsize);
+			goto setup_err;
+		}
+#if 0
+		// debug
+		for (i=3D0; i<mtd->numeraseregions;i++){
+			printk("%d: offset=3D0x%x,size=3D0x%x,blocks=3D%d\n",
+			       i,mtd->eraseregions[i].offset,
+			       mtd->eraseregions[i].erasesize,
+			       mtd->eraseregions[i].numblocks);
+		}
+#endif
+	}
+
+	switch (CFIDEV_BUSWIDTH)
+	{
+	case 1:
+	case 2:
+	case 4:
+#if 1
+		if (mtd->numeraseregions > 1)
+			mtd->erase =3D cfi_amdsmpl_erase_varsize;
+		else
+#endif
+			mtd->erase =3D cfi_amdsmpl_erase_onesize;
+		mtd->read =3D cfi_amdsmpl_read;
+		mtd->write =3D cfi_amdsmpl_write;
+		break;
+
+	default:
+	        printk(KERN_WARNING "Unsupported buswidth\n");
+		goto setup_err;
+		break;
+	}
+	if (cfi->fast_prog) {
+		/* In cfi_amdsmpl_write() we frob the protection stuff
+		   without paying any attention to the state machine.
+		   This upsets in-progress erases. So we turn this flag
+		   off for now till the code gets fixed. */
+		printk(KERN_NOTICE "cfi_cmdset_0005: Disabling fast programming due to c=
ode brokenness.\n");
+		cfi->fast_prog =3D 0;
+	}
+
+
+        /* does this chip have a secsi area? */
+	if(cfi->mfr=3D=3D1){
+	=09
+		switch(cfi->id){
+		case 0x50:
+		case 0x53:
+		case 0x55:
+		case 0x56:
+		case 0x5C:
+		case 0x5F:
+			/* Yes */
+			mtd->read_user_prot_reg =3D cfi_amdsmpl_secsi_read;
+			mtd->read_fact_prot_reg =3D cfi_amdsmpl_secsi_read;
+		default:		      =20
+			;
+		}
+	}
+=09
+	=09
+	mtd->sync =3D cfi_amdsmpl_sync;
+	mtd->suspend =3D NULL;
+	mtd->resume =3D NULL;
+	mtd->flags =3D MTD_CAP_NORFLASH;
+	map->fldrv =3D &cfi_amdsmpl_chipdrv;
+	mtd->name =3D map->name;
+	MOD_INC_USE_COUNT;
+	return mtd;
+
+ setup_err:
+	if(mtd) {
+		if(mtd->eraseregions)
+			kfree(mtd->eraseregions);
+		kfree(mtd);
+	}
+	kfree(cfi->cmdset_priv);
+	kfree(cfi->cfiq);
+	return NULL;
+}
+
+static inline int do_read_onechip(struct map_info *map, struct flchip *chi=
p, loff_t adr, size_t len, u_char *buf)
+{
+	DECLARE_WAITQUEUE(wait, current);
+	unsigned long timeo =3D jiffies + HZ;
+
+ retry:
+	cfi_spin_lock(chip->mutex);
+
+	if (chip->state !=3D FL_READY){
+#if 0
+	        printk(KERN_DEBUG "Waiting for chip to read, status =3D %d\n", ch=
ip->state);
+#endif
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&chip->wq, &wait);
+               =20
+		cfi_spin_unlock(chip->mutex);
+
+		schedule();
+		remove_wait_queue(&chip->wq, &wait);
+#if 0
+		if(signal_pending(current))
+			return -EINTR;
+#endif
+		timeo =3D jiffies + HZ;
+
+		goto retry;
+	}=09
+
+	adr +=3D chip->start;
+
+	chip->state =3D FL_READY;
+
+	map->copy_from(map, buf, adr, len);
+
+	wake_up(&chip->wq);
+	cfi_spin_unlock(chip->mutex);
+
+	return 0;
+}
+
+static int cfi_amdsmpl_read (struct mtd_info *mtd, loff_t from, size_t len=
, size_t *retlen, u_char *buf)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	unsigned long ofs;
+	int chipnum;
+	int ret =3D 0;
+
+	/* ofs: offset within the first chip that the first read should start */
+
+	chipnum =3D (from >> cfi->chipshift);
+	ofs =3D from - (chipnum <<  cfi->chipshift);
+
+
+	*retlen =3D 0;
+
+	while (len) {
+		unsigned long thislen;
+
+		if (chipnum >=3D cfi->numchips)
+			break;
+
+		if ((len + ofs -1) >> cfi->chipshift)
+			thislen =3D (1<<cfi->chipshift) - ofs;
+		else
+			thislen =3D len;
+
+		ret =3D do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
+		if (ret)
+			break;
+
+		*retlen +=3D thislen;
+		len -=3D thislen;
+		buf +=3D thislen;
+
+		ofs =3D 0;
+		chipnum++;
+	}
+	return ret;
+}
+
+static inline int do_read_secsi_onechip(struct map_info *map, struct flchi=
p *chip, loff_t adr, size_t len, u_char *buf)
+{
+	DECLARE_WAITQUEUE(wait, current);
+	unsigned long timeo =3D jiffies + HZ;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+
+ retry:
+	cfi_spin_lock(chip->mutex);
+
+	if (chip->state !=3D FL_READY){
+#if 0
+	        printk(KERN_DEBUG "Waiting for chip to read, status =3D %d\n", ch=
ip->state);
+#endif
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&chip->wq, &wait);
+               =20
+		cfi_spin_unlock(chip->mutex);
+
+		schedule();
+		remove_wait_queue(&chip->wq, &wait);
+#if 0
+		if(signal_pending(current))
+			return -EINTR;
+#endif
+		timeo =3D jiffies + HZ;
+
+		goto retry;
+	}=09
+
+	adr +=3D chip->start;
+
+	chip->state =3D FL_READY;
+=09
+	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+	cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+=09
+	map->copy_from(map, buf, adr, len);
+
+	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+	cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+	cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->dev=
ice_type, NULL);
+=09
+	wake_up(&chip->wq);
+	cfi_spin_unlock(chip->mutex);
+
+	return 0;
+}
+
+static int cfi_amdsmpl_secsi_read (struct mtd_info *mtd, loff_t from, size=
_t len, size_t *retlen, u_char *buf)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	unsigned long ofs;
+	int chipnum;
+	int ret =3D 0;
+
+
+	/* ofs: offset within the first chip that the first read should start */
+
+	/* 8 secsi bytes per chip */
+	chipnum=3Dfrom>>3;
+	ofs=3Dfrom & 7;
+
+
+	*retlen =3D 0;
+
+	while (len) {
+		unsigned long thislen;
+
+		if (chipnum >=3D cfi->numchips)
+			break;
+
+		if ((len + ofs -1) >> 3)
+			thislen =3D (1<<3) - ofs;
+		else
+			thislen =3D len;
+
+		ret =3D do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, b=
uf);
+		if (ret)
+			break;
+
+		*retlen +=3D thislen;
+		len -=3D thislen;
+		buf +=3D thislen;
+
+		ofs =3D 0;
+		chipnum++;
+	}
+	return ret;
+}
+
+
+static inline int status_poll( struct map_info *map, struct flchip *chip, =
unsigned long adr, __u32 datum, unsigned long timeo )
+{
+	int ret =3D 0;
+	unsigned int dq6, dq7;=09
+	unsigned int oldstatus, status;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+
+	/*
+	 * Wait for the end of programing/erasure by using the toggle method.
+	 * As long as there is a programming procedure going on, bit 6 of the las=
t
+	 * written byte is toggling it's state with each consectuve read and
+	 * bit 7 is the complement of the data written.
+	 * The toggling stops as soon as the procedure is completed and bit
+	 * 7 represents true data.
+	 */
+
+	/*
+	 * Polling toggle bits instead of reading back many times
+	 * This ensures that write operation is really completed,
+	 */
+	dq6 =3D CMD(1<<6);     /* toggle until operation finishes */
+	dq7 =3D CMD(1<<7);     /* inverts data until operation finishes */
+
+	oldstatus =3D cfi_read(map, adr);
+	status =3D cfi_read(map, adr);
+	DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): Check 0x%.2x 0x%.2x\n", __func__, old=
status, status );
+
+	while( ( ( oldstatus ^ status ) & dq6 )
+	       && ( ( status ^ datum ) & dq7 )
+	       && ! time_after(jiffies, timeo) ) {
+
+		if (need_resched()) {
+			cfi_spin_unlock(chip->mutex);
+			yield();
+			cfi_spin_lock(chip->mutex);
+		} else=20
+			udelay(1);
+
+		oldstatus =3D cfi_read( map, adr );
+		status =3D cfi_read( map, adr );
+		DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): Check 0x%.2x 0x%.2x\n", __func__, ol=
dstatus, status );
+	}
+
+	if ( time_after( jiffies, timeo ) ) {
+		/*
+		 * The operation did not complete in reasonable time - the
+		 * chip should be reset.
+		 */
+		printk(KERN_WARNING
+		       "MTD %s(): Internal flash device timeout occured\n",
+		       __func__ );
+	        cfi_write( map, CMD(0xF0), chip->start );
+		ret =3D -EIO;
+	} else {
+
+		status =3D cfi_read(map, adr);
+
+		if ( datum !=3D status ) {
+			/* must check two more times and succeed for both */
+			oldstatus =3D cfi_read(map, adr);
+			status =3D cfi_read(map, adr);
+			if ( datum !=3D oldstatus || datum !=3D status ) {
+				DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): 0x%.2x !=3D 0x%.2x\n", __func__, s=
tatus, datum );
+				ret =3D -EIO;
+			}
+		}
+	}
+
+	return ret;
+}
+
+
+static int do_write_oneword(struct map_info *map, struct flchip *chip, uns=
igned long adr, __u32 datum, int fast)
+{
+	unsigned long timeo =3D jiffies + HZ;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+    /* We use a 1ms + 1 jiffies generic timeout for writes (most devices h=
ave
+       a max write time of a few hundreds usec). However, we should use th=
e
+       maximum timeout value given by the chip at probe time instead.=20
+       Unfortunately, struct flchip does have a field for maximum timeout,=
=20
+       only for typical which can be far too short depending of the condit=
ions.
+       The ' + 1' is to avoid having a timeout of 0 jiffies if HZ is small=
er
+       than 1000. Using a static variable allows makes us save the costly
+       divide operation at each word write.*/=20
+    static unsigned long uWriteTimeout =3D ( HZ / 1000 ) + 1;
+	DECLARE_WAITQUEUE(wait, current);
+	int ret =3D 0;
+
+ retry:
+	cfi_spin_lock(chip->mutex);
+
+	if (chip->state !=3D FL_READY) {
+#if 0
+	        printk(KERN_DEBUG "Waiting for chip to write, status =3D %d\n", c=
hip->state);
+#endif
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&chip->wq, &wait);
+               =20
+		cfi_spin_unlock(chip->mutex);
+
+		schedule();
+		remove_wait_queue(&chip->wq, &wait);
+#if 0
+		printk(KERN_DEBUG "Wake up to write:\n");
+		if(signal_pending(current))
+			return -EINTR;
+#endif
+		timeo =3D jiffies + HZ;
+
+		goto retry;
+	}=09
+
+	chip->state =3D FL_WRITING;
+
+	DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE (0x%.8lx)0x%.2x\n", __func__, a=
dr, datum );
+	adr +=3D chip->start;
+	ENABLE_VPP(map);
+	if (fast) { /* Unlock bypass */
+		cfi_send_gen_cmd(0xA0, 0, chip->start, map, cfi, cfi->device_type, NULL)=
;
+	}
+	else {
+	        cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, =
CFI_DEVICETYPE_X8, NULL);
+	        cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, =
CFI_DEVICETYPE_X8, NULL);
+	        cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, =
CFI_DEVICETYPE_X8, NULL);
+	}
+
+	cfi_write(map, datum, adr);
+
+	cfi_spin_unlock(chip->mutex);
+	cfi_udelay(chip->word_write_time);
+	cfi_spin_lock(chip->mutex);
+
+	/* See comment above for timeout value. */
+	ret =3D status_poll( map, chip, adr, datum, jiffies + uWriteTimeout );
+
+	DISABLE_VPP(map);
+	chip->state =3D FL_READY;
+	wake_up(&chip->wq);
+	cfi_spin_unlock(chip->mutex);
+
+	return ret;
+}
+
+
+static int cfi_amdsmpl_write (struct mtd_info *mtd, loff_t to , size_t len=
, size_t *retlen, const u_char *buf)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	int ret =3D 0;
+	int chipnum;
+	unsigned long ofs, chipstart;
+
+	*retlen =3D 0;
+	if (!len)
+		return 0;
+
+	chipnum =3D to >> cfi->chipshift;
+	ofs =3D to  - (chipnum << cfi->chipshift);
+	chipstart =3D cfi->chips[chipnum].start;
+
+	/* If it's not bus-aligned, do the first byte write */
+	if (ofs & (CFIDEV_BUSWIDTH-1)) {
+		unsigned long bus_ofs =3D ofs & ~(CFIDEV_BUSWIDTH-1);
+		int i =3D ofs - bus_ofs;
+		int n =3D 0;
+		u_char tmp_buf[8];
+		__u32 datum;
+
+		map->copy_from(map, tmp_buf, bus_ofs + cfi->chips[chipnum].start, CFIDEV=
_BUSWIDTH);
+		while (len && i < CFIDEV_BUSWIDTH)
+			tmp_buf[i++] =3D buf[n++], len--;
+
+		if (cfi_buswidth_is_2()) {
+			datum =3D *(__u16*)tmp_buf;
+		} else if (cfi_buswidth_is_4()) {
+			datum =3D *(__u32*)tmp_buf;
+		} else {
+			return -EINVAL;  /* should never happen, but be safe */
+		}
+
+		ret =3D do_write_oneword(map, &cfi->chips[chipnum],=20
+				bus_ofs, datum, 0);
+		if (ret)=20
+			return ret;
+	=09
+		ofs +=3D n;
+		buf +=3D n;
+		(*retlen) +=3D n;
+
+		if (ofs >> cfi->chipshift) {
+			chipnum ++;=20
+			ofs =3D 0;
+			if (chipnum =3D=3D cfi->numchips)
+				return 0;
+		}
+	}
+=09
+	if (cfi->fast_prog) {
+		/* Go into unlock bypass mode */
+		cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, CFI_DEVIC=
ETYPE_X8, NULL);
+		cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, CFI_DEVIC=
ETYPE_X8, NULL);
+		cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, CFI_DEVIC=
ETYPE_X8, NULL);
+	}
+
+	/* We are now aligned, write as much as possible */
+	while(len >=3D CFIDEV_BUSWIDTH) {
+		__u32 datum;
+
+		if (cfi_buswidth_is_1()) {
+			datum =3D *(__u8*)buf;
+		} else if (cfi_buswidth_is_2()) {
+			datum =3D *(__u16*)buf;
+		} else if (cfi_buswidth_is_4()) {
+			datum =3D *(__u32*)buf;
+		} else {
+			return -EINVAL;
+		}
+		ret =3D do_write_oneword(map, &cfi->chips[chipnum],
+				       ofs, datum, cfi->fast_prog);
+		if (ret) {
+			if (cfi->fast_prog){
+				/* Get out of unlock bypass mode */
+				cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL)=
;
+				cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL)=
;
+			}
+			return ret;
+		}
+
+		ofs +=3D CFIDEV_BUSWIDTH;
+		buf +=3D CFIDEV_BUSWIDTH;
+		(*retlen) +=3D CFIDEV_BUSWIDTH;
+		len -=3D CFIDEV_BUSWIDTH;
+
+		if (ofs >> cfi->chipshift) {
+			if (cfi->fast_prog){
+				/* Get out of unlock bypass mode */
+				cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL)=
;
+				cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL)=
;
+			}
+
+			chipnum ++;=20
+			ofs =3D 0;
+			if (chipnum =3D=3D cfi->numchips)
+				return 0;
+			chipstart =3D cfi->chips[chipnum].start;
+			if (cfi->fast_prog){
+				/* Go into unlock bypass mode for next set of chips */
+				cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chipstart, map, cfi, CFI_DEV=
ICETYPE_X8, NULL);
+				cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chipstart, map, cfi, CFI_DEV=
ICETYPE_X8, NULL);
+				cfi_send_gen_cmd(0x20, cfi->addr_unlock1, chipstart, map, cfi, CFI_DEV=
ICETYPE_X8, NULL);
+			}
+		}
+	}
+
+	if (cfi->fast_prog){
+		/* Get out of unlock bypass mode */
+		cfi_send_gen_cmd(0x90, 0, chipstart, map, cfi, cfi->device_type, NULL);
+		cfi_send_gen_cmd(0x00, 0, chipstart, map, cfi, cfi->device_type, NULL);
+	}
+
+	/* Write the trailing bytes if any */
+	if (len & (CFIDEV_BUSWIDTH-1)) {
+		int i =3D 0, n =3D 0;
+		u_char tmp_buf[8];
+		__u32 datum;
+
+		map->copy_from(map, tmp_buf, ofs + cfi->chips[chipnum].start, CFIDEV_BUS=
WIDTH);
+		while (len--)
+			tmp_buf[i++] =3D buf[n++];
+
+		if (cfi_buswidth_is_2()) {
+			datum =3D *(__u16*)tmp_buf;
+		} else if (cfi_buswidth_is_4()) {
+			datum =3D *(__u32*)tmp_buf;
+		} else {
+			return -EINVAL;  /* should never happen, but be safe */
+		}
+
+		ret =3D do_write_oneword(map, &cfi->chips[chipnum],=20
+				ofs, datum, 0);
+		if (ret)=20
+			return ret;
+	=09
+		(*retlen) +=3D n;
+	}
+
+	return 0;
+}
+
+
+static inline int do_erase_oneblock(struct map_info *map, struct flchip *c=
hip, unsigned long adr)
+{
+	int ret =3D 0;
+	unsigned long timeo =3D jiffies + HZ;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	DECLARE_WAITQUEUE(wait, current);
+	__u32 ones =3D 0;
+
+ retry:
+	cfi_spin_lock(chip->mutex);
+
+	if (chip->state !=3D FL_READY){
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&chip->wq, &wait);
+               =20
+		cfi_spin_unlock(chip->mutex);
+
+		schedule();
+		remove_wait_queue(&chip->wq, &wait);
+#if 0
+		if(signal_pending(current))
+			return -EINTR;
+#endif
+		timeo =3D jiffies + HZ;
+
+		goto retry;
+	}=09
+
+	chip->state =3D FL_ERASING;
+
+	DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n", __func__, adr );
+	adr +=3D chip->start;
+	ENABLE_VPP(map);
+	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, CFI_DEVI=
CETYPE_X8, NULL);
+	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, CFI_DEVI=
CETYPE_X8, NULL);
+	cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, CFI_DEVI=
CETYPE_X8, NULL);
+	cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, CFI_DEVI=
CETYPE_X8, NULL);
+	cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, CFI_DEVI=
CETYPE_X8, NULL);
+	cfi_write(map, CMD(0x30), adr);
+
+	switch( CFIDEV_BUSWIDTH ) {
+	case 1:
+		ones =3D (__u8)~0;
+		break;
+	case 2:
+		ones =3D (__u16)~0;
+		break;
+	case 4:
+		ones =3D (__u32)~0;
+		break;
+	}
+=09
+	ret =3D status_poll( map, chip, adr, ones, jiffies + (HZ*20) );
+
+	DISABLE_VPP(map);
+	chip->state =3D FL_READY;
+	wake_up(&chip->wq);
+	cfi_spin_unlock(chip->mutex);
+	return ret;
+}
+
+
+static int cfi_amdsmpl_erase_varsize(struct mtd_info *mtd, struct erase_in=
fo *instr)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	unsigned long adr, len;
+	int chipnum, ret =3D 0;
+	int i, first;
+	struct mtd_erase_region_info *regions =3D mtd->eraseregions;
+
+	if (instr->addr > mtd->size)
+		return -EINVAL;
+
+	if ((instr->len + instr->addr) > mtd->size)
+		return -EINVAL;
+
+	/* Check that both start and end of the requested erase are
+	 * aligned with the erasesize at the appropriate addresses.
+	 */
+
+	i =3D 0;
+
+	/* Skip all erase regions which are ended before the start of=20
+	   the requested erase. Actually, to save on the calculations,
+	   we skip to the first erase region which starts after the
+	   start of the requested erase, and then go back one.
+	*/
+=09
+	while (i < mtd->numeraseregions && instr->addr >=3D regions[i].offset)
+	       i++;
+	i--;
+
+	/* OK, now i is pointing at the erase region in which this=20
+	   erase request starts. Check the start of the requested
+	   erase range is aligned with the erase size which is in
+	   effect here.
+	*/
+
+	if (instr->addr & (regions[i].erasesize-1))
+		return -EINVAL;
+
+	/* Remember the erase region we start on */
+	first =3D i;
+
+	/* Next, check that the end of the requested erase is aligned
+	 * with the erase region at that address.
+	 */
+
+	while (i<mtd->numeraseregions && (instr->addr + instr->len) >=3D regions[=
i].offset)
+		i++;
+
+	/* As before, drop back one to point at the region in which
+	   the address actually falls
+	*/
+	i--;
+=09
+	if ((instr->addr + instr->len) & (regions[i].erasesize-1))
+		return -EINVAL;
+=09
+	chipnum =3D instr->addr >> cfi->chipshift;
+	adr =3D instr->addr - (chipnum << cfi->chipshift);
+	len =3D instr->len;
+
+	i=3Dfirst;
+
+	while(len) {
+		ret =3D do_erase_oneblock(map, &cfi->chips[chipnum], adr);
+
+		if (ret)
+			return ret;
+
+		adr +=3D regions[i].erasesize;
+		len -=3D regions[i].erasesize;
+
+		if (adr % (1<< cfi->chipshift) =3D=3D ((regions[i].offset + (regions[i].=
erasesize * regions[i].numblocks)) %( 1<< cfi->chipshift)))
+			i++;
+
+		if (adr >> cfi->chipshift) {
+			adr =3D 0;
+			chipnum++;
+		=09
+			if (chipnum >=3D cfi->numchips)
+			break;
+		}
+	}
+
+	instr->state =3D MTD_ERASE_DONE;
+	if (instr->callback)
+		instr->callback(instr);
+=09
+	return 0;
+}
+
+
+static int cfi_amdsmpl_erase_onesize(struct mtd_info *mtd, struct erase_in=
fo *instr)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	unsigned long adr, len;
+	int chipnum, ret =3D 0;
+
+	if (instr->addr & (mtd->erasesize - 1))
+		return -EINVAL;
+
+	if (instr->len & (mtd->erasesize -1))
+		return -EINVAL;
+
+	if ((instr->len + instr->addr) > mtd->size)
+		return -EINVAL;
+
+	chipnum =3D instr->addr >> cfi->chipshift;
+	adr =3D instr->addr - (chipnum << cfi->chipshift);
+	len =3D instr->len;
+
+	while(len) {
+		ret =3D do_erase_oneblock(map, &cfi->chips[chipnum], adr);
+
+		if (ret)
+			return ret;
+
+		adr +=3D mtd->erasesize;
+		len -=3D mtd->erasesize;
+
+		if (adr >> cfi->chipshift) {
+			adr =3D 0;
+			chipnum++;
+		=09
+			if (chipnum >=3D cfi->numchips)
+			break;
+		}
+	}
+	=09
+	instr->state =3D MTD_ERASE_DONE;
+	if (instr->callback)
+		instr->callback(instr);
+=09
+	return 0;
+}
+
+
+static void cfi_amdsmpl_sync (struct mtd_info *mtd)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	int i;
+	struct flchip *chip;
+	int ret =3D 0;
+	DECLARE_WAITQUEUE(wait, current);
+
+	for (i=3D0; !ret && i<cfi->numchips; i++) {
+		chip =3D &cfi->chips[i];
+
+	retry:
+		cfi_spin_lock(chip->mutex);
+
+		switch(chip->state) {
+		case FL_READY:
+		case FL_STATUS:
+		case FL_CFI_QUERY:
+		case FL_JEDEC_QUERY:
+			chip->oldstate =3D chip->state;
+			chip->state =3D FL_SYNCING;
+			/* No need to wake_up() on this state change -=20
+			 * as the whole point is that nobody can do anything
+			 * with the chip now anyway.
+			 */
+		case FL_SYNCING:
+			cfi_spin_unlock(chip->mutex);
+			break;
+
+		default:
+			/* Not an idle state */
+			add_wait_queue(&chip->wq, &wait);
+		=09
+			cfi_spin_unlock(chip->mutex);
+
+			schedule();
+
+		        remove_wait_queue(&chip->wq, &wait);
+		=09
+			goto retry;
+		}
+	}
+
+	/* Unlock the chips again */
+
+	for (i--; i >=3D0; i--) {
+		chip =3D &cfi->chips[i];
+
+		cfi_spin_lock(chip->mutex);
+	=09
+		if (chip->state =3D=3D FL_SYNCING) {
+			chip->state =3D chip->oldstate;
+			wake_up(&chip->wq);
+		}
+		cfi_spin_unlock(chip->mutex);
+	}
+}
+
+
+static void cfi_amdsmpl_destroy(struct mtd_info *mtd)
+{
+	struct map_info *map =3D mtd->priv;
+	struct cfi_private *cfi =3D map->fldrv_priv;
+	kfree(cfi->cmdset_priv);
+	kfree(cfi->cfiq);
+	kfree(cfi);
+	kfree(mtd->eraseregions);
+}
+
+static char im_name[]=3D"cfi_cmdset_0005";
+
+int __init cfi_amdsmpl_init(void)
+{
+	inter_module_register(im_name, THIS_MODULE, &cfi_cmdset_0005);
+	return 0;
+}
+
+static void __exit cfi_amdsmpl_exit(void)
+{
+	inter_module_unregister(im_name);
+}
+
+module_init(cfi_amdsmpl_init);
+module_exit(cfi_amdsmpl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Linux Networx - based on cfi_cmdset_0002.c by Crossnet Co. =
et al.");
+MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu simplified flash chips=
");
+
diff -uNr mtd/drivers/mtd/chips/Config.in mtd-amd_simplified/drivers/mtd/ch=
ips/Config.in
--- mtd/drivers/mtd/chips/Config.in	2002-09-03 07:30:43.000000000 -0600
+++ mtd-amd_simplified/drivers/mtd/chips/Config.in	2003-03-18 16:51:05.0000=
00000 -0700
@@ -44,6 +44,7 @@
 fi
 dep_tristate '  Support for Intel/Sharp flash chips' CONFIG_MTD_CFI_INTELE=
XT $CONFIG_MTD_GEN_PROBE
 dep_tristate '  Support for AMD/Fujitsu flash chips' CONFIG_MTD_CFI_AMDSTD=
 $CONFIG_MTD_GEN_PROBE
+dep_tristate '  Support for AMD Simplified flash chips' CONFIG_MTD_AMDSIMP=
LIFIED $CONFIG_MTD_GEN_PROBE
 dep_tristate '  Support for ST (Advanced Architecture) flash chips' CONFIG=
_MTD_CFI_STAA $CONFIG_MTD_GEN_PROBE
=20
 dep_tristate '  Support for RAM chips in bus mapping' CONFIG_MTD_RAM $CONF=
IG_MTD
diff -uNr mtd/drivers/mtd/chips/gen_probe.c mtd-amd_simplified/drivers/mtd/=
chips/gen_probe.c
--- mtd/drivers/mtd/chips/gen_probe.c	2003-01-31 06:35:07.000000000 -0700
+++ mtd-amd_simplified/drivers/mtd/chips/gen_probe.c	2003-03-18 16:51:05.00=
0000000 -0700
@@ -331,6 +331,10 @@
 	case 0x0002:
 		return cfi_cmdset_0002(map, primary);
 #endif
+#ifdef CONFIG_MTD_CFI_AMDSMPLFD
+	case P_ID_AMD_SIMPLIFIED:
+		return cfi_cmdset_0005(map, primary);
+#endif
 #ifdef CONFIG_MTD_CFI_STAA
         case 0x0020:
 		return cfi_cmdset_0020(map, primary);
diff -uNr mtd/drivers/mtd/chips/jedec_probe.c mtd-amd_simplified/drivers/mt=
d/chips/jedec_probe.c
--- mtd/drivers/mtd/chips/jedec_probe.c	2003-03-18 16:36:28.000000000 -0700
+++ mtd-amd_simplified/drivers/mtd/chips/jedec_probe.c	2003-03-18 16:51:05.=
000000000 -0700
@@ -746,7 +746,7 @@
 		name: "Atmel AT49BV512",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_64KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x10000,1)
 		}
@@ -756,7 +756,7 @@
 		name: "Atmel AT29LV512",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_64KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {
 			ERASEINFO(0x80,256),
@@ -934,7 +934,7 @@
 		name: "SST 39LF512",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_64KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,16),
 		}
@@ -944,7 +944,7 @@
 		name: "SST 39LF010",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_128KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,32),
 		}
@@ -954,7 +954,7 @@
 		name: "SST 39LF020",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_256KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,64),
 		}
@@ -964,7 +964,7 @@
 		name: "SST 39LF040",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_512KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,128),
 		}
@@ -974,7 +974,7 @@
 		name: "SST 39SF010A",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_128KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,32),
 		}
@@ -984,7 +984,7 @@
 		name: "SST 39SF020A",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_256KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,64),
 		}
@@ -994,7 +994,7 @@
 		name: "SST 49LF030A",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_512KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,96),
 		}
@@ -1004,7 +1004,7 @@
 		name: "SST 49LF040A",
 		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_512KiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,128),
 		}
@@ -1014,7 +1014,7 @@
 		name: "SST 49LF080A",
  		uaddr: MTD_UADDR_0x5555_0x2AAA,
 		DevSize: SIZE_1MiB,
-		CmdSet: P_ID_AMD_STD,
+		CmdSet: P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions: {ERASEINFO(0x01000,256),
 		}
@@ -1024,7 +1024,7 @@
 		name:            "PMC_Pm49FL002",
  		uaddr:           MTD_UADDR_0x5555_0x2AAA,
 		DevSize:         SIZE_256KiB,
-		CmdSet:          P_ID_AMD_STD,
+		CmdSet:          P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions:         {
 			ERASEINFO( 0x01000, 64 )
@@ -1035,7 +1035,7 @@
 		name:            "PMC_Pm49FL004",
  		uaddr:           MTD_UADDR_0x5555_0x2AAA,
 		DevSize:         SIZE_512KiB,
-		CmdSet:          P_ID_AMD_STD,
+		CmdSet:          P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions:         {
 			ERASEINFO( 0x01000, 128 )
@@ -1046,7 +1046,7 @@
 		name:            "PMC_Pm49FL008",
  		uaddr:           MTD_UADDR_0x5555_0x2AAA,
 		DevSize:         SIZE_1MiB,
-		CmdSet:          P_ID_AMD_STD,
+		CmdSet:          P_ID_AMD_SIMPLIFIED,
 		NumEraseRegions: 1,
 		regions:         {
 			ERASEINFO( 0x01000, 256 )
diff -uNr mtd/drivers/mtd/chips/Makefile mtd-amd_simplified/drivers/mtd/chi=
ps/Makefile
--- mtd/drivers/mtd/chips/Makefile	2003-02-13 14:07:31.000000000 -0700
+++ mtd-amd_simplified/drivers/mtd/chips/Makefile	2003-03-18 16:51:05.00000=
0000 -0700
@@ -22,6 +22,7 @@
 obj-$(CONFIG_MTD_AMDSTD)	+=3D amd_flash.o=20
 obj-$(CONFIG_MTD_CFI)		+=3D cfi_probe.o
 obj-$(CONFIG_MTD_CFI_STAA)	+=3D cfi_cmdset_0020.o
+obj-$(CONFIG_MTD_AMDSIMPLIFIED)	+=3D cfi_cmdset_0005.o
 obj-$(CONFIG_MTD_CFI_AMDSTD)	+=3D cfi_cmdset_0002.o
 obj-$(CONFIG_MTD_CFI_INTELEXT)	+=3D cfi_cmdset_0001.o
 obj-$(CONFIG_MTD_GEN_PROBE)	+=3D gen_probe.o
diff -uNr mtd/patches/Configure.help mtd-amd_simplified/patches/Configure.h=
elp
--- mtd/patches/Configure.help	2002-11-26 17:24:38.000000000 -0700
+++ mtd-amd_simplified/patches/Configure.help	2003-03-18 16:49:13.000000000=
 -0700
@@ -295,6 +295,20 @@
=20
   It also works on AMD compatible chips that do conform to CFI.
=20
+AMD simplified compatible flash chip support (non-CFI)
+CONFIG_MTD_AMDSIMPLIFIED
+  This option enables support for flash chips using a subset of
+  AMD commands.  These devices provide toggle and complement status
+  polling bits but do not have support for other status bits and the
+  more sophisticated functions, such as erase suspend, that those
+  chips support.
+
+  This driver is also available as a module ( =3D code which can be
+  inserted in and removed from the running kernel whenever you want).
+  If you want to compile it as a module, say M here and read
+  <file:Documentation/modules.txt>. The module will be called
+  amd_flash.o
+
 Support for RAM chips in bus mapping
 CONFIG_MTD_RAM
   This option enables basic support for RAM chips accessed through=20

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DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Steve Wahl]

On Tue, Mar 18, 2003 at 05:23:43PM -0700, Thayne Harbaugh wrote:
>   It likely could be simplified even more - take out feeble support for
> interleaved chips (which I don't have and can't test and I'm not even
> sure that the chips that work this way support interleaving).

Interleaved operation is probably always supported, because the chips
don't "know" they're doing it.

Unless I'm completely mistaken, interleaving is simply having N chips
with a data bus width of W on a bus that's N * W wide.  For instance,
I once worked on a product with a processor that didn't do anything
smaller than a 32 bit bus, so the flash area of memory was populated
with 4 chips (each 8 bits wide).

For these, you generally issue the commands to all chips at one time,
in this case writing 32 bit words with the command bytes replicated in
each byte of the word.  Makes the polling a little complicated,
perhaps, because you have to watch for all chips to reach a finished
state before you continue.

Still thinking about the rest of what you wrote.  My initial thoughts
are this shouldn't really need a whole separate command set file.

--> Steve

DQ5 & DQ6 in chips/cfi_cmdset_0002.c (Dairy Queen 5 warning)

[Thayne Harbaugh]

--=-kZtkePRDB816W7SZVvFx
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On Wed, 2003-03-19 at 08:56, Steve Wahl wrote:

> Still thinking about the rest of what you wrote.  My initial thoughts
> are this shouldn't really need a whole separate command set file.

Yeah, I don't like making a new driver either.  The concerns are knowing
_not_ to check DQ5 and other status bits as well as knowing that a
device does not support suspend/resume.  That could be described in
another field of the jedec_table[] - unless we can come up with a
_reliable_ way of probing that functionality.

I'm still thinking, too.  I just wanted a starting point - sometimes
it's hard to get going without some sample code.

> --> Steve
>=20
>=20
>=20
>=20
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--=20
Thayne Harbaugh
Linux Networx

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