[PATCH] OneNAND MTD support

[PATCH] OneNAND MTD support

[Kyungmin Park]

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Hi

We are happy to release OneNAND MTD to open source community.

Brief desciption of OneNAND is following 

Samsung OneNANDT is a highly reliable embedded memory targeted for both
consumer electronic, and next generation mobile phone market. With Samsung's
accumulated NAND flash technologies over the last decade, Samsung designs an
ideal single memory chip based on NAND architecture integrating SRAM buffers
and logic interface.
Samsung OneNANDT takes both advantages from high-speed data read function of
NOR flash and the advanced data storage function of NAND flash. 
(from
http://www.samsung.com/Products/Semiconductor/Flash/OneNAND_TM/index.htm)

This patch is based on latest linux 2.6 kernel from linux-omap-2.6.git

It's simple implementation.
So there's no optimization and performance tuning.
It is useful to test OneNAND chip with new platform and verify hardware
configurations.

Now it's tested with CRAMFS and JFFS2 on OMAP OSK

Note: The bad block handling is not yet implemented.
since we want to use NAND BBT routine and NAND BBT routine has NAND-specific
code, then 
At first we want to split BBT code into BBT core and NAND-specific code then
we will merge with OneNAND

Any comments are welcome.

Thank you.

Kyungmin Park

[-- Attachment #2: onenand-mtd.patch --]
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Index: drivers/mtd/onenand/Kconfig
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Kconfig  (mode:100644)
@@ -0,0 +1,36 @@
+#
+# linux/drivers/mtd/onenand/Kconfig
+#
+
+menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
+	depends on MTD != n && EXPERIMENTAL
+
+config MTD_ONENAND
+	tristate "OneNAND Device Support"
+	depends on MTD
+	select MTD_ONENAND_INFO
+	help
+	  This enables support for accessing all type of OneNAND flash
+	  devices. For further information see
+	  <http://www.samsung.com/Products/Semiconductor/Flash/OneNAND_TM/index.htm>.
+
+config MTD_ONENAND_VERIFY_WRITE
+	bool "Verify OneNAND page writes"
+	depends on MTD_ONENAND
+	help
+	  This adds an extra check when data is written to the flash. The
+	  OneNAND flash device internally checks only bits transitioning
+	  from 1 to 0. There is a rare possibility that even though the
+	  device thinks the write was successful, a bit could have been
+	  flipped accidentaly due to device wear or something else.
+
+config MTD_ONENAND_INFO
+	tristate
+
+config MTD_ONENAND_OMAP
+	tristate "OneNAND Flash device on OMAP board"
+	depends on ARM && ARCH_OMAP && MTD_ONENAND
+	help
+	  Support for OneNAND flash on TI OMAP board.
+
+endmenu
Index: drivers/mtd/onenand/Makefile
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Makefile  (mode:100644)
@@ -0,0 +1,8 @@
+#
+# linux/drivers/mtd/onenand/Makefile
+#
+
+obj-$(CONFIG_MTD_ONENAND)		+= onenand_base.o
+obj-$(CONFIG_MTD_ONENAND_INFO)		+= onenand_info.o
+
+obj-$(CONFIG_MTD_ONENAND_OMAP)		+= omap-onenand.o
Index: drivers/mtd/onenand/omap-onenand.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/omap-onenand.c  (mode:100644)
@@ -0,0 +1,196 @@
+/*
+ *  linux/drivers/mtd/onenand/omap-onenand.c
+ *
+ *  Copyright (c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Derived from linux/drivers/mtd/nand/omap-nand-flash.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Overview:
+ *   This is a device driver for the OneNAND flash device for TI OMAP boards.
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/tc.h>
+#include <asm/sizes.h>
+
+#define OMAP_ONENAND_FLASH_START1	OMAP_CS2A_PHYS
+#define OMAP_ONENAND_FLASH_START2	OMAP_CS1B_PHYS
+/*
+ * MTD structure for OMAP board
+ */
+static struct mtd_info *omap_onenand_mtd = NULL;
+
+static void __iomem *omap_onenand_flash_base;
+
+/*
+ * Define partitions for flash devices
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition static_partition[] = {
+	{
+		.name		= "X-Loader + U-Boot",
+		.offset		= 0,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "U-Boot Environment",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= 2 * SZ_1M
+	},
+	{
+		.name		= "filesystem0",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_16M,
+	},
+	{
+		.name		= "filesystem1",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= MTDPART_SIZ_FULL,
+	},
+};
+
+const char *part_probes[] = { "cmdlinepart", NULL,  };
+
+#endif
+
+/* Scan to find existance of the device at omap_onenand_flash_base.
+   This also allocates oob and data internal buffers */
+static int __init probe_onenand_chip(void)
+{
+        struct onenand_chip *this;
+
+        this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
+       
+	/* Initialize structures */
+        memset((char *) this, 0, sizeof(struct onenand_chip));
+        
+	this->base = omap_onenand_flash_base;
+
+        if (onenand_scan(omap_onenand_mtd, 1))
+		return -ENXIO;
+
+	return 0;
+}
+
+static char onenand_name[] = "onenand";
+
+/*
+ * Main initialization routine
+ */
+static int __init omap_onenand_init (void)
+{
+	struct onenand_chip *this;
+	struct mtd_partition *dynamic_partition = 0;
+	int err = 0;
+
+	/* Allocate memory for MTD device structure and private data */
+	omap_onenand_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct onenand_chip),
+				GFP_KERNEL);
+	if (!omap_onenand_mtd) {
+		printk (KERN_WARNING "Unable to allocate OneNAND MTD device structure.\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	/* Get pointer to private data */
+	this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *) omap_onenand_mtd, 0, sizeof(struct mtd_info) + sizeof(struct onenand_chip));
+
+	/* Link the private data with the MTD structure */
+	omap_onenand_mtd->priv = this;
+
+        /* try the first address */
+	omap_onenand_flash_base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
+	omap_onenand_mtd->name = onenand_name;
+	if (probe_onenand_chip()){
+		/* try the second address */
+		iounmap(omap_onenand_flash_base);
+		omap_onenand_flash_base = ioremap(OMAP_ONENAND_FLASH_START2, SZ_128K);
+		if (probe_onenand_chip()){
+			iounmap(omap_onenand_flash_base);
+                        err = -ENXIO;
+                        goto out_mtd;
+		}
+	}
+
+	/* Register the partitions */
+	switch (omap_onenand_mtd->size) {
+	case SZ_128M:
+	case SZ_64M:
+	case SZ_32M:
+#ifdef CONFIG_MTD_PARTITIONS
+		err = parse_mtd_partitions(omap_onenand_mtd, part_probes,
+					&dynamic_partition, 0);
+		if (err > 0)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					dynamic_partition, err);
+		else if (1)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					static_partition,
+					ARRAY_SIZE(static_partition));
+		else
+#endif
+			err = add_mtd_device(omap_onenand_mtd);
+		if (err)
+			goto out_buf;
+		break;
+
+	default:
+		printk(KERN_WARNING "Unsupported OneNAND device\n");
+		err = -ENXIO;
+		goto out_buf;
+	}
+
+	goto out;
+
+out_buf:
+	onenand_release(omap_onenand_mtd);
+	iounmap(omap_onenand_flash_base);
+out_mtd:
+	kfree(omap_onenand_mtd);
+out:
+	return err;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit omap_onenand_cleanup (void)
+{
+	/* onenand_release frees MTD partitions, MTD structure
+	   and onenand internal buffers */
+	onenand_release(omap_onenand_mtd);
+	iounmap(omap_onenand_flash_base);
+	kfree(omap_onenand_mtd);
+}
+
+module_init(omap_onenand_init);
+module_exit(omap_onenand_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP boards");
Index: drivers/mtd/onenand/onenand_base.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/onenand_base.c  (mode:100644)
@@ -0,0 +1,1310 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_base.c
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+/**
+ * onenand_oob_64 - oob info for large (2KB) page
+ */
+static struct nand_oobinfo onenand_oob_64 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 20,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		40, 41, 42, 43, 44,
+		56, 57, 58, 59, 60,
+		},
+	.oobfree	= {
+		{2, 3}, {14, 2}, {18, 3}, {30, 2},
+		{24, 3}, {46, 2}, {40, 3}, {62, 2} }
+};
+
+/**
+ * onenand_oob_32 - oob info for middle (1KB) page
+ */
+static struct nand_oobinfo onenand_oob_32 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 10,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		},
+	.oobfree	= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
+};
+
+static const unsigned char ffchars[] = {
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 16 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 32 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 48 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 64 */
+};
+
+/**
+ * onenand_block_address - [DEFAULT] Get block address
+ * @param device	the device id
+ * @param block		the block
+ * @return		translated block address if DDP, otherwise same
+ *
+ * Setup Start Address 1 Register (F100h)
+ */
+static int onenand_block_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device Flash Core select, NAND Flash Block Address */
+		int dfs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dfs = 1;
+
+		return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1));
+	}
+
+	return block;
+}
+
+/**
+ * onenand_bufferram_address - [DEFAULT] Get bufferram address
+ * @param device	the device id
+ * @param block		the block
+ * @return		set DBS value if DDP, otherwise 0
+ *
+ * Setup Start Address 2 Register (F101h) for DDP
+ */
+static int onenand_bufferram_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device BufferRAM Select */
+		int dbs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dbs = 1;
+
+		return (dbs << ONENAND_DDP_SHIFT);
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_page_address - [DEFAULT] Get page address
+ * @param page		the page address
+ * @param sector	the sector address
+ * @return		combined page and sector address
+ *
+ * Setup Start Address 8 Register (F107h)
+ */
+static int onenand_page_address(int page, int sector)
+{
+	/* Flash Page Address, Flash Sector Address */
+	int fpa, fsa;
+
+	fpa = page & ONENAND_FPA_MASK;
+	fsa = sector & ONENAND_FSA_MASK;
+
+	return ((fpa << ONENAND_FPA_SHIFT) | fsa);
+}
+
+/**
+ * onenand_buffer_address - [DEFAULT] Get buffer address
+ * @param dataram1	DataRAM index
+ * @param sectors	the sector address
+ * @param count		the number of sectors
+ * @return		the start buffer value
+ *
+ * Setup Start Buffer Register (F200h)
+ */
+static int onenand_buffer_address(int dataram1, int sectors, int count)
+{
+	int bsa, bsc;
+
+	/* BufferRAM Sector Address */
+	bsa = sectors & ONENAND_BSA_MASK;
+
+	if (dataram1)
+		bsa |= ONENAND_BSA_DATARAM1;	/* DataRAM1 */
+	else
+		bsa |= ONENAND_BSA_DATARAM0;	/* DataRAM0 */
+
+	/* BufferRAM Sector Count */
+	bsc = count & ONENAND_BSC_MASK;
+
+	return ((bsa << ONENAND_BSA_SHIFT) | bsc);
+}
+
+/**
+ * onenand_command - [DEFAULT] Send command to OneNAND device
+ * @param mtd		MTD device structure
+ * @param cmd		the command to be sent
+ * @param addr		offset to read from or write to
+ * @param len		number of bytes to read or write
+ *
+ * Send command to OneNAND device. This function is used for middle/large page
+ * devices (1KB/2KB Bytes per page)
+ */
+static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int value, readcmd = 0;
+	int block, page;
+	/* Now we use page size operation */
+	int sectors = 4, count = 4;
+
+	/* Address translation */
+	switch (cmd) {
+	case ONENAND_CMD_UNLOCK:
+	case ONENAND_CMD_LOCK:
+	case ONENAND_CMD_LOCK_TIGHT:
+		block = -1;
+		page = -1;
+		break;
+
+	case ONENAND_CMD_ERASE:
+	case ONENAND_CMD_BUFFERRAM:
+		block = (int) (addr >> this->erase_shift);
+		page = -1;
+		break;
+
+	default:
+		block = (int) (addr >> this->erase_shift);
+		page = (int) (addr >> this->page_shift);
+		page &= this->page_mask;
+		break;
+	}
+
+	/* NOTE: The setting order of the registers is very important! */
+	if (cmd == ONENAND_CMD_BUFFERRAM) {
+		/* Select DataRAM for DDP */
+		value = onenand_bufferram_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS2);
+
+		/* Switch to the next data buffer */
+		ONENAND_SET_NEXT_BUFFERRAM(this);
+
+		return 0;
+	}
+
+	if (block != -1) {
+		/* Write 'DFS, FBA' of Flash */
+		value = onenand_block_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS1);
+	}
+
+	if (page != -1) {
+		int dataram;
+
+		switch (cmd) {
+		case ONENAND_CMD_READ:
+		case ONENAND_CMD_READOOB:
+			dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+			readcmd = 1;
+			break;
+
+		default:
+			dataram = ONENAND_CURRENT_BUFFERRAM(this);
+			break;
+		}
+
+		/* Write 'FPA, FSA' of Flash */
+		value = onenand_page_address(page, sectors);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS8);
+
+		/* Write 'BSA, BSC' of DataRAM */
+		value = onenand_buffer_address(dataram, sectors, count);
+		onenand_writew(value, this->base + ONENAND_REG_START_BUFFER);
+			
+		if (readcmd) {
+			/* Select DataRAM for DDP */
+			value = onenand_bufferram_address(this->device_id, block);
+			onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS2);
+		}
+	}
+
+	/* Interrupt clear */
+	onenand_writew(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
+
+	/* Write command */
+	onenand_writew(cmd, this->base + ONENAND_REG_COMMAND);
+
+	return 0;
+}
+
+/**
+ * onenand_wait - [DEFAULT] wait until the command is done
+ * @param mtd		MTD device structure
+ * @param state		state to select the max. timeout value
+ *
+ * Wait for command done. This applies to all OneNAND command
+ * Read can take up to 30us, erase up to 2ms and program up to 350us
+ * according to general OneNAND specs
+ */
+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+	struct onenand_chip * this = mtd->priv;
+	unsigned long timeout;
+	unsigned int flags = ONENAND_INT_MASTER;
+	unsigned int interrupt = 0;
+	unsigned int ctrl, ecc;
+
+	/* The 10 msec is enough */
+	timeout = jiffies + msecs_to_jiffies(10);
+	while (time_before(jiffies, timeout)) {
+		interrupt = onenand_readw(this->base + ONENAND_REG_INTERRUPT);
+
+		if (interrupt & flags)
+			break;
+		yield();
+	}
+	/* To get correct interrupt status in timeout case */
+	interrupt = onenand_readw(this->base + ONENAND_REG_INTERRUPT);
+
+	if (!interrupt)
+		BUG();
+
+	ctrl = onenand_readw(this->base + ONENAND_REG_CTRL_STATUS);
+
+	if (ctrl & ONENAND_CTRL_ERROR) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (ctrl & ONENAND_CTRL_LOCK) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (interrupt & ONENAND_INT_READ) {
+		ecc = onenand_readw(this->base + ONENAND_REG_ECC_STATUS);
+		if (ecc & ONENAND_ECC_2BIT_ALL) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x", ecc);
+			return -EBADMSG;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_dataram - [OneNAND Interface] Read/write the dataram area
+ * @param mtd		MTD data stru
+ * @param write		write operation if given
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Read/write the dataram area
+ */
+static int onenand_dataram(struct mtd_info *mtd, int write,
+		unsigned char *buffer, int offset, int count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *src, *dest;
+	void __iomem *dataram;
+
+	dataram = this->base + ONENAND_DATARAM;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this))
+		dataram += mtd->oobblock;
+
+	if (write) {
+		src = buffer;
+		dest = dataram + offset;
+	} else {
+		src = dataram + offset;
+		dest = buffer;
+	}
+
+	memcpy(dest, src, count);
+
+	return 0;
+}
+
+/**
+ * onenand_spareram - [OneNAND Interface] Read/write the spareram area
+ * @param mtd		MTD data stru
+ * @param write		write operation if given
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Read/write the spareram area
+ */
+static int onenand_spareram(struct mtd_info *mtd, int write,
+		unsigned char *buffer,  int offset, int count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *src, *dest;
+	void __iomem *spareram;
+
+	spareram = this->base + ONENAND_SPARERAM;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this))
+		spareram += mtd->oobsize;
+
+	if (write) {
+		src = buffer;
+		dest = spareram + offset;
+	} else {
+		src = spareram + offset;
+		dest = buffer;
+	}
+
+	memcpy(dest, src, count);
+
+	return 0;
+}
+
+
+/**
+ * onenand_get_device - [GENERIC] Get chip for selected access
+ * @param this		the onenand chip descriptor
+ * @param new_state	the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+static void onenand_get_device(struct onenand_chip *this, int new_state)
+{
+	struct onenand_chip *active = this;
+	DECLARE_WAITQUEUE(wait, current);
+
+	/*
+	 * Grab the lock and see if the device is available
+	 */
+retry:
+	if (active == this) {
+		spin_lock(&this->chip_lock);
+		if (this->state == FL_READY) {
+			this->state = new_state;
+			spin_unlock(&this->chip_lock);
+			return;
+		}
+	}
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	add_wait_queue(&active->wq, &wait);
+	spin_unlock(&active->chip_lock);
+	schedule();
+	remove_wait_queue(&active->wq, &wait);
+	goto retry;
+}
+
+/**
+ * onenand_release_device - [GENERIC] release chip
+ * @param mtd		MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+static void onenand_release_device(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	/* Release the chip */
+	spin_lock(&this->chip_lock);
+	this->state = FL_READY;
+	wake_up(&this->wq);
+	spin_unlock(&this->chip_lock);
+}
+
+/**
+ * onenand_read_ecc - [MTD Interface] Read data with ECC
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ * @param oob_buf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND read with ECC
+ */
+static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf,
+	u_char *oob_buf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, column;
+	int thislen;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Do not allow reads past end of device */
+	if ((from + len) > mtd->size) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: Attempt read beyond end of device\n");
+		*retlen = 0;
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_READING);
+
+	/* TODO handling oob */
+
+	while (read < len) {
+		thislen = min_t(int, mtd->oobblock, len - read);
+
+		column = from & (mtd->oobblock - 1);
+		if (column + thislen > mtd->oobblock)
+			thislen = mtd->oobblock - column;
+
+		this->command(mtd, ONENAND_CMD_READ, from, mtd->oobblock);
+
+		ret = this->wait(mtd, FL_READING);
+		/* First copy data and check return value for ECC handling */
+
+		this->dataram(mtd, ONENAND_READ, buf, column, thislen);
+
+		read += thislen;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: read failed = %d\n", ret);
+			goto out;
+		}
+
+		if (read == len)
+			break;
+
+		from += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	/*
+	 * Return success, if no ECC failures, else -EBADMSG
+	 * fs driver will take care of that, because
+	 * retlen == desired len and result == -EBADMSG
+	 */
+	*retlen = read;
+	return ret;
+}
+
+/**
+ * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
+*/
+static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * OneNAND read out-of-band data from the spare area
+ */
+static int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, thislen, column;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Initialize return length value */
+	*retlen = 0;
+
+	/* Do not allow reads past end of device */
+	if (unlikely((from + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_READING);
+
+	column = from & (mtd->oobblock - 1);
+
+	while (read < len) {
+		thislen = mtd->oobsize - column;
+		thislen = min_t(int, thislen, len);
+
+		this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+
+		ret = this->wait(mtd, FL_READING);
+		/* First copy data and check return value for ECC handling */
+
+		this->spareram(mtd, ONENAND_READ, buf, column, thislen);
+
+		read += thislen;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = %d\n", ret);
+			goto out;
+		}
+
+		buf += thislen;
+
+		/* Read more? */
+		if (read < len) {
+			/* Page size */
+			from += mtd->oobblock;
+			column = 0;
+		}
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = read;
+	return ret;
+}
+
+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd		MTD device structure
+ * @param buf		the databuffer to verify
+ * @param block		block address
+ * @param page		page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char *buf,
+	loff_t addr, int block, int page)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *dataram0, *dataram1;
+	int ret = 0;
+
+	this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock);
+
+	ret = this->wait(mtd, FL_READING);
+	if (ret)
+		return ret;
+
+	/* Check, if the two dataram areas are same */
+	dataram0 = this->base + ONENAND_DATARAM;
+	dataram1 = dataram0 + mtd->oobblock;
+
+	if (memcmp(dataram0, dataram1, mtd->oobblock))
+		return -EBADMSG;
+	
+	return 0;
+}
+#else
+#define onenand_verify_page(...)	(0)
+#endif
+
+#define NOTALIGNED(x)	((x & (mtd->oobblock - 1)) != 0)
+
+/**
+ * onenand_write_ecc - [MTD Interface] OneNAND write with ECC
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with ECC
+ */
+static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int written = 0;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobblock, len - written);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->dataram(mtd, ONENAND_WRITE, (u_char *) buf, 0, thislen);
+		this->spareram(mtd, ONENAND_WRITE, (u_char *) ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: write filaed %d\n", ret);
+			goto out;
+		}
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		written += thislen;
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return ret;
+}
+
+/**
+ * onenand_write - [MTD Interface] compability function for onenand_write_ecc
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * This function simply calls onenand_write_ecc
+ * with oob buffer and oobsel = NULL
+ */
+static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * OneNAND write out-of-band
+ */
+static int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int column, status;
+	int written = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobsize, len - written);
+
+		column = to & (mtd->oobsize - 1);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
+
+		this->spareram(mtd, ONENAND_WRITE, (u_char *) ffchars, 0, mtd->oobsize);
+		this->spareram(mtd, ONENAND_WRITE, (u_char *) buf, column, thislen);
+
+		this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+
+		status = this->wait(mtd, FL_WRITING);
+		if (status)
+			goto out;
+
+		written += thislen;
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return 0;
+}
+
+/**
+ * onenand_writev_ecc - [MTD Interface] write with iovec with ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with iovec with ecc
+ */
+static int onenand_writev_ecc(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned char buffer[mtd->oobblock], *pbuf;
+	size_t total_len, len;
+	int i, written = 0;
+	int ret = 0;
+
+	/* Preset written len for early exit */
+	*retlen = 0;
+
+	/* Calculate total length of data */
+	total_len = 0;
+	for (i = 0; i < count; i++)
+		total_len += vecs[i].iov_len;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_writev_ecc: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
+
+	/* Do not allow write past end of the device */
+	if (unlikely((to + total_len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempted write past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(total_len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_WRITING);
+
+	/* TODO handling oob */
+	
+	/* Loop until all keve's data has been written */
+	len = 0;
+	while (count) {
+		pbuf = buffer;
+		/* 
+		 * If the given tuple is >= pagesize then
+		 * write it out from the iov
+		 */
+		if ((vecs->iov_len - len) >= mtd->oobblock) {
+			pbuf = vecs->iov_base + len;
+
+			len += mtd->oobblock;
+
+			/* Check, if we have to switch to the next tuple */
+			if (len >= (int) vecs->iov_len) {
+				vecs++;
+				len = 0;
+				count--;
+			}
+		} else {
+			int cnt = 0, thislen;
+			while (cnt < mtd->oobblock) {
+				thislen = min_t(int, mtd->oobblock - cnt, vecs->iov_len - len);
+				memcpy(buffer + cnt, vecs->iov_base + len, thislen);
+				cnt += thislen;
+				len += thislen;
+
+				/* Check, if we have to switch to the next tuple */
+				if (len >= (int) vecs->iov_len) {
+					vecs++;
+					len = 0;
+					count--;
+				}
+			}
+		}
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->dataram(mtd, ONENAND_WRITE, pbuf, 0, mtd->oobblock);
+		this->spareram(mtd, ONENAND_WRITE, (u_char *) ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: write failed %d\n", ret);
+			goto out;
+		}
+
+		/* TODO */
+		ret = onenand_verify_page(mtd, (u_char *) pbuf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		written += mtd->oobblock;
+
+		to += mtd->oobblock;
+	}
+
+out:
+	/* Deselect and wakt up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+
+	return 0;
+}
+
+/**
+ * onenand_writev - [MTD Interface] compabilty function for onenand_writev_ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ *
+ * OneNAND write with kvec. This just calls the ecc function
+ */
+static int onenand_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen)
+{
+	return onenand_writev_ecc(mtd, vecs, count, to, retlen, NULL, NULL);
+}
+
+/**
+ * onenand_erase - [MTD Interface] erase block(s)
+ * @param mtd		MTD device structure
+ * @param instr		erase instruction
+ *
+ * Erase one ore more blocks
+ */
+static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned int block_size;
+	loff_t addr;
+	int len;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
+
+	block_size = (1 << this->erase_shift);
+
+	/* Start address must align on block boundary */
+	if (unlikely(instr->addr & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n");
+		return -EINVAL;
+	}
+
+	/* Length must align on block boundary */
+	if (unlikely(instr->len & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n");
+		return -EINVAL;
+	}
+
+	/* Do not allow erase past end of device */
+	if (unlikely((instr->len + instr->addr) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n");
+		return -EINVAL;
+	}
+
+	instr->fail_addr = 0xffffffff;
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_ERASING);
+
+	/* Loop throught the pages */
+	len = instr->len;
+	addr = instr->addr;
+
+	instr->state = MTD_ERASING;
+
+	while (len) {
+
+		/* TODO Check badblock */
+
+		this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
+
+		ret = this->wait(mtd, FL_ERASING);
+		/* Check, if it is write protected */
+		if (ret) {
+			if (ret == -EPERM)
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Device is write protected!!!\n");
+			else
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", block);
+			instr->state = MTD_ERASE_FAILED;
+			instr->fail_addr = addr;
+			goto erase_exit;
+		}
+
+		len -= block_size;
+		addr += block_size;
+	}
+
+	instr->state = MTD_ERASE_DONE;
+
+erase_exit:
+
+	ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+	/* Do call back function */
+	if (!ret)
+		mtd_erase_callback(instr);
+
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	return ret;
+}
+
+/**
+ * onenand_sync - [MTD Interface] sync
+ * @param mtd		MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+static void onenand_sync(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(this, FL_SYNCING);
+
+	/* Release it and go back */
+	onenand_release_device(mtd);
+}
+
+/**
+ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/*
+	 * TODO 
+	 * 1. Bad block table (BBT)
+	 *   -> using NAND BBT to support JFFS2
+	 * 2. Bad block management (BBM)
+	 *   -> bad block replace scheme
+	 *
+	 * Currently we do nothing
+	 */
+	return 0;
+}
+
+/**
+ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/* see above */
+	return 0;
+}
+
+/**
+ * onenand_unlock - [MTD Interface] Unlock block(s)
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ * @param len		number of bytes to unlock
+ *
+ * Unlock one or more blocks
+ */
+static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int start, end, block, value, status;
+
+	start = ofs >> this->erase_shift;
+	end = len >> this->erase_shift;
+
+	/* Continuous lock scheme */
+	if (this->options & ONENAND_CONT_LOCK) {
+		/* Set start block address */
+		onenand_writew(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Set end block address */
+		onenand_writew(end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (onenand_readw(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Check lock status */
+		status = onenand_readw(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "wp status = 0x%x\n", status);
+
+		return 0;
+	}
+
+	/* Block lock scheme */
+	for (block = start; block < end; block++) {
+		/* Set start block address */
+		onenand_writew(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (onenand_readw(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Set block address for read block status */
+		value = onenand_block_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS1);
+
+		/* Check lock status */
+		status = onenand_readw(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
+	}
+	
+	return 0;
+}
+
+
+/**
+ * onenand_scan - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd		MTD device structure
+ *
+ * OneNAND detection method:
+ *   Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	int bram_maf_id, bram_dev_id, maf_id, dev_id;
+	int density;
+
+	/* Send the command for reading device ID from BootRAM */
+	onenand_writew(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from BootRAM */
+	bram_maf_id = onenand_readw(this->base + ONENAND_BOOTRAM + 0x0);
+	bram_dev_id = onenand_readw(this->base + ONENAND_BOOTRAM + 0x2);
+
+	/* Chech empty address */
+	if (bram_maf_id == bram_dev_id)
+		return -ENXIO;
+
+	/* Reset OneNAND to read default register values */
+	onenand_writew(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from Register */
+	maf_id = onenand_readw(this->base + ONENAND_REG_MANUFACTURER_ID);
+	dev_id = onenand_readw(this->base + ONENAND_REG_DEVICE_ID);
+
+	/* Check OneNAND device */
+	if (maf_id != bram_maf_id || dev_id != bram_dev_id)
+		return -ENXIO;
+
+	/* Manufacturer ID */
+	onenand_print_maf_info(maf_id);
+	/* Flash device information */
+	onenand_print_device_info(dev_id);
+	this->device_id = dev_id;
+
+	density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+	this->chipsize = (16 << density) << 20;
+
+	/* OneNAND page size & block size */
+	/* The data buffer size is equal to page size */
+	mtd->oobblock = onenand_readw(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+	mtd->oobsize = mtd->oobblock >> 5;
+	/* Pagers per block is always 64 in OneNAND */
+	mtd->erasesize = mtd->oobblock << 6;
+
+	this->erase_shift = ffs(mtd->erasesize) - 1;
+	this->page_shift = ffs(mtd->oobblock) - 1;
+	this->ppb_shift = (this->erase_shift - this->page_shift);
+	this->page_mask = (mtd->erasesize / mtd->oobblock) - 1;
+
+	/* TODO: Multichip handling */
+
+	mtd->size = this->chipsize;
+
+	/* Version ID */
+	this->version_id = onenand_readw(this->base + ONENAND_REG_VERSION_ID);
+	printk(KERN_DEBUG "OneNAND version = 0x%04x\n", this->version_id);
+
+	/* Lock scheme */
+	if (density <= ONENAND_DEVICE_DENSITY_512Mb &&
+	    !(this->version_id >> ONENAND_VERSION_PROCESS_SHIFT)) {
+		printk(KERN_INFO "Lock scheme is Continues Lock\n");
+		this->options |= ONENAND_CONT_LOCK;
+	}
+	
+	return 0;
+}
+
+
+/**
+ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
+ * @param mtd		MTD device structure
+ * @param maxchips	Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values.
+ */
+int onenand_scan(struct mtd_info *mtd, int maxchips)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (!this->command)
+		this->command = onenand_command;
+	if (!this->wait)
+		this->wait = onenand_wait;
+
+	if (!this->dataram)
+		this->dataram = onenand_dataram;
+	if (!this->spareram)
+		this->spareram = onenand_spareram;
+
+	if (onenand_probe(mtd))
+		return -ENXIO;
+
+	this->state = FL_READY;
+	init_waitqueue_head(&this->wq);
+	spin_lock_init(&this->chip_lock);
+
+	switch (mtd->oobsize) {
+	case 64:
+		this->autooob = &onenand_oob_64;
+		break;
+
+	case 32:
+		this->autooob = &onenand_oob_32;
+		break;
+
+	default:
+		printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
+			mtd->oobsize);
+		break;
+	}
+
+	memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
+	
+	/* Fill in remaining MTD driver data */
+	mtd->type = MTD_NANDFLASH;
+	mtd->flags = MTD_CAP_NANDFLASH;
+	mtd->ecctype = MTD_ECC_SW;
+	mtd->erase = onenand_erase;
+	mtd->point = NULL;
+	mtd->unpoint = NULL;
+	mtd->read = onenand_read;
+	mtd->write = onenand_write;
+	mtd->read_ecc = onenand_read_ecc;
+	mtd->write_ecc = onenand_write_ecc;
+	mtd->read_oob = onenand_read_oob;
+	mtd->write_oob = onenand_write_oob;
+	mtd->readv = NULL;
+	mtd->writev = onenand_writev;
+	mtd->writev_ecc = onenand_writev_ecc;
+	mtd->sync = onenand_sync;
+	mtd->lock = NULL;
+	mtd->unlock = onenand_unlock;
+	mtd->suspend = NULL;
+	mtd->resume = NULL;
+	mtd->block_isbad = onenand_block_isbad;
+	mtd->block_markbad = onenand_block_markbad;
+	mtd->owner = THIS_MODULE;
+
+	/* Unlock whole block */
+	mtd->unlock(mtd, 0x0, this->chipsize);
+
+	return 0;
+}
+
+/**
+ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
+ * @param mtd		MTD device structure
+ */
+void onenand_release(struct mtd_info *mtd)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+	/* Deregister partitions */
+	del_mtd_partitions (mtd);
+#endif
+	/* Deregister the device */
+	del_mtd_device (mtd);
+}
+
+EXPORT_SYMBOL(onenand_scan);
+EXPORT_SYMBOL(onenand_release);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Generic OneNAND flash driver code");
Index: drivers/mtd/onenand/onenand_info.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/onenand_info.c  (mode:100644)
@@ -0,0 +1,53 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_info.c
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/mtd/onenand.h>
+
+void onenand_print_device_info(int device)
+{
+	int vcc, demuxed, ddp, density;
+
+	vcc = device & ONENAND_DEVICE_VCC_MASK;
+	demuxed = device & ONENAND_DEVICE_IS_DEMUX;
+	ddp = device & ONENAND_DEVICE_IS_DDP;
+	density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+	printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
+		demuxed ? "" : "Muxed ",
+		ddp ? "(DDP)" : "",
+		(16 << density),
+		vcc ? "2.65/3.3" : "1.8",
+		device);
+}
+
+static const struct onenand_manufacturers onenand_manuf_ids[] = {
+	{ONENAND_MFR_SAMSUNG, "Samsung"},
+	{ONENAND_MFR_UNKNOWN, "Unknown"}
+};
+
+void onenand_print_maf_info(int manuf)
+{
+	int i;
+
+	for (i = 0; onenand_manuf_ids[i].id; i++) {
+		if (manuf == onenand_manuf_ids[i].id)
+			break;
+	}
+
+	printk(KERN_DEBUG "OneNAND Manufacturer: %s\n",
+		onenand_manuf_ids[i].name);
+}
+
+EXPORT_SYMBOL_GPL(onenand_print_device_info);
+EXPORT_SYMBOL_GPL(onenand_print_maf_info);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Display OneNAND device and manufacturer ID's");
Index: include/linux/mtd/onenand.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand.h  (mode:100644)
@@ -0,0 +1,132 @@
+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand_regs.h>
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan(struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release(struct mtd_info *mtd);
+
+/* OneNADA read / write value */
+enum {
+	ONENAND_READ = 0,
+	ONENAND_WRITE,
+};
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_UNLOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param bufferam	[INTERN] BufferRAM index
+ * @param command	[REPLACEABLE] hardwarespecific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardwarespecific function for wait on ready
+ * @param dataram	[REPLACEABLE] hardwarespecific function for Data Area
+ * @param spareram	[REPLACEABLE] hardwarespecific function for Spare Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem		*base;
+	unsigned int		chipsize;
+	unsigned int		device_id;
+	unsigned int		version_id;
+	unsigned int		options;
+
+	unsigned int		erase_shift;
+	unsigned int		page_shift;
+	unsigned int		ppb_shift;	/* Pages per block shift */
+	unsigned int		page_mask;
+
+	unsigned int		bufferram;
+
+	int (*command)(struct mtd_info *mtd, int cmd, loff_t address, size_t len);
+	int (*wait)(struct mtd_info *mtd, int state);
+	int (*dataram)(struct mtd_info *mtd, int write, unsigned char *buffer,
+			int offset, int count);
+	int (*spareram)(struct mtd_info *mtd, int write, unsigned char *buffer,
+			int offset, int count);
+
+	spinlock_t		chip_lock;
+	wait_queue_head_t	wq;
+	onenand_state_t		state;
+
+	struct nand_oobinfo	*autooob;
+
+	void			*priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram ^= 1)
+
+/*
+ * Functions to access the OneNAND IO region
+ */
+#define onenand_readw(a)		readw(a)
+#define onenand_writew(v,a)		writew(v, a)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK		(0x0001)
+
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG	0xec
+#define ONENAND_MFR_UNKNOWN	0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+        int id;
+        char *name;
+};
+
+extern void onenand_print_device_info(int device_id);
+extern void onenand_print_maf_info(int manuf_id);
+
+#endif	/* __LINUX_MTD_ONENAND_H */
Index: include/linux/mtd/onenand_regs.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand_regs.h  (mode:100644)
@@ -0,0 +1,167 @@
+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x3f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL		(1 << 12)
+#define ONENAND_SYS_CFG1_BL		(1 << 9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+
+#endif	/* __ONENAND_REG_H */

Re: [PATCH] OneNAND MTD support

[Thomas Gleixner]

On Mon, 2005-07-04 at 10:19 +0900, Kyungmin Park wrote:

> This patch is based on latest linux 2.6 kernel from linux-omap-2.6.git

Please provide a patch against MTD-CVS

> Note: The bad block handling is not yet implemented.
> since we want to use NAND BBT routine and NAND BBT routine has NAND-specific
> code, then 
> At first we want to split BBT code into BBT core and NAND-specific code then
> we will merge with OneNAND

Makes sense.

tglx

Some remarks:

Kconfig and Makefile need references in drivers/mtd/Kconfig and
drivers/mtd/Makefile !!!


+menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
+	depends on MTD != n && EXPERIMENTAL
+
+config MTD_ONENAND
+	tristate "OneNAND Device Support"
+	depends on MTD
+	select MTD_ONENAND_INFO

Why do you need a seperate config option, which is just a mirror of
MTD_ONENAND ?

+
+        /* try the first address */
+	omap_onenand_flash_base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);

Why a seperate static variable ? Please use the base member of the
private structure.

+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+	struct onenand_chip * this = mtd->priv;
+	unsigned long timeout;
+	unsigned int flags = ONENAND_INT_MASTER;
+	unsigned int interrupt = 0;
+	unsigned int ctrl, ecc;
+
+	/* The 10 msec is enough */
+	timeout = jiffies + msecs_to_jiffies(10);
+	while (time_before(jiffies, timeout)) {
+		interrupt = onenand_readw(this->base + ONENAND_REG_INTERRUPT);
+
+		if (interrupt & flags)
+			break;
+		yield();

Please use cond_resched() instead of yield()

+	}
+	/* To get correct interrupt status in timeout case */
+	interrupt = onenand_readw(this->base + ONENAND_REG_INTERRUPT);
+
+	if (!interrupt)
+		BUG();

A timeout should be handled gracefully by the driver. Use BUG() to catch
errors, which are caused by invalid arguments to a function,
uninitialized data structures or calling from a wrong context. 


+static int onenand_dataram(struct mtd_info *mtd, int write,
+		unsigned char *buffer, int offset, int count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *src, *dest;
+	void __iomem *dataram;
+
+	dataram = this->base + ONENAND_DATARAM;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this))
+		dataram += mtd->oobblock;
+
+	if (write) {
+		src = buffer;
+		dest = dataram + offset;
+	} else {
+		src = dataram + offset;
+		dest = buffer;
+	}
+
+	memcpy(dest, src, count);


Can the read/write functions be seperate please ?
Only the hardware access should be replaceable by the board driver.
Calculations which are valid for every implementation should be done in
generic code. This reduces the code size and the error sources for
hardware specific implementations


+static int onenand_spareram(struct mtd_info *mtd, int write,
+		unsigned char *buffer,  int offset, int count)

Same as above.

+static void onenand_get_device(struct onenand_chip *this, int new_state)
+{
+	struct onenand_chip *active = this;
+	DECLARE_WAITQUEUE(wait, current);
+
+	/*
+	 * Grab the lock and see if the device is available
+	 */
+retry:
+	if (active == this) {

That's bogus, as active is never changed.

+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd		MTD device structure
+ * @param buf		the databuffer to verify
+ * @param block		block address
+ * @param page		page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char *buf,
+	loff_t addr, int block, int page)
+{
<SNIP>
+	dataram1 = dataram0 + mtd->oobblock;
+
+	if (memcmp(dataram0, dataram1, mtd->oobblock))
+		return -EBADMSG;

See onenand_dataram()


+static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
<SNIP>
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);

Why not ?

+		/* Sanity check */
+		while (onenand_readw(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;

What happens if the condition is not met ? 

<SNIP>
+		/* Sanity check */
+		while (onenand_readw(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;

Same as above

+		/* Set block address for read block status */
+		value = onenand_block_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS1);
+
+		/* Check lock status */
+		status = onenand_readw(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
+	}
+	
+	return 0;

The function returns unconditionally success, even if the status is not
correct !



+/**
+ * onenand_scan - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd		MTD device structure
+ *
+ * OneNAND detection method:
+ *   Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)

Please make comment and function name consistent.



+/*
+ *  linux/drivers/mtd/onenand/onenand_info.c

<SNIP>

+EXPORT_SYMBOL_GPL(onenand_print_device_info);
+EXPORT_SYMBOL_GPL(onenand_print_maf_info);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Display OneNAND device and manufacturer ID's");


Please link this with onenand_base.c. It's overkill to have those
exports and a seperate module. The seperate nand_ids file in
drivers/mtd/nand is solely there to make it reusable by the legacy
DiskOnChip drivers. Once those are gone the id table will be linked to
nand_base.c unconditionally.


+	FL_ERASING,
+	FL_SYNCING,
+	FL_UNLOCKING,
+} onenand_state_t;

Shouldnt there be a LOCK counterpart to UNLOCK ?


+/*
+ * Functions to access the OneNAND IO region
+ */
+#define onenand_readw(a)		readw(a)
+#define onenand_writew(v,a)		writew(v, a)

Please make onenand_readw/writew functions accessible by function
pointers along with default implementations, so the board driver can
override them if necessary.

Re: [PATCH] OneNAND MTD support

[Artem B. Bityuckiy]

On Mon, 2005-07-04 at 10:19 +0900, Kyungmin Park wrote:
> Hi
> 
> We are happy to release OneNAND MTD to open source community.
Hello,

+config MTD_ONENAND_VERIFY_WRITE
+       bool "Verify OneNAND page writes"
+       depends on MTD_ONENAND
+       help
+         This adds an extra check when data is written to the flash.
The
+         OneNAND flash device internally checks only bits transitioning
+         from 1 to 0. There is a rare possibility that even though the
+         device thinks the write was successful, a bit could have been
+         flipped accidentaly due to device wear or something else.

Why general MTD  CONFIG_MTD_NAND_VERIFY_WRITE config option and -
>verify_buf driver method (see nand_base.c) is not enough and you need
your own verify option?

Re: [PATCH] OneNAND MTD support

[Thomas Gleixner]

On Mon, 2005-07-04 at 17:30 +0400, Artem B. Bityuckiy wrote:
> 
> Why general MTD  CONFIG_MTD_NAND_VERIFY_WRITE config option and -
> >verify_buf driver method (see nand_base.c) is not enough and you need
> your own verify option?

Because its a seperate driver in a seperate directory. It's ok.

tglx

RE: [PATCH] OneNAND MTD support

[Kyungmin Park]

[-- Attachment #1: Type: text/plain, Size: 3761 bytes --]


Hi

It's new patch as your request

and I append some bufferram function to reduce unnecessary read access.

It's similay page buf in NAND.

Regards

Kyungmin Park

> 
> Some remarks:
> 
> Kconfig and Makefile need references in drivers/mtd/Kconfig and
> drivers/mtd/Makefile !!!

Yes, I'm missing

>+menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
>+	depends on MTD != n && EXPERIMENTAL
>+
>+config MTD_ONENAND
>+	tristate "OneNAND Device Support"
>	depends on MTD
>	select MTD_ONENAND_INFO

>Why do you need a seperate config option, which is just a mirror of
MTD_ONENAND ?

I don't understood. What's meaning?

> 
> +
> +        /* try the first address */
> +	omap_onenand_flash_base = 
> ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
> 
> Why a seperate static variable ? Please use the base member of the
> private structure.

OK. I done.

> +static int onenand_dataram(struct mtd_info *mtd, int write,
> +		unsigned char *buffer, int offset, int count)
> +{
> +	struct onenand_chip *this = mtd->priv;
> +	void __iomem *src, *dest;
> +	void __iomem *dataram;
> +
> +	dataram = this->base + ONENAND_DATARAM;
> +
> +	if (ONENAND_CURRENT_BUFFERRAM(this))
> +		dataram += mtd->oobblock;
> +
> +	if (write) {
> +		src = buffer;
> +		dest = dataram + offset;
> +	} else {
> +		src = dataram + offset;
> +		dest = buffer;
> +	}
> +
> +	memcpy(dest, src, count);
> 
> 
> Can the read/write functions be seperate please ?
> Only the hardware access should be replaceable by the board driver.
> Calculations which are valid for every implementation should 
> be done in
> generic code. This reduces the code size and the error sources for
> hardware specific implementations

As your request, I create read/write_bufferram function instread of dataram
and spareram
 
> 
> +static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, 
> size_t len)
> <SNIP>
> +		/* There's no return value */
> +		this->wait(mtd, FL_UNLOCKING);
> 
> Why not ?

There's no status check in locking mechanism

> 
> +		/* Sanity check */
> +		while (onenand_readw(this->base + 
> ONENAND_REG_CTRL_STATUS)
> +		    & ONENAND_CTRL_ONGO)
> +			continue;
> 
> What happens if the condition is not met ?

I think it's board bug. For safety I check it. 

> 
> +/**
> + * onenand_scan - [OneNAND Interface] Probe the OneNAND device
> + * @param mtd		MTD device structure
> + *
> + * OneNAND detection method:
> + *   Compare the the values from command with ones from register
> + */
> +static int onenand_probe(struct mtd_info *mtd)
> 
> Please make comment and function name consistent.

OK. fix it

> +/*
> + *  linux/drivers/mtd/onenand/onenand_info.c
> 
> <SNIP>
> 
> +EXPORT_SYMBOL_GPL(onenand_print_device_info);
> +EXPORT_SYMBOL_GPL(onenand_print_maf_info);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
> +MODULE_DESCRIPTION("Display OneNAND device and manufacturer ID's");
> 
> 
> Please link this with onenand_base.c. It's overkill to have those
> exports and a seperate module. The seperate nand_ids file in
> drivers/mtd/nand is solely there to make it reusable by the legacy
> DiskOnChip drivers. Once those are gone the id table will be linked to
> nand_base.c unconditionally.

I merged it 

> 
> 
> +	FL_ERASING,
> +	FL_SYNCING,
> +	FL_UNLOCKING,
> +} onenand_state_t;
> 
> Shouldnt there be a LOCK counterpart to UNLOCK ?

OK.

> 
> 
> +/*
> + * Functions to access the OneNAND IO region
> + */
> +#define onenand_readw(a)		readw(a)
> +#define onenand_writew(v,a)		writew(v, a)
> 
> Please make onenand_readw/writew functions accessible by function
> pointers along with default implementations, so the board driver can
> override them if necessary.
> 

It's just memory access function. I think no need to make a function.


[-- Attachment #2: onenand-mtd.patch --]
[-- Type: application/octet-stream, Size: 59009 bytes --]

Index: drivers/mtd/Kconfig
===================================================================
--- 0da3933055729e361b7b9ffd523f17ac65ca1489/drivers/mtd/Kconfig  (mode:100644)
+++ uncommitted/drivers/mtd/Kconfig  (mode:100644)
@@ -261,5 +261,7 @@

 source "drivers/mtd/nand/Kconfig"

+source "drivers/mtd/onenand/Kconfig"
+
 endmenu

Index: drivers/mtd/Makefile
===================================================================
--- 0da3933055729e361b7b9ffd523f17ac65ca1489/drivers/mtd/Makefile  (mode:100644)
+++ uncommitted/drivers/mtd/Makefile  (mode:100644)
@@ -24,4 +24,4 @@
 nftl-objs              := nftlcore.o nftlmount.o
 inftl-objs             := inftlcore.o inftlmount.o

-obj-y          += chips/ maps/ devices/ nand/
+obj-y          += chips/ maps/ devices/ nand/ onenand/
Index: drivers/mtd/onenand/Kconfig
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Kconfig  (mode:100644)
@@ -0,0 +1,32 @@
+#
+# linux/drivers/mtd/onenand/Kconfig
+#
+
+menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
+	depends on MTD != n && EXPERIMENTAL
+
+config MTD_ONENAND
+	tristate "OneNAND Device Support"
+	depends on MTD
+	help
+	  This enables support for accessing all type of OneNAND flash
+	  devices. For further information see
+	  <http://www.samsung.com/Products/Semiconductor/Flash/OneNAND_TM/index.htm>.
+
+config MTD_ONENAND_VERIFY_WRITE
+	bool "Verify OneNAND page writes"
+	depends on MTD_ONENAND
+	help
+	  This adds an extra check when data is written to the flash. The
+	  OneNAND flash device internally checks only bits transitioning
+	  from 1 to 0. There is a rare possibility that even though the
+	  device thinks the write was successful, a bit could have been
+	  flipped accidentaly due to device wear or something else.
+
+config MTD_ONENAND_OMAP
+	tristate "OneNAND Flash device on OMAP board"
+	depends on ARM && ARCH_OMAP && MTD_ONENAND
+	help
+	  Support for OneNAND flash on TI OMAP board.
+
+endmenu
Index: drivers/mtd/onenand/Makefile
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Makefile  (mode:100644)
@@ -0,0 +1,9 @@
+#
+# Makefile for the OneNAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_ONENAND)		+= onenand_base.o
+
+# Board specific.
+obj-$(CONFIG_MTD_ONENAND_OMAP)		+= omap-onenand.o
Index: drivers/mtd/onenand/omap-onenand.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/omap-onenand.c  (mode:100644)
@@ -0,0 +1,179 @@
+/*
+ *  linux/drivers/mtd/onenand/omap-onenand.c
+ *
+ *  Copyright (c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Derived from linux/drivers/mtd/nand/omap-nand-flash.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Overview:
+ *   This is a device driver for the OneNAND flash device for TI OMAP boards.
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/tc.h>
+#include <asm/sizes.h>
+
+#define OMAP_ONENAND_FLASH_START1	OMAP_CS2A_PHYS
+#define OMAP_ONENAND_FLASH_START2	OMAP_CS0_PHYS
+/*
+ * MTD structure for OMAP board
+ */
+static struct mtd_info *omap_onenand_mtd = NULL;
+
+/*
+ * Define partitions for flash devices
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition static_partition[] = {
+	{
+		.name		= "X-Loader + U-Boot",
+		.offset		= 0,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "U-Boot Environment",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= 2 * SZ_1M
+	},
+	{
+		.name		= "filesystem0",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_16M,
+	},
+	{
+		.name		= "filesystem1",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= MTDPART_SIZ_FULL,
+	},
+};
+
+const char *part_probes[] = { "cmdlinepart", NULL,  };
+
+#endif
+
+/* Scan to find existance of the device at base.
+   This also allocates oob and data internal buffers */
+static char onenand_name[] = "onenand";
+
+/*
+ * Main initialization routine
+ */
+static int __init omap_onenand_init (void)
+{
+	struct onenand_chip *this;
+	struct mtd_partition *dynamic_partition = 0;
+	int err = 0;
+
+	/* Allocate memory for MTD device structure and private data */
+	omap_onenand_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct onenand_chip),
+				GFP_KERNEL);
+	if (!omap_onenand_mtd) {
+		printk (KERN_WARNING "Unable to allocate OneNAND MTD device structure.\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	/* Get pointer to private data */
+	this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *) omap_onenand_mtd, 0, sizeof(struct mtd_info) + sizeof(struct onenand_chip));
+
+	/* Link the private data with the MTD structure */
+	omap_onenand_mtd->priv = this;
+
+        /* try the first address */
+	this->base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
+	omap_onenand_mtd->name = onenand_name;
+	if (onenand_scan(omap_onenand_mtd, 1)){
+		/* try the second address */
+		iounmap(this->base);
+		this->base = ioremap(OMAP_ONENAND_FLASH_START2, SZ_128K);
+		if (onenand_scan(omap_onenand_mtd, 1)) {
+			iounmap(this->base);
+                        err = -ENXIO;
+                        goto out_mtd;
+		}
+	}
+
+	/* Register the partitions */
+	switch (omap_onenand_mtd->size) {
+	case SZ_128M:
+	case SZ_64M:
+	case SZ_32M:
+#ifdef CONFIG_MTD_PARTITIONS
+		err = parse_mtd_partitions(omap_onenand_mtd, part_probes,
+					&dynamic_partition, 0);
+		if (err > 0)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					dynamic_partition, err);
+		else if (1)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					static_partition,
+					ARRAY_SIZE(static_partition));
+		else
+#endif
+			err = add_mtd_device(omap_onenand_mtd);
+		if (err)
+			goto out_buf;
+		break;
+
+	default:
+		printk(KERN_WARNING "Unsupported OneNAND device\n");
+		err = -ENXIO;
+		goto out_buf;
+	}
+
+	goto out;
+
+out_buf:
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+out_mtd:
+	kfree(omap_onenand_mtd);
+out:
+	return err;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit omap_onenand_cleanup (void)
+{
+	struct onenand_chip *this = omap_onenand_mtd->priv;
+
+	/* onenand_release frees MTD partitions, MTD structure
+	   and onenand internal buffers */
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+	kfree(omap_onenand_mtd);
+}
+
+module_init(omap_onenand_init);
+module_exit(omap_onenand_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP boards");
Index: drivers/mtd/onenand/onenand_base.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/onenand_base.c  (mode:100644)
@@ -0,0 +1,1433 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_base.c
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+/**
+ * onenand_oob_64 - oob info for large (2KB) page
+ */
+static struct nand_oobinfo onenand_oob_64 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 20,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		40, 41, 42, 43, 44,
+		56, 57, 58, 59, 60,
+		},
+	.oobfree	= {
+		{2, 3}, {14, 2}, {18, 3}, {30, 2},
+		{24, 3}, {46, 2}, {40, 3}, {62, 2} }
+};
+
+/**
+ * onenand_oob_32 - oob info for middle (1KB) page
+ */
+static struct nand_oobinfo onenand_oob_32 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 10,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		},
+	.oobfree	= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
+};
+
+static const unsigned char ffchars[] = {
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 16 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 32 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 48 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 64 */
+};
+
+/**
+ * onenand_block_address - [DEFAULT] Get block address
+ * @param device	the device id
+ * @param block		the block
+ * @return		translated block address if DDP, otherwise same
+ *
+ * Setup Start Address 1 Register (F100h)
+ */
+static int onenand_block_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device Flash Core select, NAND Flash Block Address */
+		int dfs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dfs = 1;
+
+		return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1));
+	}
+
+	return block;
+}
+
+/**
+ * onenand_bufferram_address - [DEFAULT] Get bufferram address
+ * @param device	the device id
+ * @param block		the block
+ * @return		set DBS value if DDP, otherwise 0
+ *
+ * Setup Start Address 2 Register (F101h) for DDP
+ */
+static int onenand_bufferram_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device BufferRAM Select */
+		int dbs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dbs = 1;
+
+		return (dbs << ONENAND_DDP_SHIFT);
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_page_address - [DEFAULT] Get page address
+ * @param page		the page address
+ * @param sector	the sector address
+ * @return		combined page and sector address
+ *
+ * Setup Start Address 8 Register (F107h)
+ */
+static int onenand_page_address(int page, int sector)
+{
+	/* Flash Page Address, Flash Sector Address */
+	int fpa, fsa;
+
+	fpa = page & ONENAND_FPA_MASK;
+	fsa = sector & ONENAND_FSA_MASK;
+
+	return ((fpa << ONENAND_FPA_SHIFT) | fsa);
+}
+
+/**
+ * onenand_buffer_address - [DEFAULT] Get buffer address
+ * @param dataram1	DataRAM index
+ * @param sectors	the sector address
+ * @param count		the number of sectors
+ * @return		the start buffer value
+ *
+ * Setup Start Buffer Register (F200h)
+ */
+static int onenand_buffer_address(int dataram1, int sectors, int count)
+{
+	int bsa, bsc;
+
+	/* BufferRAM Sector Address */
+	bsa = sectors & ONENAND_BSA_MASK;
+
+	if (dataram1)
+		bsa |= ONENAND_BSA_DATARAM1;	/* DataRAM1 */
+	else
+		bsa |= ONENAND_BSA_DATARAM0;	/* DataRAM0 */
+
+	/* BufferRAM Sector Count */
+	bsc = count & ONENAND_BSC_MASK;
+
+	return ((bsa << ONENAND_BSA_SHIFT) | bsc);
+}
+
+/**
+ * onenand_command - [DEFAULT] Send command to OneNAND device
+ * @param mtd		MTD device structure
+ * @param cmd		the command to be sent
+ * @param addr		offset to read from or write to
+ * @param len		number of bytes to read or write
+ *
+ * Send command to OneNAND device. This function is used for middle/large page
+ * devices (1KB/2KB Bytes per page)
+ */
+static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int value, readcmd = 0;
+	int block, page;
+	/* Now we use page size operation */
+	int sectors = 4, count = 4;
+
+	/* Address translation */
+	switch (cmd) {
+	case ONENAND_CMD_UNLOCK:
+	case ONENAND_CMD_LOCK:
+	case ONENAND_CMD_LOCK_TIGHT:
+		block = -1;
+		page = -1;
+		break;
+
+	case ONENAND_CMD_ERASE:
+	case ONENAND_CMD_BUFFERRAM:
+		block = (int) (addr >> this->erase_shift);
+		page = -1;
+		break;
+
+	default:
+		block = (int) (addr >> this->erase_shift);
+		page = (int) (addr >> this->page_shift);
+		page &= this->page_mask;
+		break;
+	}
+
+	/* NOTE: The setting order of the registers is very important! */
+	if (cmd == ONENAND_CMD_BUFFERRAM) {
+		/* Select DataRAM for DDP */
+		value = onenand_bufferram_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS2);
+
+		/* Switch to the next data buffer */
+		ONENAND_SET_NEXT_BUFFERRAM(this);
+
+		return 0;
+	}
+
+	if (block != -1) {
+		/* Write 'DFS, FBA' of Flash */
+		value = onenand_block_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS1);
+	}
+
+	if (page != -1) {
+		int dataram;
+
+		switch (cmd) {
+		case ONENAND_CMD_READ:
+		case ONENAND_CMD_READOOB:
+			dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+			readcmd = 1;
+			break;
+
+		default:
+			dataram = ONENAND_CURRENT_BUFFERRAM(this);
+			break;
+		}
+
+		/* Write 'FPA, FSA' of Flash */
+		value = onenand_page_address(page, sectors);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS8);
+
+		/* Write 'BSA, BSC' of DataRAM */
+		value = onenand_buffer_address(dataram, sectors, count);
+		onenand_writew(value, this->base + ONENAND_REG_START_BUFFER);
+			
+		if (readcmd) {
+			/* Select DataRAM for DDP */
+			value = onenand_bufferram_address(this->device_id, block);
+			onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS2);
+		}
+	}
+
+	/* Interrupt clear */
+	onenand_writew(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
+
+	/* Write command */
+	onenand_writew(cmd, this->base + ONENAND_REG_COMMAND);
+
+	return 0;
+}
+
+/**
+ * onenand_wait - [DEFAULT] wait until the command is done
+ * @param mtd		MTD device structure
+ * @param state		state to select the max. timeout value
+ *
+ * Wait for command done. This applies to all OneNAND command
+ * Read can take up to 30us, erase up to 2ms and program up to 350us
+ * according to general OneNAND specs
+ */
+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+	struct onenand_chip * this = mtd->priv;
+	unsigned long timeout;
+	unsigned int flags = ONENAND_INT_MASTER;
+	unsigned int interrupt = 0;
+	unsigned int ctrl, ecc;
+
+	/* The 10 msec is enough */
+	timeout = jiffies + msecs_to_jiffies(10);
+	while (time_before(jiffies, timeout)) {
+		interrupt = onenand_readw(this->base + ONENAND_REG_INTERRUPT);
+
+		if (interrupt & flags)
+			break;
+
+		if (state != FL_READING)
+			cond_resched();
+	}
+	/* To get correct interrupt status in timeout case */
+	interrupt = onenand_readw(this->base + ONENAND_REG_INTERRUPT);
+
+	ctrl = onenand_readw(this->base + ONENAND_REG_CTRL_STATUS);
+
+	if (ctrl & ONENAND_CTRL_ERROR) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (ctrl & ONENAND_CTRL_LOCK) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (interrupt & ONENAND_INT_READ) {
+		ecc = onenand_readw(this->base + ONENAND_REG_ECC_STATUS);
+		if (ecc & ONENAND_ECC_2BIT_ALL) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x", ecc);
+			return -EBADMSG;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Read the BufferRAM area
+ */
+static int onenand_read_bufferram(struct mtd_info *mtd, int area,
+		unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	if (area == DATARAM)
+		bufferram = this->base + ONENAND_DATARAM;
+	else if (area == SPARERAM)
+		bufferram = this->base + ONENAND_SPARERAM;
+	else  
+		bufferram = this->base + ONENAND_BOOTRAM;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == DATARAM)
+			bufferram += mtd->oobblock;
+		else if (area == SPARERAM)
+			bufferram += mtd->oobsize;
+	}
+
+	memcpy(buffer, bufferram + offset, count);
+
+	return 0;
+}
+
+/**
+ * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Write the BufferRAM area
+ */
+static int onenand_write_bufferram(struct mtd_info *mtd, int area,
+		const unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	if (area == DATARAM)
+		bufferram = this->base + ONENAND_DATARAM;
+	else if (area == SPARERAM)
+		bufferram = this->base + ONENAND_SPARERAM;
+	else  
+		bufferram = this->base + ONENAND_BOOTRAM;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == DATARAM)
+			bufferram += mtd->oobblock;
+		else if (area == SPARERAM)
+			bufferram += mtd->oobsize;
+	}
+
+	memcpy(bufferram + offset, buffer, count);
+
+	return 0;
+}
+
+/**
+ * onenand_check_bufferram - [GENERIC] Check BufferRAM information
+ * @param mtd		MTD data structure
+ * @param addr		address to check
+ * @return		1 if there are valid data, otherwise 0 
+ *
+ * Check bufferram if there is data we required
+ */
+static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
+{
+	struct onenand_chip *this = mtd->priv;
+	int block, page;
+	int i;
+	
+	block = (int) (addr >> this->erase_shift);
+	page = (int) (addr >> this->page_shift);
+	page &= this->page_mask;
+
+	i = ONENAND_CURRENT_BUFFERRAM(this);
+
+	/* Is there valid data? */
+	if (this->bufferram[i].block == block &&
+	    this->bufferram[i].page == page &&
+	    this->bufferram[i].valid)
+		return 1;
+
+	return 0;
+}
+
+/**
+ * onenand_update_bufferram - [GENERIC] Update BufferRAM information
+ * @param mtd		MTD data structure
+ * @param addr		address to update
+ * @param valid		valid flag
+ *
+ * Update BufferRAM information
+ */
+static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
+		int valid)
+{
+	struct onenand_chip *this = mtd->priv;
+	int block, page;
+	int i;
+	
+	block = (int) (addr >> this->erase_shift);
+	page = (int) (addr >> this->page_shift);
+	page &= this->page_mask;
+
+	/* Invalidate BufferRAM */
+	for (i = 0; i < MAX_BUFFERRAM; i++) {
+		if (this->bufferram[i].block == block &&
+		    this->bufferram[i].page == page)
+			this->bufferram[i].valid = 0;
+	}
+
+	/* Update BufferRAM */
+	i = ONENAND_CURRENT_BUFFERRAM(this);
+	this->bufferram[i].block = block;
+	this->bufferram[i].page = page;
+	this->bufferram[i].valid = valid;
+
+	return 0;
+}
+
+/**
+ * onenand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd		MTD device structure
+ * @param new_state	the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+static void onenand_get_device(struct mtd_info *mtd, int new_state)
+{
+	struct onenand_chip *this = mtd->priv;
+	DECLARE_WAITQUEUE(wait, current);
+
+	/*
+	 * Grab the lock and see if the device is available
+	 */
+	while (1) {
+		spin_lock(&this->chip_lock);
+		if (this->state == FL_READY) {
+			this->state = new_state;
+			spin_unlock(&this->chip_lock);
+			break;
+		}
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&this->wq, &wait);
+		spin_unlock(&this->chip_lock);
+		schedule();
+		remove_wait_queue(&this->wq, &wait);
+	}
+}
+
+/**
+ * onenand_release_device - [GENERIC] release chip
+ * @param mtd		MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+static void onenand_release_device(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	/* Release the chip */
+	spin_lock(&this->chip_lock);
+	this->state = FL_READY;
+	wake_up(&this->wq);
+	spin_unlock(&this->chip_lock);
+}
+
+/**
+ * onenand_read_ecc - [MTD Interface] Read data with ECC
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ * @param oob_buf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND read with ECC
+ */
+static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf,
+	u_char *oob_buf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, column;
+	int thislen;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Do not allow reads past end of device */
+	if ((from + len) > mtd->size) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: Attempt read beyond end of device\n");
+		*retlen = 0;
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_READING);
+
+	/* TODO handling oob */
+
+	while (read < len) {
+		thislen = min_t(int, mtd->oobblock, len - read);
+
+		column = from & (mtd->oobblock - 1);
+		if (column + thislen > mtd->oobblock)
+			thislen = mtd->oobblock - column;
+
+		if (!onenand_check_bufferram(mtd, from)) {
+			this->command(mtd, ONENAND_CMD_READ, from, mtd->oobblock);
+
+			ret = this->wait(mtd, FL_READING);
+			/* First copy data and check return value for ECC handling */
+			onenand_update_bufferram(mtd, from, 1);
+		}
+
+		this->read_bufferram(mtd, DATARAM, buf, column, thislen);
+
+		read += thislen;
+
+		if (read == len)
+			break;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: read failed = %d\n", ret);
+			goto out;
+		}
+
+		from += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	/*
+	 * Return success, if no ECC failures, else -EBADMSG
+	 * fs driver will take care of that, because
+	 * retlen == desired len and result == -EBADMSG
+	 */
+	*retlen = read;
+	return ret;
+}
+
+/**
+ * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
+*/
+static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * OneNAND read out-of-band data from the spare area
+ */
+static int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, thislen, column;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Initialize return length value */
+	*retlen = 0;
+
+	/* Do not allow reads past end of device */
+	if (unlikely((from + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_READING);
+
+	column = from & (mtd->oobsize - 1);
+
+	while (read < len) {
+		thislen = mtd->oobsize - column;
+		thislen = min_t(int, thislen, len);
+
+		this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+
+		onenand_update_bufferram(mtd, from, 0);
+
+		ret = this->wait(mtd, FL_READING);
+		/* First copy data and check return value for ECC handling */
+
+		this->read_bufferram(mtd, SPARERAM, buf, column, thislen);
+
+		read += thislen;
+
+		if (read == len)
+			break;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = %d\n", ret);
+			goto out;
+		}
+
+		buf += thislen;
+
+		/* Read more? */
+		if (read < len) {
+			/* Page size */
+			from += mtd->oobblock;
+			column = 0;
+		}
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = read;
+	return ret;
+}
+
+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd		MTD device structure
+ * @param buf		the databuffer to verify
+ * @param block		block address
+ * @param page		page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char *buf,
+	loff_t addr, int block, int page)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *dataram0, *dataram1;
+	int ret = 0;
+
+	this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock);
+
+	ret = this->wait(mtd, FL_READING);
+	if (ret)
+		return ret;
+
+	onenand_update_bufferram(mtd, addr, 1);
+
+	/* Check, if the two dataram areas are same */
+	dataram0 = this->base + ONENAND_DATARAM;
+	dataram1 = dataram0 + mtd->oobblock;
+
+	if (memcmp(dataram0, dataram1, mtd->oobblock))
+		return -EBADMSG;
+	
+	return 0;
+}
+#else
+#define onenand_verify_page(...)	(0)
+#endif
+
+#define NOTALIGNED(x)	((x & (mtd->oobblock - 1)) != 0)
+
+/**
+ * onenand_write_ecc - [MTD Interface] OneNAND write with ECC
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with ECC
+ */
+static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int written = 0;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobblock, len - written);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->write_bufferram(mtd, DATARAM, buf, 0, thislen);
+		this->write_bufferram(mtd, SPARERAM, ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		onenand_update_bufferram(mtd, to, 1);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: write filaed %d\n", ret);
+			goto out;
+		}
+
+		written += thislen;
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return ret;
+}
+
+/**
+ * onenand_write - [MTD Interface] compability function for onenand_write_ecc
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * This function simply calls onenand_write_ecc
+ * with oob buffer and oobsel = NULL
+ */
+static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * OneNAND write out-of-band
+ */
+static int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int column, status;
+	int written = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobsize, len - written);
+
+		column = to & (mtd->oobsize - 1);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
+
+		this->write_bufferram(mtd, SPARERAM, ffchars, 0, mtd->oobsize);
+		this->write_bufferram(mtd, SPARERAM, buf, column, thislen);
+
+		this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+
+		onenand_update_bufferram(mtd, to, 0);
+
+		status = this->wait(mtd, FL_WRITING);
+		if (status)
+			goto out;
+
+		written += thislen;
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return 0;
+}
+
+/**
+ * onenand_writev_ecc - [MTD Interface] write with iovec with ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with iovec with ecc
+ */
+static int onenand_writev_ecc(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned char buffer[mtd->oobblock], *pbuf;
+	size_t total_len, len;
+	int i, written = 0;
+	int ret = 0;
+
+	/* Preset written len for early exit */
+	*retlen = 0;
+
+	/* Calculate total length of data */
+	total_len = 0;
+	for (i = 0; i < count; i++)
+		total_len += vecs[i].iov_len;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_writev_ecc: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
+
+	/* Do not allow write past end of the device */
+	if (unlikely((to + total_len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempted write past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(total_len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* TODO handling oob */
+	
+	/* Loop until all keve's data has been written */
+	len = 0;
+	while (count) {
+		pbuf = buffer;
+		/* 
+		 * If the given tuple is >= pagesize then
+		 * write it out from the iov
+		 */
+		if ((vecs->iov_len - len) >= mtd->oobblock) {
+			pbuf = vecs->iov_base + len;
+
+			len += mtd->oobblock;
+
+			/* Check, if we have to switch to the next tuple */
+			if (len >= (int) vecs->iov_len) {
+				vecs++;
+				len = 0;
+				count--;
+			}
+		} else {
+			int cnt = 0, thislen;
+			while (cnt < mtd->oobblock) {
+				thislen = min_t(int, mtd->oobblock - cnt, vecs->iov_len - len);
+				memcpy(buffer + cnt, vecs->iov_base + len, thislen);
+				cnt += thislen;
+				len += thislen;
+
+				/* Check, if we have to switch to the next tuple */
+				if (len >= (int) vecs->iov_len) {
+					vecs++;
+					len = 0;
+					count--;
+				}
+			}
+		}
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->write_bufferram(mtd, DATARAM, pbuf, 0, mtd->oobblock);
+		this->write_bufferram(mtd, SPARERAM, ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		onenand_update_bufferram(mtd, to, 1);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: write failed %d\n", ret);
+			goto out;
+		}
+
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) pbuf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		written += mtd->oobblock;
+
+		to += mtd->oobblock;
+	}
+
+out:
+	/* Deselect and wakt up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+
+	return 0;
+}
+
+/**
+ * onenand_writev - [MTD Interface] compabilty function for onenand_writev_ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ *
+ * OneNAND write with kvec. This just calls the ecc function
+ */
+static int onenand_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen)
+{
+	return onenand_writev_ecc(mtd, vecs, count, to, retlen, NULL, NULL);
+}
+
+/**
+ * onenand_erase - [MTD Interface] erase block(s)
+ * @param mtd		MTD device structure
+ * @param instr		erase instruction
+ *
+ * Erase one ore more blocks
+ */
+static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned int block_size;
+	loff_t addr;
+	int len;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
+
+	block_size = (1 << this->erase_shift);
+
+	/* Start address must align on block boundary */
+	if (unlikely(instr->addr & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n");
+		return -EINVAL;
+	}
+
+	/* Length must align on block boundary */
+	if (unlikely(instr->len & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n");
+		return -EINVAL;
+	}
+
+	/* Do not allow erase past end of device */
+	if (unlikely((instr->len + instr->addr) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n");
+		return -EINVAL;
+	}
+
+	instr->fail_addr = 0xffffffff;
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_ERASING);
+
+	/* Loop throught the pages */
+	len = instr->len;
+	addr = instr->addr;
+
+	instr->state = MTD_ERASING;
+
+	while (len) {
+
+		/* TODO Check badblock */
+
+		this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
+
+		ret = this->wait(mtd, FL_ERASING);
+		/* Check, if it is write protected */
+		if (ret) {
+			if (ret == -EPERM)
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Device is write protected!!!\n");
+			else
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift));
+			instr->state = MTD_ERASE_FAILED;
+			instr->fail_addr = addr;
+			goto erase_exit;
+		}
+
+		len -= block_size;
+		addr += block_size;
+	}
+
+	instr->state = MTD_ERASE_DONE;
+
+erase_exit:
+
+	ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+	/* Do call back function */
+	if (!ret)
+		mtd_erase_callback(instr);
+
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	return ret;
+}
+
+/**
+ * onenand_sync - [MTD Interface] sync
+ * @param mtd		MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+static void onenand_sync(struct mtd_info *mtd)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_SYNCING);
+
+	/* Release it and go back */
+	onenand_release_device(mtd);
+}
+
+/**
+ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/*
+	 * TODO 
+	 * 1. Bad block table (BBT)
+	 *   -> using NAND BBT to support JFFS2
+	 * 2. Bad block management (BBM)
+	 *   -> bad block replace scheme
+	 *
+	 * Currently we do nothing
+	 */
+	return 0;
+}
+
+/**
+ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/* see above */
+	return 0;
+}
+
+/**
+ * onenand_unlock - [MTD Interface] Unlock block(s)
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ * @param len		number of bytes to unlock
+ *
+ * Unlock one or more blocks
+ */
+static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int start, end, block, value, status;
+
+	start = ofs >> this->erase_shift;
+	end = len >> this->erase_shift;
+
+	/* Continuous lock scheme */
+	if (this->options & ONENAND_CONT_LOCK) {
+		/* Set start block address */
+		onenand_writew(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Set end block address */
+		onenand_writew(end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (onenand_readw(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Check lock status */
+		status = onenand_readw(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "wp status = 0x%x\n", status);
+
+		return 0;
+	}
+
+	/* Block lock scheme */
+	for (block = start; block < end; block++) {
+		/* Set start block address */
+		onenand_writew(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (onenand_readw(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Set block address for read block status */
+		value = onenand_block_address(this->device_id, block);
+		onenand_writew(value, this->base + ONENAND_REG_START_ADDRESS1);
+
+		/* Check lock status */
+		status = onenand_readw(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
+	}
+	
+	return 0;
+}
+
+/**
+ * onenand_print_device_info - Print device ID
+ * @param device        device ID
+ *
+ * Print device ID
+ */
+static void onenand_print_device_info(int device)
+{
+        int vcc, demuxed, ddp, density;
+
+        vcc = device & ONENAND_DEVICE_VCC_MASK;
+        demuxed = device & ONENAND_DEVICE_IS_DEMUX;
+        ddp = device & ONENAND_DEVICE_IS_DDP;
+        density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+        printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
+                demuxed ? "" : "Muxed ",
+                ddp ? "(DDP)" : "",
+                (16 << density),
+                vcc ? "2.65/3.3" : "1.8",
+                device);
+}
+
+static const struct onenand_manufacturers onenand_manuf_ids[] = {
+        {ONENAND_MFR_SAMSUNG, "Samsung"},
+        {ONENAND_MFR_UNKNOWN, "Unknown"}
+};
+
+/**
+ * onenand_check_maf - Check manufacturer ID
+ * @param manuf         manufacturer ID
+ *
+ * Check manufacturer ID
+ */
+static int onenand_check_maf(int manuf)
+{
+        int i;
+
+        for (i = 0; onenand_manuf_ids[i].id; i++) {
+                if (manuf == onenand_manuf_ids[i].id)
+                        break;
+        }
+
+        printk(KERN_DEBUG "OneNAND Manufacturer: %s\n",
+                onenand_manuf_ids[i].name);
+
+        return (i != ONENAND_MFR_UNKNOWN);
+}
+
+/**
+ * onenand_probe - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd		MTD device structure
+ *
+ * OneNAND detection method:
+ *   Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	int bram_maf_id, bram_dev_id, maf_id, dev_id;
+	int density;
+
+	/* Send the command for reading device ID from BootRAM */
+	onenand_writew(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from BootRAM */
+	bram_maf_id = onenand_readw(this->base + ONENAND_BOOTRAM + 0x0);
+	bram_dev_id = onenand_readw(this->base + ONENAND_BOOTRAM + 0x2);
+
+	/* Check manufacturer ID */
+	if (onenand_check_maf(bram_maf_id))
+		return -ENXIO;
+
+	/* Reset OneNAND to read default register values */
+	onenand_writew(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from Register */
+	maf_id = onenand_readw(this->base + ONENAND_REG_MANUFACTURER_ID);
+	dev_id = onenand_readw(this->base + ONENAND_REG_DEVICE_ID);
+
+	/* Check OneNAND device */
+	if (maf_id != bram_maf_id || dev_id != bram_dev_id)
+		return -ENXIO;
+
+	/* Flash device information */
+	onenand_print_device_info(dev_id);
+	this->device_id = dev_id;
+
+	density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+	this->chipsize = (16 << density) << 20;
+
+	/* OneNAND page size & block size */
+	/* The data buffer size is equal to page size */
+	mtd->oobblock = onenand_readw(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+	mtd->oobsize = mtd->oobblock >> 5;
+	/* Pagers per block is always 64 in OneNAND */
+	mtd->erasesize = mtd->oobblock << 6;
+
+	this->erase_shift = ffs(mtd->erasesize) - 1;
+	this->page_shift = ffs(mtd->oobblock) - 1;
+	this->ppb_shift = (this->erase_shift - this->page_shift);
+	this->page_mask = (mtd->erasesize / mtd->oobblock) - 1;
+
+	/* REVIST: Multichip handling */
+
+	mtd->size = this->chipsize;
+
+	/* Version ID */
+	this->version_id = onenand_readw(this->base + ONENAND_REG_VERSION_ID);
+	printk(KERN_DEBUG "OneNAND version = 0x%04x\n", this->version_id);
+
+	/* Lock scheme */
+	if (density <= ONENAND_DEVICE_DENSITY_512Mb &&
+	    !(this->version_id >> ONENAND_VERSION_PROCESS_SHIFT)) {
+		printk(KERN_INFO "Lock scheme is Continues Lock\n");
+		this->options |= ONENAND_CONT_LOCK;
+	}
+	
+	return 0;
+}
+
+
+/**
+ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
+ * @param mtd		MTD device structure
+ * @param maxchips	Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values.
+ */
+int onenand_scan(struct mtd_info *mtd, int maxchips)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (!this->command)
+		this->command = onenand_command;
+	if (!this->wait)
+		this->wait = onenand_wait;
+
+	if (!this->read_bufferram)
+		this->read_bufferram = onenand_read_bufferram;
+	if (!this->write_bufferram)
+		this->write_bufferram = onenand_write_bufferram;
+
+	if (onenand_probe(mtd))
+		return -ENXIO;
+
+	this->state = FL_READY;
+	init_waitqueue_head(&this->wq);
+	spin_lock_init(&this->chip_lock);
+
+	switch (mtd->oobsize) {
+	case 64:
+		this->autooob = &onenand_oob_64;
+		break;
+
+	case 32:
+		this->autooob = &onenand_oob_32;
+		break;
+
+	default:
+		printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
+			mtd->oobsize);
+		/* To prevent kernel oops */
+		this->autooob = &onenand_oob_32;
+		break;
+	}
+
+	memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
+	
+	/* Fill in remaining MTD driver data */
+	mtd->type = MTD_NANDFLASH;
+	mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
+	mtd->ecctype = MTD_ECC_SW;
+	mtd->erase = onenand_erase;
+	mtd->point = NULL;
+	mtd->unpoint = NULL;
+	mtd->read = onenand_read;
+	mtd->write = onenand_write;
+	mtd->read_ecc = onenand_read_ecc;
+	mtd->write_ecc = onenand_write_ecc;
+	mtd->read_oob = onenand_read_oob;
+	mtd->write_oob = onenand_write_oob;
+	mtd->readv = NULL;
+	mtd->readv_ecc = NULL;
+	mtd->writev = onenand_writev;
+	mtd->writev_ecc = onenand_writev_ecc;
+	mtd->sync = onenand_sync;
+	mtd->lock = NULL;
+	mtd->unlock = onenand_unlock;
+	mtd->suspend = NULL;
+	mtd->resume = NULL;
+	mtd->block_isbad = onenand_block_isbad;
+	mtd->block_markbad = onenand_block_markbad;
+	mtd->owner = THIS_MODULE;
+
+	/* Unlock whole block */
+	mtd->unlock(mtd, 0x0, this->chipsize);
+
+	return 0;
+}
+
+/**
+ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
+ * @param mtd		MTD device structure
+ */
+void onenand_release(struct mtd_info *mtd)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+	/* Deregister partitions */
+	del_mtd_partitions (mtd);
+#endif
+	/* Deregister the device */
+	del_mtd_device (mtd);
+}
+
+EXPORT_SYMBOL(onenand_scan);
+EXPORT_SYMBOL(onenand_release);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Generic OneNAND flash driver code");
Index: include/linux/mtd/onenand.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand.h  (mode:100644)
@@ -0,0 +1,147 @@
+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand_regs.h>
+
+#define MAX_BUFFERRAM		2
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan(struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release(struct mtd_info *mtd);
+
+/* OneNAND BufferRAM */
+enum {
+	BOOTRAM,
+	DATARAM,
+	SPARERAM,
+};
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_UNLOCKING,
+	FL_LOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param block		block number in BufferRAM
+ * @param page		page number in BufferRAM
+ * @param valid		valid flag
+ */
+struct onenand_bufferram {
+	int block;
+	int page;
+	int valid;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param bufferam_index	[INTERN] BufferRAM index
+ * @param bufferam	[INTERN] BufferRAM info
+ * @param command	[REPLACEABLE] hardwarespecific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardwarespecific function for wait on ready
+ * @param read_bufferram	[REPLACEABLE] hardwarespecific function for BufferRAM Area
+ * @param write_bufferram	[REPLACEABLE] hardwarespecific function for BufferRAM Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem		*base;
+	unsigned int		chipsize;
+	unsigned int		device_id;
+	unsigned int		version_id;
+	unsigned int		options;
+
+	unsigned int		erase_shift;
+	unsigned int		page_shift;
+	unsigned int		ppb_shift;	/* Pages per block shift */
+	unsigned int		page_mask;
+
+	unsigned int		bufferram_index;
+	struct onenand_bufferram	bufferram[MAX_BUFFERRAM];
+
+	int (*command)(struct mtd_info *mtd, int cmd, loff_t address, size_t len);
+	int (*wait)(struct mtd_info *mtd, int state);
+	int (*read_bufferram)(struct mtd_info *mtd, int area,
+			unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram)(struct mtd_info *mtd, int area,
+			const unsigned char *buffer, int offset, size_t count);
+
+	spinlock_t		chip_lock;
+	wait_queue_head_t	wq;
+	onenand_state_t		state;
+
+	struct nand_oobinfo	*autooob;
+
+	void			*priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+
+/*
+ * Macros to access the OneNAND IO region
+ */
+#define onenand_readw(a)		readw(a)
+#define onenand_writew(v,a)		writew(v, a)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK		(0x0001)
+
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG	0xec
+#define ONENAND_MFR_UNKNOWN	0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+        int id;
+        char *name;
+};
+
+#endif	/* __LINUX_MTD_ONENAND_H */
Index: include/linux/mtd/onenand_regs.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand_regs.h  (mode:100644)
@@ -0,0 +1,167 @@
+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x3f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL		(1 << 12)
+#define ONENAND_SYS_CFG1_BL		(1 << 9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+
+#endif	/* __ONENAND_REG_H */

RE: [PATCH] OneNAND MTD support

[Thomas Gleixner]

Hi, Kyungmin

On Sat, 2005-07-09 at 11:13 +0900, Kyungmin Park wrote:

> It's new patch as your request
> and I append some bufferram function to reduce unnecessary read
> access.
> It's similay page buf in NAND.
> 
Thanks, looks much better now.


> >	select MTD_ONENAND_INFO
> 
> >Why do you need a seperate config option, which is just a mirror of
> MTD_ONENAND ?
> I don't understood. What's meaning?

MTD_ONENAND_INFO is a seperate config option, which gets turned on when
MTD_ONENAND is selected. This does not make much sense as you have only
MTD_ONENAND which can select MTD_ONENAND_INFO. Its superfluid anyway as
you merged the info code into the base code now.


> > +static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, 
> There's no status check in locking mechanism

Hmm. So all the status errors checked in onenand_wait() will never
happen here ?

> > 
> > +		/* Sanity check */
> > +		while (onenand_readw(this->base + 
> > ONENAND_REG_CTRL_STATUS)
> > +		    & ONENAND_CTRL_ONGO)
> > +			continue;
> > 
> > What happens if the condition is not met ?
> 
> I think it's board bug. For safety I check it. 

Then some kind of timeout is definitely appropriate. You will endup in a
dead loop when the condition is not met due to the bug.

> > +/*
> > + * Functions to access the OneNAND IO region
> > + */
> > +#define onenand_readw(a)		readw(a)
> > +#define onenand_writew(v,a)		writew(v, a)
> > 
> > Please make onenand_readw/writew functions accessible by function
> > pointers along with default implementations, so the board driver can
> > override them if necessary.
> > 
> 
> It's just memory access function. I think no need to make a function.

Yes, on your board. It turned out to be a good choice to turn _all_ the
functions which access hardware into function pointers. People design
weird hardware and the overhead of the function pointer based access is
minimal. Keeping it your way, one has to replace 4 complex functions
(command, wait, read/ write) instead of providing 4 small and simple
ones.




+config MTD_ONENAND_OMAP
+	tristate "OneNAND Flash device on OMAP board"
+	depends on ARM && ARCH_OMAP && MTD_ONENAND

"depends on ARCH_OMAP && MTD_ONENAND" is enough, as ARCH_OMAP already
depends on ARM


+++ uncommitted/drivers/mtd/onenand/omap-onenand.c  
+	default:
+		printk(KERN_WARNING "Unsupported OneNAND device\n");
+		err = -ENXIO;
+		goto out_buf;
+	}
+
+	goto out;

	return 0; 
This is the normal return path. Below is error exit (cleanup)

+
+out_buf:
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+out_mtd:
+	kfree(omap_onenand_mtd);
+out:
+	return err;

+++ uncommitted/drivers/mtd/onenand/onenand_base.c  (mode:100644)
+static int onenand_read_bufferram(struct mtd_info *mtd, int area,
+		unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	if (area == DATARAM)
+		bufferram = this->base + ONENAND_DATARAM;
+	else if (area == SPARERAM)
+		bufferram = this->base + ONENAND_SPARERAM;
+	else  
+		bufferram = this->base + ONENAND_BOOTRAM;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == DATARAM)
+			bufferram += mtd->oobblock;
+		else if (area == SPARERAM)
+			bufferram += mtd->oobsize;
+	}
+
+	memcpy(buffer, bufferram + offset, count);
+
+	return 0;
+}

area can be a direct offset (ONENAND_DATARAM, ONENAND_SPARERAM,
ONENAND_BOOTRAM), so you can just write: bufferram = this->base + area;


+static int onenand_write_bufferram(struct mtd_info *mtd, int area,
+		const unsigned char *buffer, int offset, size_t count)
+{

Same as onenand_read_bufferram

+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == DATARAM)
+			bufferram += mtd->oobblock;
+		else if (area == SPARERAM)
+			bufferram += mtd->oobsize;
+	}

Please make this a inline function used in read/write_bufferram

+EXPORT_SYMBOL(onenand_scan);
+EXPORT_SYMBOL(onenand_release);

Would you mind to change those exports to EXPORT_SYMBOL_GPL ?

+++ uncommitted/include/linux/mtd/onenand_regs.h  (mode:100644)

+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)

Is this considered to be a general rule, i.e. is this the only valid way
to address the chip ? 


+struct onenand_chip {
+	void __iomem		*base;
+	unsigned int		chipsize;
+	unsigned int		device_id;
+	unsigned int		version_id;
+	unsigned int		options;

Are device_id and version_id necessary for anything else than scan ? If
no, please remove.

RE: [PATCH] OneNAND MTD support

[Kyungmin Park]

[-- Attachment #1: Type: text/plain, Size: 4850 bytes --]

Hi 

Thank you for comments and advice.

Here's new patch.

Regards

Kyungmin Park

> > > +static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, 
> > There's no status check in locking mechanism
> 
> Hmm. So all the status errors checked in onenand_wait() will never
> happen here ?
> 
> > > 
> > > +		/* Sanity check */
> > > +		while (onenand_readw(this->base + 
> > > ONENAND_REG_CTRL_STATUS)
> > > +		    & ONENAND_CTRL_ONGO)
> > > +			continue;
> > > 
> > > What happens if the condition is not met ?
> > 
> > I think it's board bug. For safety I check it. 
> 
> Then some kind of timeout is definitely appropriate. You will 
> endup in a
> dead loop when the condition is not met due to the bug.

In OneNAND after operation done, The interrupt and controller status is
updated simultaneously.
So it's no problem checking controller status.
If the problem occurs, It's chip bug.

> 
> > > +/*
> > > + * Functions to access the OneNAND IO region
> > > + */
> > > +#define onenand_readw(a)		readw(a)
> > > +#define onenand_writew(v,a)		writew(v, a)
> > > 
> > > Please make onenand_readw/writew functions accessible by function
> > > pointers along with default implementations, so the board 
> driver can
> > > override them if necessary.
> > > 
> > 
> > It's just memory access function. I think no need to make a 
> function.
> 
> Yes, on your board. It turned out to be a good choice to turn 
> _all_ the
> functions which access hardware into function pointers. People design
> weird hardware and the overhead of the function pointer based 
> access is
> minimal. Keeping it your way, one has to replace 4 complex functions
> (command, wait, read/ write) instead of providing 4 small and simple
> ones.

OK. I do it

> 
> +config MTD_ONENAND_OMAP
> +	tristate "OneNAND Flash device on OMAP board"
> +	depends on ARM && ARCH_OMAP && MTD_ONENAND
> 
> "depends on ARCH_OMAP && MTD_ONENAND" is enough, as ARCH_OMAP already
> depends on ARM

It's derived from omap-nand-flash.c, But it's not sended to MTD.
OK. I done

> 
> 
> +++ uncommitted/drivers/mtd/onenand/omap-onenand.c  
> +	default:
> +		printk(KERN_WARNING "Unsupported OneNAND device\n");
> +		err = -ENXIO;
> +		goto out_buf;
> +	}
> +
> +	goto out;
> 
> 	return 0; 
> This is the normal return path. Below is error exit (cleanup)

OK

> 
> +++ uncommitted/drivers/mtd/onenand/onenand_base.c  (mode:100644)
> +static int onenand_read_bufferram(struct mtd_info *mtd, int area,
> +		unsigned char *buffer, int offset, size_t count)
> +{
> +	struct onenand_chip *this = mtd->priv;
> +	void __iomem *bufferram;
> +
> +	if (area == DATARAM)
> +		bufferram = this->base + ONENAND_DATARAM;
> +	else if (area == SPARERAM)
> +		bufferram = this->base + ONENAND_SPARERAM;
> +	else  
> +		bufferram = this->base + ONENAND_BOOTRAM;
> +
> +	if (ONENAND_CURRENT_BUFFERRAM(this)) {
> +		if (area == DATARAM)
> +			bufferram += mtd->oobblock;
> +		else if (area == SPARERAM)
> +			bufferram += mtd->oobsize;
> +	}
> +
> +	memcpy(buffer, bufferram + offset, count);
> +
> +	return 0;
> +}
> 
> area can be a direct offset (ONENAND_DATARAM, ONENAND_SPARERAM,
> ONENAND_BOOTRAM), so you can just write: bufferram = 
> this->base + area;
> 
> 
> +static int onenand_write_bufferram(struct mtd_info *mtd, int area,
> +		const unsigned char *buffer, int offset, size_t count)
> +{
> 
> Same as onenand_read_bufferram

Yes It is more natual. why I don't know this method :)

> 
> +	if (ONENAND_CURRENT_BUFFERRAM(this)) {
> +		if (area == DATARAM)
> +			bufferram += mtd->oobblock;
> +		else if (area == SPARERAM)
> +			bufferram += mtd->oobsize;
> +	}
> 
> Please make this a inline function used in read/write_bufferram

I done.

> 
> +EXPORT_SYMBOL(onenand_scan);
> +EXPORT_SYMBOL(onenand_release);
> 
> Would you mind to change those exports to EXPORT_SYMBOL_GPL ?

In fact I not sure and also don't know license issue. 
If we develop the some commercial mtd user software then can we use mtd
device code exported with GPL? Is there no problem?

> 
> +++ uncommitted/include/linux/mtd/onenand_regs.h  (mode:100644)
> 
> +/* Memory Address Map Translation (Word order) */
> +#define ONENAND_MEMORY_MAP(x)		((x) << 1)
> 
> Is this considered to be a general rule, i.e. is this the 
> only valid way
> to address the chip ? 

To comply with Spec. In Spec. most register addresses are written in word
e.g., Interrupt status registers is 0xf241h
#define ONENAND_REG_INTERRUPT          ONENAND_MEMORY_MAP(0xF241)

> 
> +struct onenand_chip {
> +	void __iomem		*base;
> +	unsigned int		chipsize;
> +	unsigned int		device_id;
> +	unsigned int		version_id;
> +	unsigned int		options;
> 
> Are device_id and version_id necessary for anything else than 
> scan ? If
> no, please remove.
> 

device_id necessary to control DDP chip. But I'm not yet tested with DDP
chip.
version_id is not necessary. removed. 

[-- Attachment #2: onenand-mtd.patch --]
[-- Type: application/octet-stream, Size: 59782 bytes --]

Index: drivers/mtd/Kconfig
===================================================================
--- 19f75ba1af6b4b16744159e62fbb7decab5553ef/drivers/mtd/Kconfig  (mode:100644)
+++ uncommitted/drivers/mtd/Kconfig  (mode:100644)
@@ -261,5 +261,7 @@

 source "drivers/mtd/nand/Kconfig"

+source "drivers/mtd/onenand/Kconfig"
+
 endmenu

Index: drivers/mtd/Makefile
===================================================================
--- 19f75ba1af6b4b16744159e62fbb7decab5553ef/drivers/mtd/Makefile  (mode:100644)
+++ uncommitted/drivers/mtd/Makefile  (mode:100644)
@@ -24,4 +24,4 @@
 nftl-objs              := nftlcore.o nftlmount.o
 inftl-objs             := inftlcore.o inftlmount.o

-obj-y          += chips/ maps/ devices/ nand/
+obj-y          += chips/ maps/ devices/ nand/ onenand/
Index: drivers/mtd/onenand/Kconfig
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Kconfig  (mode:100644)
@@ -0,0 +1,32 @@
+#
+# linux/drivers/mtd/onenand/Kconfig
+#
+
+menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
+	depends on MTD != n && EXPERIMENTAL
+
+config MTD_ONENAND
+	tristate "OneNAND Device Support"
+	depends on MTD
+	help
+	  This enables support for accessing all type of OneNAND flash
+	  devices. For further information see
+	  <http://www.samsung.com/Products/Semiconductor/Flash/OneNAND_TM/index.htm>.
+
+config MTD_ONENAND_VERIFY_WRITE
+	bool "Verify OneNAND page writes"
+	depends on MTD_ONENAND
+	help
+	  This adds an extra check when data is written to the flash. The
+	  OneNAND flash device internally checks only bits transitioning
+	  from 1 to 0. There is a rare possibility that even though the
+	  device thinks the write was successful, a bit could have been
+	  flipped accidentaly due to device wear or something else.
+
+config MTD_ONENAND_OMAP
+	tristate "OneNAND Flash device on OMAP board"
+	depends on ARCH_OMAP && MTD_ONENAND
+	help
+	  Support for OneNAND flash on TI OMAP board.
+
+endmenu
Index: drivers/mtd/onenand/Makefile
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Makefile  (mode:100644)
@@ -0,0 +1,9 @@
+#
+# Makefile for the OneNAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_ONENAND)		+= onenand_base.o
+
+# Board specific.
+obj-$(CONFIG_MTD_ONENAND_OMAP)		+= omap-onenand.o
Index: drivers/mtd/onenand/omap-onenand.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/omap-onenand.c  (mode:100644)
@@ -0,0 +1,179 @@
+/*
+ *  linux/drivers/mtd/onenand/omap-onenand.c
+ *
+ *  Copyright (c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Derived from linux/drivers/mtd/nand/omap-nand-flash.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Overview:
+ *   This is a device driver for the OneNAND flash device for TI OMAP boards.
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/tc.h>
+#include <asm/sizes.h>
+
+#define OMAP_ONENAND_FLASH_START1	OMAP_CS2A_PHYS
+#define OMAP_ONENAND_FLASH_START2	OMAP_CS0_PHYS
+/*
+ * MTD structure for OMAP board
+ */
+static struct mtd_info *omap_onenand_mtd = NULL;
+
+/*
+ * Define partitions for flash devices
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition static_partition[] = {
+	{
+		.name		= "X-Loader + U-Boot",
+		.offset		= 0,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "U-Boot Environment",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= 2 * SZ_1M
+	},
+	{
+		.name		= "filesystem0",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_16M,
+	},
+	{
+		.name		= "filesystem1",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= MTDPART_SIZ_FULL,
+	},
+};
+
+const char *part_probes[] = { "cmdlinepart", NULL,  };
+
+#endif
+
+/* Scan to find existance of the device at base.
+   This also allocates oob and data internal buffers */
+static char onenand_name[] = "onenand";
+
+/*
+ * Main initialization routine
+ */
+static int __init omap_onenand_init (void)
+{
+	struct onenand_chip *this;
+	struct mtd_partition *dynamic_partition = 0;
+	int err = 0;
+
+	/* Allocate memory for MTD device structure and private data */
+	omap_onenand_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct onenand_chip),
+				GFP_KERNEL);
+	if (!omap_onenand_mtd) {
+		printk (KERN_WARNING "Unable to allocate OneNAND MTD device structure.\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	/* Get pointer to private data */
+	this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *) omap_onenand_mtd, 0, sizeof(struct mtd_info) + sizeof(struct onenand_chip));
+
+	/* Link the private data with the MTD structure */
+	omap_onenand_mtd->priv = this;
+
+        /* try the first address */
+	this->base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
+	omap_onenand_mtd->name = onenand_name;
+	if (onenand_scan(omap_onenand_mtd, 1)){
+		/* try the second address */
+		iounmap(this->base);
+		this->base = ioremap(OMAP_ONENAND_FLASH_START2, SZ_128K);
+		if (onenand_scan(omap_onenand_mtd, 1)) {
+			iounmap(this->base);
+                        err = -ENXIO;
+                        goto out_mtd;
+		}
+	}
+
+	/* Register the partitions */
+	switch (omap_onenand_mtd->size) {
+	case SZ_128M:
+	case SZ_64M:
+	case SZ_32M:
+#ifdef CONFIG_MTD_PARTITIONS
+		err = parse_mtd_partitions(omap_onenand_mtd, part_probes,
+					&dynamic_partition, 0);
+		if (err > 0)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					dynamic_partition, err);
+		else if (1)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					static_partition,
+					ARRAY_SIZE(static_partition));
+		else
+#endif
+			err = add_mtd_device(omap_onenand_mtd);
+		if (err)
+			goto out_buf;
+		break;
+
+	default:
+		printk(KERN_WARNING "Unsupported OneNAND device\n");
+		err = -ENXIO;
+		goto out_buf;
+	}
+
+	return 0;
+
+out_buf:
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+out_mtd:
+	kfree(omap_onenand_mtd);
+out:
+	return err;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit omap_onenand_cleanup (void)
+{
+	struct onenand_chip *this = omap_onenand_mtd->priv;
+
+	/* onenand_release frees MTD partitions, MTD structure
+	   and onenand internal buffers */
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+	kfree(omap_onenand_mtd);
+}
+
+module_init(omap_onenand_init);
+module_exit(omap_onenand_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP boards");
Index: drivers/mtd/onenand/onenand_base.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/onenand_base.c  (mode:100644)
@@ -0,0 +1,1464 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_base.c
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+
+/**
+ * onenand_oob_64 - oob info for large (2KB) page
+ */
+static struct nand_oobinfo onenand_oob_64 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 20,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		40, 41, 42, 43, 44,
+		56, 57, 58, 59, 60,
+		},
+	.oobfree	= {
+		{2, 3}, {14, 2}, {18, 3}, {30, 2},
+		{24, 3}, {46, 2}, {40, 3}, {62, 2} }
+};
+
+/**
+ * onenand_oob_32 - oob info for middle (1KB) page
+ */
+static struct nand_oobinfo onenand_oob_32 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 10,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		},
+	.oobfree	= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
+};
+
+static const unsigned char ffchars[] = {
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 16 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 32 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 48 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 64 */
+};
+
+/**
+ * onenand_readw - [OneNAND Interface] Read OneNAND register
+ * @param addr		address to read
+ *
+ * Read OneNAND register
+ */
+static unsigned short onenand_readw(void __iomem *addr)
+{
+	return readw(addr);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Write OneNAND register with value
+ * @param value		value to write
+ * @param addr		address to write
+ *
+ * Write OneNAND register with value
+ */
+static void onenand_writew(unsigned short value, void __iomem *addr)
+{
+	writew(value, addr);
+}
+
+/**
+ * onenand_block_address - [DEFAULT] Get block address
+ * @param device	the device id
+ * @param block		the block
+ * @return		translated block address if DDP, otherwise same
+ *
+ * Setup Start Address 1 Register (F100h)
+ */
+static int onenand_block_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device Flash Core select, NAND Flash Block Address */
+		int dfs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dfs = 1;
+
+		return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1));
+	}
+
+	return block;
+}
+
+/**
+ * onenand_bufferram_address - [DEFAULT] Get bufferram address
+ * @param device	the device id
+ * @param block		the block
+ * @return		set DBS value if DDP, otherwise 0
+ *
+ * Setup Start Address 2 Register (F101h) for DDP
+ */
+static int onenand_bufferram_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device BufferRAM Select */
+		int dbs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dbs = 1;
+
+		return (dbs << ONENAND_DDP_SHIFT);
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_page_address - [DEFAULT] Get page address
+ * @param page		the page address
+ * @param sector	the sector address
+ * @return		combined page and sector address
+ *
+ * Setup Start Address 8 Register (F107h)
+ */
+static int onenand_page_address(int page, int sector)
+{
+	/* Flash Page Address, Flash Sector Address */
+	int fpa, fsa;
+
+	fpa = page & ONENAND_FPA_MASK;
+	fsa = sector & ONENAND_FSA_MASK;
+
+	return ((fpa << ONENAND_FPA_SHIFT) | fsa);
+}
+
+/**
+ * onenand_buffer_address - [DEFAULT] Get buffer address
+ * @param dataram1	DataRAM index
+ * @param sectors	the sector address
+ * @param count		the number of sectors
+ * @return		the start buffer value
+ *
+ * Setup Start Buffer Register (F200h)
+ */
+static int onenand_buffer_address(int dataram1, int sectors, int count)
+{
+	int bsa, bsc;
+
+	/* BufferRAM Sector Address */
+	bsa = sectors & ONENAND_BSA_MASK;
+
+	if (dataram1)
+		bsa |= ONENAND_BSA_DATARAM1;	/* DataRAM1 */
+	else
+		bsa |= ONENAND_BSA_DATARAM0;	/* DataRAM0 */
+
+	/* BufferRAM Sector Count */
+	bsc = count & ONENAND_BSC_MASK;
+
+	return ((bsa << ONENAND_BSA_SHIFT) | bsc);
+}
+
+/**
+ * onenand_command - [DEFAULT] Send command to OneNAND device
+ * @param mtd		MTD device structure
+ * @param cmd		the command to be sent
+ * @param addr		offset to read from or write to
+ * @param len		number of bytes to read or write
+ *
+ * Send command to OneNAND device. This function is used for middle/large page
+ * devices (1KB/2KB Bytes per page)
+ */
+static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int value, readcmd = 0;
+	int block, page;
+	/* Now we use page size operation */
+	int sectors = 4, count = 4;
+
+	/* Address translation */
+	switch (cmd) {
+	case ONENAND_CMD_UNLOCK:
+	case ONENAND_CMD_LOCK:
+	case ONENAND_CMD_LOCK_TIGHT:
+		block = -1;
+		page = -1;
+		break;
+
+	case ONENAND_CMD_ERASE:
+	case ONENAND_CMD_BUFFERRAM:
+		block = (int) (addr >> this->erase_shift);
+		page = -1;
+		break;
+
+	default:
+		block = (int) (addr >> this->erase_shift);
+		page = (int) (addr >> this->page_shift);
+		page &= this->page_mask;
+		break;
+	}
+
+	/* NOTE: The setting order of the registers is very important! */
+	if (cmd == ONENAND_CMD_BUFFERRAM) {
+		/* Select DataRAM for DDP */
+		value = onenand_bufferram_address(this->device_id, block);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
+
+		/* Switch to the next data buffer */
+		ONENAND_SET_NEXT_BUFFERRAM(this);
+
+		return 0;
+	}
+
+	if (block != -1) {
+		/* Write 'DFS, FBA' of Flash */
+		value = onenand_block_address(this->device_id, block);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
+	}
+
+	if (page != -1) {
+		int dataram;
+
+		switch (cmd) {
+		case ONENAND_CMD_READ:
+		case ONENAND_CMD_READOOB:
+			dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+			readcmd = 1;
+			break;
+
+		default:
+			dataram = ONENAND_CURRENT_BUFFERRAM(this);
+			break;
+		}
+
+		/* Write 'FPA, FSA' of Flash */
+		value = onenand_page_address(page, sectors);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8);
+
+		/* Write 'BSA, BSC' of DataRAM */
+		value = onenand_buffer_address(dataram, sectors, count);
+		this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
+			
+		if (readcmd) {
+			/* Select DataRAM for DDP */
+			value = onenand_bufferram_address(this->device_id, block);
+			this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
+		}
+	}
+
+	/* Interrupt clear */
+	this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
+
+	/* Write command */
+	this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
+
+	return 0;
+}
+
+/**
+ * onenand_wait - [DEFAULT] wait until the command is done
+ * @param mtd		MTD device structure
+ * @param state		state to select the max. timeout value
+ *
+ * Wait for command done. This applies to all OneNAND command
+ * Read can take up to 30us, erase up to 2ms and program up to 350us
+ * according to general OneNAND specs
+ */
+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+	struct onenand_chip * this = mtd->priv;
+	unsigned long timeout;
+	unsigned int flags = ONENAND_INT_MASTER;
+	unsigned int interrupt = 0;
+	unsigned int ctrl, ecc;
+
+	/* The 10 msec is enough */
+	timeout = jiffies + msecs_to_jiffies(10);
+	while (time_before(jiffies, timeout)) {
+		interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
+
+		if (interrupt & flags)
+			break;
+
+		if (state != FL_READING)
+			cond_resched();
+	}
+	/* To get correct interrupt status in timeout case */
+	interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
+
+	ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
+
+	if (ctrl & ONENAND_CTRL_ERROR) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (ctrl & ONENAND_CTRL_LOCK) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (interrupt & ONENAND_INT_READ) {
+		ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
+		if (ecc & ONENAND_ECC_2BIT_ALL) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x", ecc);
+			return -EBADMSG;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @return		offset given area
+ *
+ * Return BufferRAM offset given area
+ */
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == ONENAND_DATARAM)
+			return mtd->oobblock;
+		if (area == ONENAND_SPARERAM)
+			return mtd->oobsize;
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Read the BufferRAM area
+ */
+static int onenand_read_bufferram(struct mtd_info *mtd, int area,
+		unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	memcpy(buffer, bufferram + offset, count);
+
+	return 0;
+}
+
+/**
+ * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Write the BufferRAM area
+ */
+static int onenand_write_bufferram(struct mtd_info *mtd, int area,
+		const unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	memcpy(bufferram + offset, buffer, count);
+
+	return 0;
+}
+
+/**
+ * onenand_check_bufferram - [GENERIC] Check BufferRAM information
+ * @param mtd		MTD data structure
+ * @param addr		address to check
+ * @return		1 if there are valid data, otherwise 0 
+ *
+ * Check bufferram if there is data we required
+ */
+static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
+{
+	struct onenand_chip *this = mtd->priv;
+	int block, page;
+	int i;
+	
+	block = (int) (addr >> this->erase_shift);
+	page = (int) (addr >> this->page_shift);
+	page &= this->page_mask;
+
+	i = ONENAND_CURRENT_BUFFERRAM(this);
+
+	/* Is there valid data? */
+	if (this->bufferram[i].block == block &&
+	    this->bufferram[i].page == page &&
+	    this->bufferram[i].valid)
+		return 1;
+
+	return 0;
+}
+
+/**
+ * onenand_update_bufferram - [GENERIC] Update BufferRAM information
+ * @param mtd		MTD data structure
+ * @param addr		address to update
+ * @param valid		valid flag
+ *
+ * Update BufferRAM information
+ */
+static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
+		int valid)
+{
+	struct onenand_chip *this = mtd->priv;
+	int block, page;
+	int i;
+	
+	block = (int) (addr >> this->erase_shift);
+	page = (int) (addr >> this->page_shift);
+	page &= this->page_mask;
+
+	/* Invalidate BufferRAM */
+	for (i = 0; i < MAX_BUFFERRAM; i++) {
+		if (this->bufferram[i].block == block &&
+		    this->bufferram[i].page == page)
+			this->bufferram[i].valid = 0;
+	}
+
+	/* Update BufferRAM */
+	i = ONENAND_CURRENT_BUFFERRAM(this);
+	this->bufferram[i].block = block;
+	this->bufferram[i].page = page;
+	this->bufferram[i].valid = valid;
+
+	return 0;
+}
+
+/**
+ * onenand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd		MTD device structure
+ * @param new_state	the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+static void onenand_get_device(struct mtd_info *mtd, int new_state)
+{
+	struct onenand_chip *this = mtd->priv;
+	DECLARE_WAITQUEUE(wait, current);
+
+	/*
+	 * Grab the lock and see if the device is available
+	 */
+	while (1) {
+		spin_lock(&this->chip_lock);
+		if (this->state == FL_READY) {
+			this->state = new_state;
+			spin_unlock(&this->chip_lock);
+			break;
+		}
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&this->wq, &wait);
+		spin_unlock(&this->chip_lock);
+		schedule();
+		remove_wait_queue(&this->wq, &wait);
+	}
+}
+
+/**
+ * onenand_release_device - [GENERIC] release chip
+ * @param mtd		MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+static void onenand_release_device(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	/* Release the chip */
+	spin_lock(&this->chip_lock);
+	this->state = FL_READY;
+	wake_up(&this->wq);
+	spin_unlock(&this->chip_lock);
+}
+
+/**
+ * onenand_read_ecc - [MTD Interface] Read data with ECC
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ * @param oob_buf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND read with ECC
+ */
+static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf,
+	u_char *oob_buf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, column;
+	int thislen;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Do not allow reads past end of device */
+	if ((from + len) > mtd->size) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: Attempt read beyond end of device\n");
+		*retlen = 0;
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_READING);
+
+	/* TODO handling oob */
+
+	while (read < len) {
+		thislen = min_t(int, mtd->oobblock, len - read);
+
+		column = from & (mtd->oobblock - 1);
+		if (column + thislen > mtd->oobblock)
+			thislen = mtd->oobblock - column;
+
+		if (!onenand_check_bufferram(mtd, from)) {
+			this->command(mtd, ONENAND_CMD_READ, from, mtd->oobblock);
+
+			ret = this->wait(mtd, FL_READING);
+			/* First copy data and check return value for ECC handling */
+			onenand_update_bufferram(mtd, from, 1);
+		}
+
+		this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
+
+		read += thislen;
+
+		if (read == len)
+			break;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: read failed = %d\n", ret);
+			goto out;
+		}
+
+		from += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	/*
+	 * Return success, if no ECC failures, else -EBADMSG
+	 * fs driver will take care of that, because
+	 * retlen == desired len and result == -EBADMSG
+	 */
+	*retlen = read;
+	return ret;
+}
+
+/**
+ * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
+*/
+static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * OneNAND read out-of-band data from the spare area
+ */
+static int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, thislen, column;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Initialize return length value */
+	*retlen = 0;
+
+	/* Do not allow reads past end of device */
+	if (unlikely((from + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_READING);
+
+	column = from & (mtd->oobsize - 1);
+
+	while (read < len) {
+		thislen = mtd->oobsize - column;
+		thislen = min_t(int, thislen, len);
+
+		this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+
+		onenand_update_bufferram(mtd, from, 0);
+
+		ret = this->wait(mtd, FL_READING);
+		/* First copy data and check return value for ECC handling */
+
+		this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
+
+		read += thislen;
+
+		if (read == len)
+			break;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = %d\n", ret);
+			goto out;
+		}
+
+		buf += thislen;
+
+		/* Read more? */
+		if (read < len) {
+			/* Page size */
+			from += mtd->oobblock;
+			column = 0;
+		}
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = read;
+	return ret;
+}
+
+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd		MTD device structure
+ * @param buf		the databuffer to verify
+ * @param block		block address
+ * @param page		page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char *buf,
+	loff_t addr, int block, int page)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *dataram0, *dataram1;
+	int ret = 0;
+
+	this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock);
+
+	ret = this->wait(mtd, FL_READING);
+	if (ret)
+		return ret;
+
+	onenand_update_bufferram(mtd, addr, 1);
+
+	/* Check, if the two dataram areas are same */
+	dataram0 = this->base + ONENAND_DATARAM;
+	dataram1 = dataram0 + mtd->oobblock;
+
+	if (memcmp(dataram0, dataram1, mtd->oobblock))
+		return -EBADMSG;
+	
+	return 0;
+}
+#else
+#define onenand_verify_page(...)	(0)
+#endif
+
+#define NOTALIGNED(x)	((x & (mtd->oobblock - 1)) != 0)
+
+/**
+ * onenand_write_ecc - [MTD Interface] OneNAND write with ECC
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with ECC
+ */
+static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int written = 0;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobblock, len - written);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen);
+		this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		onenand_update_bufferram(mtd, to, 1);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: write filaed %d\n", ret);
+			goto out;
+		}
+
+		written += thislen;
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return ret;
+}
+
+/**
+ * onenand_write - [MTD Interface] compability function for onenand_write_ecc
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * This function simply calls onenand_write_ecc
+ * with oob buffer and oobsel = NULL
+ */
+static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * OneNAND write out-of-band
+ */
+static int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int column, status;
+	int written = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobsize, len - written);
+
+		column = to & (mtd->oobsize - 1);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
+
+		this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
+		this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
+
+		this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+
+		onenand_update_bufferram(mtd, to, 0);
+
+		status = this->wait(mtd, FL_WRITING);
+		if (status)
+			goto out;
+
+		written += thislen;
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return 0;
+}
+
+/**
+ * onenand_writev_ecc - [MTD Interface] write with iovec with ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with iovec with ecc
+ */
+static int onenand_writev_ecc(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned char buffer[mtd->oobblock], *pbuf;
+	size_t total_len, len;
+	int i, written = 0;
+	int ret = 0;
+
+	/* Preset written len for early exit */
+	*retlen = 0;
+
+	/* Calculate total length of data */
+	total_len = 0;
+	for (i = 0; i < count; i++)
+		total_len += vecs[i].iov_len;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_writev_ecc: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
+
+	/* Do not allow write past end of the device */
+	if (unlikely((to + total_len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempted write past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(total_len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* TODO handling oob */
+	
+	/* Loop until all keve's data has been written */
+	len = 0;
+	while (count) {
+		pbuf = buffer;
+		/* 
+		 * If the given tuple is >= pagesize then
+		 * write it out from the iov
+		 */
+		if ((vecs->iov_len - len) >= mtd->oobblock) {
+			pbuf = vecs->iov_base + len;
+
+			len += mtd->oobblock;
+
+			/* Check, if we have to switch to the next tuple */
+			if (len >= (int) vecs->iov_len) {
+				vecs++;
+				len = 0;
+				count--;
+			}
+		} else {
+			int cnt = 0, thislen;
+			while (cnt < mtd->oobblock) {
+				thislen = min_t(int, mtd->oobblock - cnt, vecs->iov_len - len);
+				memcpy(buffer + cnt, vecs->iov_base + len, thislen);
+				cnt += thislen;
+				len += thislen;
+
+				/* Check, if we have to switch to the next tuple */
+				if (len >= (int) vecs->iov_len) {
+					vecs++;
+					len = 0;
+					count--;
+				}
+			}
+		}
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->write_bufferram(mtd, ONENAND_DATARAM, pbuf, 0, mtd->oobblock);
+		this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		onenand_update_bufferram(mtd, to, 1);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: write failed %d\n", ret);
+			goto out;
+		}
+
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) pbuf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		written += mtd->oobblock;
+
+		to += mtd->oobblock;
+	}
+
+out:
+	/* Deselect and wakt up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+
+	return 0;
+}
+
+/**
+ * onenand_writev - [MTD Interface] compabilty function for onenand_writev_ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ *
+ * OneNAND write with kvec. This just calls the ecc function
+ */
+static int onenand_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen)
+{
+	return onenand_writev_ecc(mtd, vecs, count, to, retlen, NULL, NULL);
+}
+
+/**
+ * onenand_erase - [MTD Interface] erase block(s)
+ * @param mtd		MTD device structure
+ * @param instr		erase instruction
+ *
+ * Erase one ore more blocks
+ */
+static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned int block_size;
+	loff_t addr;
+	int len;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
+
+	block_size = (1 << this->erase_shift);
+
+	/* Start address must align on block boundary */
+	if (unlikely(instr->addr & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n");
+		return -EINVAL;
+	}
+
+	/* Length must align on block boundary */
+	if (unlikely(instr->len & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n");
+		return -EINVAL;
+	}
+
+	/* Do not allow erase past end of device */
+	if (unlikely((instr->len + instr->addr) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n");
+		return -EINVAL;
+	}
+
+	instr->fail_addr = 0xffffffff;
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_ERASING);
+
+	/* Loop throught the pages */
+	len = instr->len;
+	addr = instr->addr;
+
+	instr->state = MTD_ERASING;
+
+	while (len) {
+
+		/* TODO Check badblock */
+
+		this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
+
+		ret = this->wait(mtd, FL_ERASING);
+		/* Check, if it is write protected */
+		if (ret) {
+			if (ret == -EPERM)
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Device is write protected!!!\n");
+			else
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift));
+			instr->state = MTD_ERASE_FAILED;
+			instr->fail_addr = addr;
+			goto erase_exit;
+		}
+
+		len -= block_size;
+		addr += block_size;
+	}
+
+	instr->state = MTD_ERASE_DONE;
+
+erase_exit:
+
+	ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+	/* Do call back function */
+	if (!ret)
+		mtd_erase_callback(instr);
+
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	return ret;
+}
+
+/**
+ * onenand_sync - [MTD Interface] sync
+ * @param mtd		MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+static void onenand_sync(struct mtd_info *mtd)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_SYNCING);
+
+	/* Release it and go back */
+	onenand_release_device(mtd);
+}
+
+/**
+ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/*
+	 * TODO 
+	 * 1. Bad block table (BBT)
+	 *   -> using NAND BBT to support JFFS2
+	 * 2. Bad block management (BBM)
+	 *   -> bad block replace scheme
+	 *
+	 * Currently we do nothing
+	 */
+	return 0;
+}
+
+/**
+ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/* see above */
+	return 0;
+}
+
+/**
+ * onenand_unlock - [MTD Interface] Unlock block(s)
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ * @param len		number of bytes to unlock
+ *
+ * Unlock one or more blocks
+ */
+static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int start, end, block, value, status;
+
+	start = ofs >> this->erase_shift;
+	end = len >> this->erase_shift;
+
+	/* Continuous lock scheme */
+	if (this->options & ONENAND_CONT_LOCK) {
+		/* Set start block address */
+		this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Set end block address */
+		this->write_word(end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Check lock status */
+		status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "wp status = 0x%x\n", status);
+
+		return 0;
+	}
+
+	/* Block lock scheme */
+	for (block = start; block < end; block++) {
+		/* Set start block address */
+		this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Set block address for read block status */
+		value = onenand_block_address(this->device_id, block);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
+
+		/* Check lock status */
+		status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
+	}
+	
+	return 0;
+}
+
+/**
+ * onenand_print_device_info - Print device ID
+ * @param device        device ID
+ *
+ * Print device ID
+ */
+static void onenand_print_device_info(int device)
+{
+        int vcc, demuxed, ddp, density;
+
+        vcc = device & ONENAND_DEVICE_VCC_MASK;
+        demuxed = device & ONENAND_DEVICE_IS_DEMUX;
+        ddp = device & ONENAND_DEVICE_IS_DDP;
+        density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+        printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
+                demuxed ? "" : "Muxed ",
+                ddp ? "(DDP)" : "",
+                (16 << density),
+                vcc ? "2.65/3.3" : "1.8",
+                device);
+}
+
+static const struct onenand_manufacturers onenand_manuf_ids[] = {
+        {ONENAND_MFR_SAMSUNG, "Samsung"},
+        {ONENAND_MFR_UNKNOWN, "Unknown"}
+};
+
+/**
+ * onenand_check_maf - Check manufacturer ID
+ * @param manuf         manufacturer ID
+ *
+ * Check manufacturer ID
+ */
+static int onenand_check_maf(int manuf)
+{
+        int i;
+
+        for (i = 0; onenand_manuf_ids[i].id; i++) {
+                if (manuf == onenand_manuf_ids[i].id)
+                        break;
+        }
+
+        printk(KERN_DEBUG "OneNAND Manufacturer: %s\n",
+                onenand_manuf_ids[i].name);
+
+        return (i != ONENAND_MFR_UNKNOWN);
+}
+
+/**
+ * onenand_probe - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd		MTD device structure
+ *
+ * OneNAND detection method:
+ *   Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	int bram_maf_id, bram_dev_id, maf_id, dev_id;
+	int version_id;
+	int density;
+
+	/* Send the command for reading device ID from BootRAM */
+	this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from BootRAM */
+	bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
+	bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
+
+	/* Check manufacturer ID */
+	if (onenand_check_maf(bram_maf_id))
+		return -ENXIO;
+
+	/* Reset OneNAND to read default register values */
+	this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from Register */
+	maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
+	dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
+
+	/* Check OneNAND device */
+	if (maf_id != bram_maf_id || dev_id != bram_dev_id)
+		return -ENXIO;
+
+	/* Flash device information */
+	onenand_print_device_info(dev_id);
+	this->device_id = dev_id;
+
+	density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+	this->chipsize = (16 << density) << 20;
+
+	/* OneNAND page size & block size */
+	/* The data buffer size is equal to page size */
+	mtd->oobblock = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+	mtd->oobsize = mtd->oobblock >> 5;
+	/* Pagers per block is always 64 in OneNAND */
+	mtd->erasesize = mtd->oobblock << 6;
+
+	this->erase_shift = ffs(mtd->erasesize) - 1;
+	this->page_shift = ffs(mtd->oobblock) - 1;
+	this->ppb_shift = (this->erase_shift - this->page_shift);
+	this->page_mask = (mtd->erasesize / mtd->oobblock) - 1;
+
+	/* REVIST: Multichip handling */
+
+	mtd->size = this->chipsize;
+
+	/* Version ID */
+	version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
+	printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id);
+
+	/* Lock scheme */
+	if (density <= ONENAND_DEVICE_DENSITY_512Mb &&
+	    !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) {
+		printk(KERN_INFO "Lock scheme is Continues Lock\n");
+		this->options |= ONENAND_CONT_LOCK;
+	}
+	
+	return 0;
+}
+
+
+/**
+ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
+ * @param mtd		MTD device structure
+ * @param maxchips	Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values.
+ */
+int onenand_scan(struct mtd_info *mtd, int maxchips)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (!this->read_word)
+		this->read_word = onenand_readw;
+	if (!this->write_word)
+		this->write_word = onenand_writew;
+
+	if (!this->command)
+		this->command = onenand_command;
+	if (!this->wait)
+		this->wait = onenand_wait;
+
+	if (!this->read_bufferram)
+		this->read_bufferram = onenand_read_bufferram;
+	if (!this->write_bufferram)
+		this->write_bufferram = onenand_write_bufferram;
+
+	if (onenand_probe(mtd))
+		return -ENXIO;
+
+	this->state = FL_READY;
+	init_waitqueue_head(&this->wq);
+	spin_lock_init(&this->chip_lock);
+
+	switch (mtd->oobsize) {
+	case 64:
+		this->autooob = &onenand_oob_64;
+		break;
+
+	case 32:
+		this->autooob = &onenand_oob_32;
+		break;
+
+	default:
+		printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
+			mtd->oobsize);
+		/* To prevent kernel oops */
+		this->autooob = &onenand_oob_32;
+		break;
+	}
+
+	memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
+	
+	/* Fill in remaining MTD driver data */
+	mtd->type = MTD_NANDFLASH;
+	mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
+	mtd->ecctype = MTD_ECC_SW;
+	mtd->erase = onenand_erase;
+	mtd->point = NULL;
+	mtd->unpoint = NULL;
+	mtd->read = onenand_read;
+	mtd->write = onenand_write;
+	mtd->read_ecc = onenand_read_ecc;
+	mtd->write_ecc = onenand_write_ecc;
+	mtd->read_oob = onenand_read_oob;
+	mtd->write_oob = onenand_write_oob;
+	mtd->readv = NULL;
+	mtd->readv_ecc = NULL;
+	mtd->writev = onenand_writev;
+	mtd->writev_ecc = onenand_writev_ecc;
+	mtd->sync = onenand_sync;
+	mtd->lock = NULL;
+	mtd->unlock = onenand_unlock;
+	mtd->suspend = NULL;
+	mtd->resume = NULL;
+	mtd->block_isbad = onenand_block_isbad;
+	mtd->block_markbad = onenand_block_markbad;
+	mtd->owner = THIS_MODULE;
+
+	/* Unlock whole block */
+	mtd->unlock(mtd, 0x0, this->chipsize);
+
+	return 0;
+}
+
+/**
+ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
+ * @param mtd		MTD device structure
+ */
+void onenand_release(struct mtd_info *mtd)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+	/* Deregister partitions */
+	del_mtd_partitions (mtd);
+#endif
+	/* Deregister the device */
+	del_mtd_device (mtd);
+}
+
+EXPORT_SYMBOL(onenand_scan);
+EXPORT_SYMBOL(onenand_release);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Generic OneNAND flash driver code");
Index: include/linux/mtd/onenand.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand.h  (mode:100644)
@@ -0,0 +1,137 @@
+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand_regs.h>
+
+#define MAX_BUFFERRAM		2
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan(struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release(struct mtd_info *mtd);
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_UNLOCKING,
+	FL_LOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param block		block address in BufferRAM
+ * @param page		page address in BufferRAM
+ * @param valid		valid flag
+ */
+struct onenand_bufferram {
+	int block;
+	int page;
+	int valid;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param bufferam_index	[INTERN] BufferRAM index
+ * @param bufferam	[INTERN] BufferRAM info
+ * @param readw		[REPLACEABLE] hardware specific function for read short
+ * @param writew	[REPLACEABLE] hardware specific function for write short
+ * @param command	[REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem		*base;
+	unsigned int		chipsize;
+	unsigned int		device_id;
+	unsigned int		options;
+
+	unsigned int		erase_shift;
+	unsigned int		page_shift;
+	unsigned int		ppb_shift;	/* Pages per block shift */
+	unsigned int		page_mask;
+
+	unsigned int		bufferram_index;
+	struct onenand_bufferram	bufferram[MAX_BUFFERRAM];
+
+	int (*command)(struct mtd_info *mtd, int cmd, loff_t address, size_t len);
+	int (*wait)(struct mtd_info *mtd, int state);
+	int (*read_bufferram)(struct mtd_info *mtd, int area,
+			unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram)(struct mtd_info *mtd, int area,
+			const unsigned char *buffer, int offset, size_t count);
+	unsigned short (*read_word)(void __iomem *addr);
+	void (*write_word)(unsigned short value, void __iomem *addr);
+
+	spinlock_t		chip_lock;
+	wait_queue_head_t	wq;
+	onenand_state_t		state;
+
+	struct nand_oobinfo	*autooob;
+
+	void			*priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK		(0x0001)
+
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG	0xec
+#define ONENAND_MFR_UNKNOWN	0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+        int id;
+        char *name;
+};
+
+#endif	/* __LINUX_MTD_ONENAND_H */
Index: include/linux/mtd/onenand_regs.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand_regs.h  (mode:100644)
@@ -0,0 +1,167 @@
+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x3f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL		(1 << 12)
+#define ONENAND_SYS_CFG1_BL		(1 << 9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+
+#endif	/* __ONENAND_REG_H */

RE: [PATCH] OneNAND MTD support

[Thomas Gleixner]

On Mon, 2005-07-11 at 10:53 +0900, Kyungmin Park wrote:
> It's derived from omap-nand-flash.c, But it's not sended to MTD.
> OK. I done

I removed the redundant dependencies in drivers/mtd/nand and
drivers/mtd/maps too.

> > 
> > +EXPORT_SYMBOL(onenand_scan);
> > +EXPORT_SYMBOL(onenand_release);
> > 
> > Would you mind to change those exports to EXPORT_SYMBOL_GPL ?
> 
> In fact I not sure and also don't know license issue. 
> If we develop the some commercial mtd user software then can we use mtd
> device code exported with GPL? Is there no problem?

User space software is not concerned of kernel licences.

If you talk about a proprietary closed source kernel module which needs
those exports, you are stepping into a legal grey area regardless of the
exports style. I don't see a point where it makes sense to have a closed
source board driver, as it just initializes a data structure and calls
generic handling code. 


> > Are device_id and version_id necessary for anything else than 
> > scan ? If
> > no, please remove.
> device_id necessary to control DDP chip. But I'm not yet tested with DDP
> chip.

Ok.

Some nitpicks though

+	/* The 10 msec is enough */
+	timeout = jiffies + msecs_to_jiffies(10);
+	while (time_before(jiffies, timeout)) {

On CPU's which have HZ=100 (1 jiffy == 10ms) this might be critical, as
you might set the timeout immidiately before the timer interrupt
happens. Using a 20ms timeout will keep you on the safe side in any case


Please clean up your includes to avoid redundant includes of header
files.

tglx

RE: [PATCH] OneNAND MTD support

[Kyungmin Park]

> 
> > > 
> > > +EXPORT_SYMBOL(onenand_scan);
> > > +EXPORT_SYMBOL(onenand_release);
> > > 
> > > Would you mind to change those exports to EXPORT_SYMBOL_GPL ?
> > 
> > In fact I not sure and also don't know license issue. 
> > If we develop the some commercial mtd user software then 
> can we use mtd
> > device code exported with GPL? Is there no problem?
> 
> User space software is not concerned of kernel licences.
> 
> If you talk about a proprietary closed source kernel module 
> which needs
> those exports, you are stepping into a legal grey area 
> regardless of the
> exports style. I don't see a point where it makes sense to 
> have a closed
> source board driver, as it just initializes a data structure and calls
> generic handling code. 
> 

OK
 
> 
> Some nitpicks though
> 
> +	/* The 10 msec is enough */
> +	timeout = jiffies + msecs_to_jiffies(10);
> +	while (time_before(jiffies, timeout)) {
> 
> On CPU's which have HZ=100 (1 jiffy == 10ms) this might be 
> critical, as
> you might set the timeout immidiately before the timer interrupt
> happens. Using a 20ms timeout will keep you on the safe side 
> in any case

No problem.

> 
> 
> Please clean up your includes to avoid redundant includes of header
> files.

which one do you mean?
Are there not required header file?


Regards

Kyungmin Park.

RE: [PATCH] OneNAND MTD support

[Thomas Gleixner]

On Mon, 2005-07-11 at 17:30 +0900, Kyungmin Park wrote:
> > Please clean up your includes to avoid redundant includes of header
> > files.
> 
> which one do you mean?
> Are there not required header file?

in omap-onenand.c  

+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>

Same in onenand_base.c


in onenand.h you have:

+#include <linux/config.h>
----------^^^^^^^^^^^^^^^^
Not needed, as your header does not contain CONFIG_XXX dependend stuff

+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/mtd/mtd.h>
----------^^^^^^^^^^^^^^^^^
Already included above

+#include <linux/mtd/onenand_regs.h>

tglx

RE: [PATCH] OneNAND MTD support

[Kyungmin Park]

[-- Attachment #1: Type: text/plain, Size: 397 bytes --]

> in onenand.h you have:

> +#include <linux/config.h>
> ----------^^^^^^^^^^^^^^^^
> Not needed, as your header does not contain CONFIG_XXX dependend stuff

>+#include <linux/kernel.h>
>+#include <linux/spinlock.h>
>+#include <linux/mtd/mtd.h>
>----------^^^^^^^^^^^^^^^^^
>Already included above

>+#include <linux/mtd/onenand_regs.h>

OK.

Is there another issue? :)

Regards

Kyungmin Park




[-- Attachment #2: onenand-mtd.patch --]
[-- Type: application/octet-stream, Size: 59671 bytes --]

Index: drivers/mtd/Kconfig
===================================================================
--- 19f75ba1af6b4b16744159e62fbb7decab5553ef/drivers/mtd/Kconfig  (mode:100644)
+++ uncommitted/drivers/mtd/Kconfig  (mode:100644)
@@ -261,5 +261,7 @@

 source "drivers/mtd/nand/Kconfig"

+source "drivers/mtd/onenand/Kconfig"
+
 endmenu

Index: drivers/mtd/Makefile
===================================================================
--- 19f75ba1af6b4b16744159e62fbb7decab5553ef/drivers/mtd/Makefile  (mode:100644)
+++ uncommitted/drivers/mtd/Makefile  (mode:100644)
@@ -24,4 +24,4 @@
 nftl-objs              := nftlcore.o nftlmount.o
 inftl-objs             := inftlcore.o inftlmount.o

-obj-y          += chips/ maps/ devices/ nand/
+obj-y          += chips/ maps/ devices/ nand/ onenand/
Index: drivers/mtd/onenand/Kconfig
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Kconfig  (mode:100644)
@@ -0,0 +1,32 @@
+#
+# linux/drivers/mtd/onenand/Kconfig
+#
+
+menu "OneNAND Flash Device Drivers (EXPERIMENTAL)"
+	depends on MTD != n && EXPERIMENTAL
+
+config MTD_ONENAND
+	tristate "OneNAND Device Support"
+	depends on MTD
+	help
+	  This enables support for accessing all type of OneNAND flash
+	  devices. For further information see
+	  <http://www.samsung.com/Products/Semiconductor/Flash/OneNAND_TM/index.htm>.
+
+config MTD_ONENAND_VERIFY_WRITE
+	bool "Verify OneNAND page writes"
+	depends on MTD_ONENAND
+	help
+	  This adds an extra check when data is written to the flash. The
+	  OneNAND flash device internally checks only bits transitioning
+	  from 1 to 0. There is a rare possibility that even though the
+	  device thinks the write was successful, a bit could have been
+	  flipped accidentaly due to device wear or something else.
+
+config MTD_ONENAND_OMAP
+	tristate "OneNAND Flash device on OMAP board"
+	depends on ARCH_OMAP && MTD_ONENAND
+	help
+	  Support for OneNAND flash on TI OMAP board.
+
+endmenu
Index: drivers/mtd/onenand/Makefile
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/Makefile  (mode:100644)
@@ -0,0 +1,9 @@
+#
+# Makefile for the OneNAND MTD
+#
+
+# Core functionality.
+obj-$(CONFIG_MTD_ONENAND)		+= onenand_base.o
+
+# Board specific.
+obj-$(CONFIG_MTD_ONENAND_OMAP)		+= omap-onenand.o
Index: drivers/mtd/onenand/omap-onenand.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/omap-onenand.c  (mode:100644)
@@ -0,0 +1,178 @@
+/*
+ *  linux/drivers/mtd/onenand/omap-onenand.c
+ *
+ *  Copyright (c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Derived from linux/drivers/mtd/nand/omap-nand-flash.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Overview:
+ *   This is a device driver for the OneNAND flash device for TI OMAP boards.
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/tc.h>
+#include <asm/sizes.h>
+
+#define OMAP_ONENAND_FLASH_START1	OMAP_CS2A_PHYS
+#define OMAP_ONENAND_FLASH_START2	OMAP_CS0_PHYS
+/*
+ * MTD structure for OMAP board
+ */
+static struct mtd_info *omap_onenand_mtd = NULL;
+
+/*
+ * Define partitions for flash devices
+ */
+
+#ifdef CONFIG_MTD_PARTITIONS
+static struct mtd_partition static_partition[] = {
+	{
+		.name		= "X-Loader + U-Boot",
+		.offset		= 0,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "U-Boot Environment",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_128K,
+		.mask_flags	= MTD_WRITEABLE	/* force read-only */
+ 	},
+	{
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= 2 * SZ_1M
+	},
+	{
+		.name		= "filesystem0",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_16M,
+	},
+	{
+		.name		= "filesystem1",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= MTDPART_SIZ_FULL,
+	},
+};
+
+const char *part_probes[] = { "cmdlinepart", NULL,  };
+
+#endif
+
+/* Scan to find existance of the device at base.
+   This also allocates oob and data internal buffers */
+static char onenand_name[] = "onenand";
+
+/*
+ * Main initialization routine
+ */
+static int __init omap_onenand_init (void)
+{
+	struct onenand_chip *this;
+	struct mtd_partition *dynamic_partition = 0;
+	int err = 0;
+
+	/* Allocate memory for MTD device structure and private data */
+	omap_onenand_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct onenand_chip),
+				GFP_KERNEL);
+	if (!omap_onenand_mtd) {
+		printk (KERN_WARNING "Unable to allocate OneNAND MTD device structure.\n");
+		err = -ENOMEM;
+		goto out;
+	}
+
+	/* Get pointer to private data */
+	this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
+
+	/* Initialize structures */
+	memset((char *) omap_onenand_mtd, 0, sizeof(struct mtd_info) + sizeof(struct onenand_chip));
+
+	/* Link the private data with the MTD structure */
+	omap_onenand_mtd->priv = this;
+
+        /* try the first address */
+	this->base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
+	omap_onenand_mtd->name = onenand_name;
+	if (onenand_scan(omap_onenand_mtd, 1)){
+		/* try the second address */
+		iounmap(this->base);
+		this->base = ioremap(OMAP_ONENAND_FLASH_START2, SZ_128K);
+		if (onenand_scan(omap_onenand_mtd, 1)) {
+			iounmap(this->base);
+                        err = -ENXIO;
+                        goto out_mtd;
+		}
+	}
+
+	/* Register the partitions */
+	switch (omap_onenand_mtd->size) {
+	case SZ_128M:
+	case SZ_64M:
+	case SZ_32M:
+#ifdef CONFIG_MTD_PARTITIONS
+		err = parse_mtd_partitions(omap_onenand_mtd, part_probes,
+					&dynamic_partition, 0);
+		if (err > 0)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					dynamic_partition, err);
+		else if (1)
+			err = add_mtd_partitions(omap_onenand_mtd,
+					static_partition,
+					ARRAY_SIZE(static_partition));
+		else
+#endif
+			err = add_mtd_device(omap_onenand_mtd);
+		if (err)
+			goto out_buf;
+		break;
+
+	default:
+		printk(KERN_WARNING "Unsupported OneNAND device\n");
+		err = -ENXIO;
+		goto out_buf;
+	}
+
+	return 0;
+
+out_buf:
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+out_mtd:
+	kfree(omap_onenand_mtd);
+out:
+	return err;
+}
+
+/*
+ * Clean up routine
+ */
+static void __exit omap_onenand_cleanup (void)
+{
+	struct onenand_chip *this = omap_onenand_mtd->priv;
+
+	/* onenand_release frees MTD partitions, MTD structure
+	   and onenand internal buffers */
+	onenand_release(omap_onenand_mtd);
+	iounmap(this->base);
+	kfree(omap_onenand_mtd);
+}
+
+module_init(omap_onenand_init);
+module_exit(omap_onenand_cleanup);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP boards");
Index: drivers/mtd/onenand/onenand_base.c
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/drivers/mtd/onenand/onenand_base.c  (mode:100644)
@@ -0,0 +1,1462 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_base.c
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/io.h>
+
+/**
+ * onenand_oob_64 - oob info for large (2KB) page
+ */
+static struct nand_oobinfo onenand_oob_64 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 20,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		40, 41, 42, 43, 44,
+		56, 57, 58, 59, 60,
+		},
+	.oobfree	= {
+		{2, 3}, {14, 2}, {18, 3}, {30, 2},
+		{24, 3}, {46, 2}, {40, 3}, {62, 2} }
+};
+
+/**
+ * onenand_oob_32 - oob info for middle (1KB) page
+ */
+static struct nand_oobinfo onenand_oob_32 = {
+	.useecc		= MTD_NANDECC_AUTOPLACE,
+	.eccbytes	= 10,
+	.eccpos		= {
+		8, 9, 10, 11, 12,
+		24, 25, 26, 27, 28,
+		},
+	.oobfree	= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
+};
+
+static const unsigned char ffchars[] = {
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 16 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 32 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 48 */
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,	/* 64 */
+};
+
+/**
+ * onenand_readw - [OneNAND Interface] Read OneNAND register
+ * @param addr		address to read
+ *
+ * Read OneNAND register
+ */
+static unsigned short onenand_readw(void __iomem *addr)
+{
+	return readw(addr);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Write OneNAND register with value
+ * @param value		value to write
+ * @param addr		address to write
+ *
+ * Write OneNAND register with value
+ */
+static void onenand_writew(unsigned short value, void __iomem *addr)
+{
+	writew(value, addr);
+}
+
+/**
+ * onenand_block_address - [DEFAULT] Get block address
+ * @param device	the device id
+ * @param block		the block
+ * @return		translated block address if DDP, otherwise same
+ *
+ * Setup Start Address 1 Register (F100h)
+ */
+static int onenand_block_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device Flash Core select, NAND Flash Block Address */
+		int dfs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dfs = 1;
+
+		return (dfs << ONENAND_DDP_SHIFT) | (block & (mask - 1));
+	}
+
+	return block;
+}
+
+/**
+ * onenand_bufferram_address - [DEFAULT] Get bufferram address
+ * @param device	the device id
+ * @param block		the block
+ * @return		set DBS value if DDP, otherwise 0
+ *
+ * Setup Start Address 2 Register (F101h) for DDP
+ */
+static int onenand_bufferram_address(int device, int block)
+{
+	if (device & ONENAND_DEVICE_IS_DDP) {
+		/* Device BufferRAM Select */
+		int dbs = 0, density, mask;
+
+		density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+		mask = (1 << (density + 6));
+
+		if (block & mask)
+			dbs = 1;
+
+		return (dbs << ONENAND_DDP_SHIFT);
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_page_address - [DEFAULT] Get page address
+ * @param page		the page address
+ * @param sector	the sector address
+ * @return		combined page and sector address
+ *
+ * Setup Start Address 8 Register (F107h)
+ */
+static int onenand_page_address(int page, int sector)
+{
+	/* Flash Page Address, Flash Sector Address */
+	int fpa, fsa;
+
+	fpa = page & ONENAND_FPA_MASK;
+	fsa = sector & ONENAND_FSA_MASK;
+
+	return ((fpa << ONENAND_FPA_SHIFT) | fsa);
+}
+
+/**
+ * onenand_buffer_address - [DEFAULT] Get buffer address
+ * @param dataram1	DataRAM index
+ * @param sectors	the sector address
+ * @param count		the number of sectors
+ * @return		the start buffer value
+ *
+ * Setup Start Buffer Register (F200h)
+ */
+static int onenand_buffer_address(int dataram1, int sectors, int count)
+{
+	int bsa, bsc;
+
+	/* BufferRAM Sector Address */
+	bsa = sectors & ONENAND_BSA_MASK;
+
+	if (dataram1)
+		bsa |= ONENAND_BSA_DATARAM1;	/* DataRAM1 */
+	else
+		bsa |= ONENAND_BSA_DATARAM0;	/* DataRAM0 */
+
+	/* BufferRAM Sector Count */
+	bsc = count & ONENAND_BSC_MASK;
+
+	return ((bsa << ONENAND_BSA_SHIFT) | bsc);
+}
+
+/**
+ * onenand_command - [DEFAULT] Send command to OneNAND device
+ * @param mtd		MTD device structure
+ * @param cmd		the command to be sent
+ * @param addr		offset to read from or write to
+ * @param len		number of bytes to read or write
+ *
+ * Send command to OneNAND device. This function is used for middle/large page
+ * devices (1KB/2KB Bytes per page)
+ */
+static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int value, readcmd = 0;
+	int block, page;
+	/* Now we use page size operation */
+	int sectors = 4, count = 4;
+
+	/* Address translation */
+	switch (cmd) {
+	case ONENAND_CMD_UNLOCK:
+	case ONENAND_CMD_LOCK:
+	case ONENAND_CMD_LOCK_TIGHT:
+		block = -1;
+		page = -1;
+		break;
+
+	case ONENAND_CMD_ERASE:
+	case ONENAND_CMD_BUFFERRAM:
+		block = (int) (addr >> this->erase_shift);
+		page = -1;
+		break;
+
+	default:
+		block = (int) (addr >> this->erase_shift);
+		page = (int) (addr >> this->page_shift);
+		page &= this->page_mask;
+		break;
+	}
+
+	/* NOTE: The setting order of the registers is very important! */
+	if (cmd == ONENAND_CMD_BUFFERRAM) {
+		/* Select DataRAM for DDP */
+		value = onenand_bufferram_address(this->device_id, block);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
+
+		/* Switch to the next data buffer */
+		ONENAND_SET_NEXT_BUFFERRAM(this);
+
+		return 0;
+	}
+
+	if (block != -1) {
+		/* Write 'DFS, FBA' of Flash */
+		value = onenand_block_address(this->device_id, block);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
+	}
+
+	if (page != -1) {
+		int dataram;
+
+		switch (cmd) {
+		case ONENAND_CMD_READ:
+		case ONENAND_CMD_READOOB:
+			dataram = ONENAND_SET_NEXT_BUFFERRAM(this);
+			readcmd = 1;
+			break;
+
+		default:
+			dataram = ONENAND_CURRENT_BUFFERRAM(this);
+			break;
+		}
+
+		/* Write 'FPA, FSA' of Flash */
+		value = onenand_page_address(page, sectors);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8);
+
+		/* Write 'BSA, BSC' of DataRAM */
+		value = onenand_buffer_address(dataram, sectors, count);
+		this->write_word(value, this->base + ONENAND_REG_START_BUFFER);
+			
+		if (readcmd) {
+			/* Select DataRAM for DDP */
+			value = onenand_bufferram_address(this->device_id, block);
+			this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
+		}
+	}
+
+	/* Interrupt clear */
+	this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT);
+
+	/* Write command */
+	this->write_word(cmd, this->base + ONENAND_REG_COMMAND);
+
+	return 0;
+}
+
+/**
+ * onenand_wait - [DEFAULT] wait until the command is done
+ * @param mtd		MTD device structure
+ * @param state		state to select the max. timeout value
+ *
+ * Wait for command done. This applies to all OneNAND command
+ * Read can take up to 30us, erase up to 2ms and program up to 350us
+ * according to general OneNAND specs
+ */
+static int onenand_wait(struct mtd_info *mtd, int state)
+{
+	struct onenand_chip * this = mtd->priv;
+	unsigned long timeout;
+	unsigned int flags = ONENAND_INT_MASTER;
+	unsigned int interrupt = 0;
+	unsigned int ctrl, ecc;
+
+	/* The 20 msec is enough */
+	timeout = jiffies + msecs_to_jiffies(20);
+	while (time_before(jiffies, timeout)) {
+		interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
+
+		if (interrupt & flags)
+			break;
+
+		if (state != FL_READING)
+			cond_resched();
+	}
+	/* To get correct interrupt status in timeout case */
+	interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
+
+	ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
+
+	if (ctrl & ONENAND_CTRL_ERROR) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (ctrl & ONENAND_CTRL_LOCK) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x", ctrl);
+		return -EIO;
+	}
+
+	if (interrupt & ONENAND_INT_READ) {
+		ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
+		if (ecc & ONENAND_ECC_2BIT_ALL) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x", ecc);
+			return -EBADMSG;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_bufferram_offset - [DEFAULT] BufferRAM offset
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @return		offset given area
+ *
+ * Return BufferRAM offset given area
+ */
+static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (ONENAND_CURRENT_BUFFERRAM(this)) {
+		if (area == ONENAND_DATARAM)
+			return mtd->oobblock;
+		if (area == ONENAND_SPARERAM)
+			return mtd->oobsize;
+	}
+
+	return 0;
+}
+
+/**
+ * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Read the BufferRAM area
+ */
+static int onenand_read_bufferram(struct mtd_info *mtd, int area,
+		unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	memcpy(buffer, bufferram + offset, count);
+
+	return 0;
+}
+
+/**
+ * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Write the BufferRAM area
+ */
+static int onenand_write_bufferram(struct mtd_info *mtd, int area,
+		const unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	memcpy(bufferram + offset, buffer, count);
+
+	return 0;
+}
+
+/**
+ * onenand_check_bufferram - [GENERIC] Check BufferRAM information
+ * @param mtd		MTD data structure
+ * @param addr		address to check
+ * @return		1 if there are valid data, otherwise 0 
+ *
+ * Check bufferram if there is data we required
+ */
+static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
+{
+	struct onenand_chip *this = mtd->priv;
+	int block, page;
+	int i;
+	
+	block = (int) (addr >> this->erase_shift);
+	page = (int) (addr >> this->page_shift);
+	page &= this->page_mask;
+
+	i = ONENAND_CURRENT_BUFFERRAM(this);
+
+	/* Is there valid data? */
+	if (this->bufferram[i].block == block &&
+	    this->bufferram[i].page == page &&
+	    this->bufferram[i].valid)
+		return 1;
+
+	return 0;
+}
+
+/**
+ * onenand_update_bufferram - [GENERIC] Update BufferRAM information
+ * @param mtd		MTD data structure
+ * @param addr		address to update
+ * @param valid		valid flag
+ *
+ * Update BufferRAM information
+ */
+static int onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
+		int valid)
+{
+	struct onenand_chip *this = mtd->priv;
+	int block, page;
+	int i;
+	
+	block = (int) (addr >> this->erase_shift);
+	page = (int) (addr >> this->page_shift);
+	page &= this->page_mask;
+
+	/* Invalidate BufferRAM */
+	for (i = 0; i < MAX_BUFFERRAM; i++) {
+		if (this->bufferram[i].block == block &&
+		    this->bufferram[i].page == page)
+			this->bufferram[i].valid = 0;
+	}
+
+	/* Update BufferRAM */
+	i = ONENAND_CURRENT_BUFFERRAM(this);
+	this->bufferram[i].block = block;
+	this->bufferram[i].page = page;
+	this->bufferram[i].valid = valid;
+
+	return 0;
+}
+
+/**
+ * onenand_get_device - [GENERIC] Get chip for selected access
+ * @param mtd		MTD device structure
+ * @param new_state	the state which is requested
+ *
+ * Get the device and lock it for exclusive access
+ */
+static void onenand_get_device(struct mtd_info *mtd, int new_state)
+{
+	struct onenand_chip *this = mtd->priv;
+	DECLARE_WAITQUEUE(wait, current);
+
+	/*
+	 * Grab the lock and see if the device is available
+	 */
+	while (1) {
+		spin_lock(&this->chip_lock);
+		if (this->state == FL_READY) {
+			this->state = new_state;
+			spin_unlock(&this->chip_lock);
+			break;
+		}
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&this->wq, &wait);
+		spin_unlock(&this->chip_lock);
+		schedule();
+		remove_wait_queue(&this->wq, &wait);
+	}
+}
+
+/**
+ * onenand_release_device - [GENERIC] release chip
+ * @param mtd		MTD device structure
+ *
+ * Deselect, release chip lock and wake up anyone waiting on the device
+ */
+static void onenand_release_device(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	/* Release the chip */
+	spin_lock(&this->chip_lock);
+	this->state = FL_READY;
+	wake_up(&this->wq);
+	spin_unlock(&this->chip_lock);
+}
+
+/**
+ * onenand_read_ecc - [MTD Interface] Read data with ECC
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ * @param oob_buf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND read with ECC
+ */
+static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf,
+	u_char *oob_buf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, column;
+	int thislen;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ecc: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Do not allow reads past end of device */
+	if ((from + len) > mtd->size) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: Attempt read beyond end of device\n");
+		*retlen = 0;
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_READING);
+
+	/* TODO handling oob */
+
+	while (read < len) {
+		thislen = min_t(int, mtd->oobblock, len - read);
+
+		column = from & (mtd->oobblock - 1);
+		if (column + thislen > mtd->oobblock)
+			thislen = mtd->oobblock - column;
+
+		if (!onenand_check_bufferram(mtd, from)) {
+			this->command(mtd, ONENAND_CMD_READ, from, mtd->oobblock);
+
+			ret = this->wait(mtd, FL_READING);
+			/* First copy data and check return value for ECC handling */
+			onenand_update_bufferram(mtd, from, 1);
+		}
+
+		this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen);
+
+		read += thislen;
+
+		if (read == len)
+			break;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_ecc: read failed = %d\n", ret);
+			goto out;
+		}
+
+		from += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	/*
+	 * Return success, if no ECC failures, else -EBADMSG
+	 * fs driver will take care of that, because
+	 * retlen == desired len and result == -EBADMSG
+	 */
+	*retlen = read;
+	return ret;
+}
+
+/**
+ * onenand_read - [MTD Interface] MTD compability function for onenand_read_ecc
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * This function simply calls onenand_read_ecc with oob buffer and oobsel = NULL
+*/
+static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_read_oob - [MTD Interface] OneNAND read out-of-band
+ * @param mtd		MTD device structure
+ * @param from		offset to read from
+ * @param len		number of bytes to read
+ * @param retlen	pointer to variable to store the number of read bytes
+ * @param buf		the databuffer to put data
+ *
+ * OneNAND read out-of-band data from the spare area
+ */
+static int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
+	size_t *retlen, u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int read = 0, thislen, column;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
+
+	/* Initialize return length value */
+	*retlen = 0;
+
+	/* Do not allow reads past end of device */
+	if (unlikely((from + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: Attempt read beyond end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_READING);
+
+	column = from & (mtd->oobsize - 1);
+
+	while (read < len) {
+		thislen = mtd->oobsize - column;
+		thislen = min_t(int, thislen, len);
+
+		this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize);
+
+		onenand_update_bufferram(mtd, from, 0);
+
+		ret = this->wait(mtd, FL_READING);
+		/* First copy data and check return value for ECC handling */
+
+		this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
+
+		read += thislen;
+
+		if (read == len)
+			break;
+
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_read_oob: read failed = %d\n", ret);
+			goto out;
+		}
+
+		buf += thislen;
+
+		/* Read more? */
+		if (read < len) {
+			/* Page size */
+			from += mtd->oobblock;
+			column = 0;
+		}
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = read;
+	return ret;
+}
+
+#ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE
+/**
+ * onenand_verify_page - [GENERIC] verify the chip contents after a write
+ * @param mtd		MTD device structure
+ * @param buf		the databuffer to verify
+ * @param block		block address
+ * @param page		page address
+ *
+ * Check DataRAM area directly
+ */
+static int onenand_verify_page(struct mtd_info *mtd, u_char *buf,
+	loff_t addr, int block, int page)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *dataram0, *dataram1;
+	int ret = 0;
+
+	this->command(mtd, ONENAND_CMD_READ, addr, mtd->oobblock);
+
+	ret = this->wait(mtd, FL_READING);
+	if (ret)
+		return ret;
+
+	onenand_update_bufferram(mtd, addr, 1);
+
+	/* Check, if the two dataram areas are same */
+	dataram0 = this->base + ONENAND_DATARAM;
+	dataram1 = dataram0 + mtd->oobblock;
+
+	if (memcmp(dataram0, dataram1, mtd->oobblock))
+		return -EBADMSG;
+	
+	return 0;
+}
+#else
+#define onenand_verify_page(...)	(0)
+#endif
+
+#define NOTALIGNED(x)	((x & (mtd->oobblock - 1)) != 0)
+
+/**
+ * onenand_write_ecc - [MTD Interface] OneNAND write with ECC
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with ECC
+ */
+static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	int written = 0;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ecc: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobblock, len - written);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen);
+		this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		onenand_update_bufferram(mtd, to, 1);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: write filaed %d\n", ret);
+			goto out;
+		}
+
+		written += thislen;
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return ret;
+}
+
+/**
+ * onenand_write - [MTD Interface] compability function for onenand_write_ecc
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * This function simply calls onenand_write_ecc
+ * with oob buffer and oobsel = NULL
+ */
+static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL);
+}
+
+/**
+ * onenand_write_oob - [MTD Interface] OneNAND write out-of-band
+ * @param mtd		MTD device structure
+ * @param to		offset to write to
+ * @param len		number of bytes to write
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param buf		the data to write
+ *
+ * OneNAND write out-of-band
+ */
+static int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
+	size_t *retlen, const u_char *buf)
+{
+	struct onenand_chip *this = mtd->priv;
+	int column, status;
+	int written = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len);
+
+	/* Initialize retlen, in case of early exit */
+	*retlen = 0;
+
+	/* Do not allow writes past end of device */
+	if (unlikely((to + len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_oob: Attempt write to past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* Loop until all data write */
+	while (written < len) {
+		int thislen = min_t(int, mtd->oobsize, len - written);
+
+		column = to & (mtd->oobsize - 1);
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize);
+
+		this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
+		this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen);
+
+		this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
+
+		onenand_update_bufferram(mtd, to, 0);
+
+		status = this->wait(mtd, FL_WRITING);
+		if (status)
+			goto out;
+
+		written += thislen;
+
+		if (written == len)
+			break;
+
+		to += thislen;
+		buf += thislen;
+	}
+
+out:
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+	
+	return 0;
+}
+
+/**
+ * onenand_writev_ecc - [MTD Interface] write with iovec with ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ * @param eccbuf	filesystem supplied oob data buffer
+ * @param oobsel	oob selection structure
+ *
+ * OneNAND write with iovec with ecc
+ */
+static int onenand_writev_ecc(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen,
+	u_char *eccbuf, struct nand_oobinfo *oobsel)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned char buffer[mtd->oobblock], *pbuf;
+	size_t total_len, len;
+	int i, written = 0;
+	int ret = 0;
+
+	/* Preset written len for early exit */
+	*retlen = 0;
+
+	/* Calculate total length of data */
+	total_len = 0;
+	for (i = 0; i < count; i++)
+		total_len += vecs[i].iov_len;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_writev_ecc: to = 0x%08x, len = %i, count = %ld\n", (unsigned int) to, (unsigned int) total_len, count);
+
+	/* Do not allow write past end of the device */
+	if (unlikely((to + total_len) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempted write past end of device\n");
+		return -EINVAL;
+	}
+
+	/* Reject writes, which are not page aligned */
+        if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(total_len))) {
+                DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: Attempt to write not page aligned data\n");
+                return -EINVAL;
+        }
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_WRITING);
+
+	/* TODO handling oob */
+	
+	/* Loop until all keve's data has been written */
+	len = 0;
+	while (count) {
+		pbuf = buffer;
+		/* 
+		 * If the given tuple is >= pagesize then
+		 * write it out from the iov
+		 */
+		if ((vecs->iov_len - len) >= mtd->oobblock) {
+			pbuf = vecs->iov_base + len;
+
+			len += mtd->oobblock;
+
+			/* Check, if we have to switch to the next tuple */
+			if (len >= (int) vecs->iov_len) {
+				vecs++;
+				len = 0;
+				count--;
+			}
+		} else {
+			int cnt = 0, thislen;
+			while (cnt < mtd->oobblock) {
+				thislen = min_t(int, mtd->oobblock - cnt, vecs->iov_len - len);
+				memcpy(buffer + cnt, vecs->iov_base + len, thislen);
+				cnt += thislen;
+				len += thislen;
+
+				/* Check, if we have to switch to the next tuple */
+				if (len >= (int) vecs->iov_len) {
+					vecs++;
+					len = 0;
+					count--;
+				}
+			}
+		}
+
+		this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobblock);
+
+		this->write_bufferram(mtd, ONENAND_DATARAM, pbuf, 0, mtd->oobblock);
+		this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize);
+
+		this->command(mtd, ONENAND_CMD_PROG, to, mtd->oobblock);
+
+		onenand_update_bufferram(mtd, to, 1);
+
+		ret = this->wait(mtd, FL_WRITING);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: write failed %d\n", ret);
+			goto out;
+		}
+
+
+		/* Only check verify write turn on */
+		ret = onenand_verify_page(mtd, (u_char *) pbuf, to, block, page);
+		if (ret) {
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: verify failed %d\n", ret);
+			goto out;
+		}
+
+		written += mtd->oobblock;
+
+		to += mtd->oobblock;
+	}
+
+out:
+	/* Deselect and wakt up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	*retlen = written;
+
+	return 0;
+}
+
+/**
+ * onenand_writev - [MTD Interface] compabilty function for onenand_writev_ecc
+ * @param mtd		MTD device structure
+ * @param vecs		the iovectors to write
+ * @param count		number of vectors
+ * @param to		offset to write to
+ * @param retlen	pointer to variable to store the number of written bytes
+ *
+ * OneNAND write with kvec. This just calls the ecc function
+ */
+static int onenand_writev(struct mtd_info *mtd, const struct kvec *vecs,
+	unsigned long count, loff_t to, size_t *retlen)
+{
+	return onenand_writev_ecc(mtd, vecs, count, to, retlen, NULL, NULL);
+}
+
+/**
+ * onenand_erase - [MTD Interface] erase block(s)
+ * @param mtd		MTD device structure
+ * @param instr		erase instruction
+ *
+ * Erase one ore more blocks
+ */
+static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct onenand_chip *this = mtd->priv;
+	unsigned int block_size;
+	loff_t addr;
+	int len;
+	int ret = 0;
+
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len);
+
+	block_size = (1 << this->erase_shift);
+
+	/* Start address must align on block boundary */
+	if (unlikely(instr->addr & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Unaligned address\n");
+		return -EINVAL;
+	}
+
+	/* Length must align on block boundary */
+	if (unlikely(instr->len & (block_size - 1))) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Length not block aligned\n");
+		return -EINVAL;
+	}
+
+	/* Do not allow erase past end of device */
+	if (unlikely((instr->len + instr->addr) > mtd->size)) {
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Erase past end of device\n");
+		return -EINVAL;
+	}
+
+	instr->fail_addr = 0xffffffff;
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_ERASING);
+
+	/* Loop throught the pages */
+	len = instr->len;
+	addr = instr->addr;
+
+	instr->state = MTD_ERASING;
+
+	while (len) {
+
+		/* TODO Check badblock */
+
+		this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
+
+		ret = this->wait(mtd, FL_ERASING);
+		/* Check, if it is write protected */
+		if (ret) {
+			if (ret == -EPERM)
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Device is write protected!!!\n");
+			else
+				DEBUG(MTD_DEBUG_LEVEL0, "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift));
+			instr->state = MTD_ERASE_FAILED;
+			instr->fail_addr = addr;
+			goto erase_exit;
+		}
+
+		len -= block_size;
+		addr += block_size;
+	}
+
+	instr->state = MTD_ERASE_DONE;
+
+erase_exit:
+
+	ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+	/* Do call back function */
+	if (!ret)
+		mtd_erase_callback(instr);
+
+	/* Deselect and wake up anyone waiting on the device */
+	onenand_release_device(mtd);
+
+	return ret;
+}
+
+/**
+ * onenand_sync - [MTD Interface] sync
+ * @param mtd		MTD device structure
+ *
+ * Sync is actually a wait for chip ready function
+ */
+static void onenand_sync(struct mtd_info *mtd)
+{
+	DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n");
+
+	/* Grab the lock and see if the device is available */
+	onenand_get_device(mtd, FL_SYNCING);
+
+	/* Release it and go back */
+	onenand_release_device(mtd);
+}
+
+/**
+ * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/*
+	 * TODO 
+	 * 1. Bad block table (BBT)
+	 *   -> using NAND BBT to support JFFS2
+	 * 2. Bad block management (BBM)
+	 *   -> bad block replace scheme
+	 *
+	 * Currently we do nothing
+	 */
+	return 0;
+}
+
+/**
+ * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ */
+static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	/* see above */
+	return 0;
+}
+
+/**
+ * onenand_unlock - [MTD Interface] Unlock block(s)
+ * @param mtd		MTD device structure
+ * @param ofs		offset relative to mtd start
+ * @param len		number of bytes to unlock
+ *
+ * Unlock one or more blocks
+ */
+static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+{
+	struct onenand_chip *this = mtd->priv;
+	int start, end, block, value, status;
+
+	start = ofs >> this->erase_shift;
+	end = len >> this->erase_shift;
+
+	/* Continuous lock scheme */
+	if (this->options & ONENAND_CONT_LOCK) {
+		/* Set start block address */
+		this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Set end block address */
+		this->write_word(end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Check lock status */
+		status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "wp status = 0x%x\n", status);
+
+		return 0;
+	}
+
+	/* Block lock scheme */
+	for (block = start; block < end; block++) {
+		/* Set start block address */
+		this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS);
+		/* Write unlock command */
+		this->command(mtd, ONENAND_CMD_UNLOCK, 0, 0);
+
+		/* There's no return value */
+		this->wait(mtd, FL_UNLOCKING);
+
+		/* Sanity check */
+		while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS)
+		    & ONENAND_CTRL_ONGO)
+			continue;
+
+		/* Set block address for read block status */
+		value = onenand_block_address(this->device_id, block);
+		this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1);
+
+		/* Check lock status */
+		status = this->read_word(this->base + ONENAND_REG_WP_STATUS);
+		if (!(status & ONENAND_WP_US))
+			printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status);
+	}
+	
+	return 0;
+}
+
+/**
+ * onenand_print_device_info - Print device ID
+ * @param device        device ID
+ *
+ * Print device ID
+ */
+static void onenand_print_device_info(int device)
+{
+        int vcc, demuxed, ddp, density;
+
+        vcc = device & ONENAND_DEVICE_VCC_MASK;
+        demuxed = device & ONENAND_DEVICE_IS_DEMUX;
+        ddp = device & ONENAND_DEVICE_IS_DDP;
+        density = device >> ONENAND_DEVICE_DENSITY_SHIFT;
+        printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n",
+                demuxed ? "" : "Muxed ",
+                ddp ? "(DDP)" : "",
+                (16 << density),
+                vcc ? "2.65/3.3" : "1.8",
+                device);
+}
+
+static const struct onenand_manufacturers onenand_manuf_ids[] = {
+        {ONENAND_MFR_SAMSUNG, "Samsung"},
+        {ONENAND_MFR_UNKNOWN, "Unknown"}
+};
+
+/**
+ * onenand_check_maf - Check manufacturer ID
+ * @param manuf         manufacturer ID
+ *
+ * Check manufacturer ID
+ */
+static int onenand_check_maf(int manuf)
+{
+        int i;
+
+        for (i = 0; onenand_manuf_ids[i].id; i++) {
+                if (manuf == onenand_manuf_ids[i].id)
+                        break;
+        }
+
+        printk(KERN_DEBUG "OneNAND Manufacturer: %s\n",
+                onenand_manuf_ids[i].name);
+
+        return (i != ONENAND_MFR_UNKNOWN);
+}
+
+/**
+ * onenand_probe - [OneNAND Interface] Probe the OneNAND device
+ * @param mtd		MTD device structure
+ *
+ * OneNAND detection method:
+ *   Compare the the values from command with ones from register
+ */
+static int onenand_probe(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	int bram_maf_id, bram_dev_id, maf_id, dev_id;
+	int version_id;
+	int density;
+
+	/* Send the command for reading device ID from BootRAM */
+	this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from BootRAM */
+	bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0);
+	bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2);
+
+	/* Check manufacturer ID */
+	if (onenand_check_maf(bram_maf_id))
+		return -ENXIO;
+
+	/* Reset OneNAND to read default register values */
+	this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM);
+
+	/* Read manufacturer and device IDs from Register */
+	maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID);
+	dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID);
+
+	/* Check OneNAND device */
+	if (maf_id != bram_maf_id || dev_id != bram_dev_id)
+		return -ENXIO;
+
+	/* Flash device information */
+	onenand_print_device_info(dev_id);
+	this->device_id = dev_id;
+
+	density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+	this->chipsize = (16 << density) << 20;
+
+	/* OneNAND page size & block size */
+	/* The data buffer size is equal to page size */
+	mtd->oobblock = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE);
+	mtd->oobsize = mtd->oobblock >> 5;
+	/* Pagers per block is always 64 in OneNAND */
+	mtd->erasesize = mtd->oobblock << 6;
+
+	this->erase_shift = ffs(mtd->erasesize) - 1;
+	this->page_shift = ffs(mtd->oobblock) - 1;
+	this->ppb_shift = (this->erase_shift - this->page_shift);
+	this->page_mask = (mtd->erasesize / mtd->oobblock) - 1;
+
+	/* REVIST: Multichip handling */
+
+	mtd->size = this->chipsize;
+
+	/* Version ID */
+	version_id = this->read_word(this->base + ONENAND_REG_VERSION_ID);
+	printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version_id);
+
+	/* Lock scheme */
+	if (density <= ONENAND_DEVICE_DENSITY_512Mb &&
+	    !(version_id >> ONENAND_VERSION_PROCESS_SHIFT)) {
+		printk(KERN_INFO "Lock scheme is Continues Lock\n");
+		this->options |= ONENAND_CONT_LOCK;
+	}
+	
+	return 0;
+}
+
+
+/**
+ * onenand_scan - [OneNAND Interface] Scan for the OneNAND device
+ * @param mtd		MTD device structure
+ * @param maxchips	Number of chips to scan for
+ *
+ * This fills out all the not initialized function pointers
+ * with the defaults.
+ * The flash ID is read and the mtd/chip structures are
+ * filled with the appropriate values.
+ */
+int onenand_scan(struct mtd_info *mtd, int maxchips)
+{
+	struct onenand_chip *this = mtd->priv;
+
+	if (!this->read_word)
+		this->read_word = onenand_readw;
+	if (!this->write_word)
+		this->write_word = onenand_writew;
+
+	if (!this->command)
+		this->command = onenand_command;
+	if (!this->wait)
+		this->wait = onenand_wait;
+
+	if (!this->read_bufferram)
+		this->read_bufferram = onenand_read_bufferram;
+	if (!this->write_bufferram)
+		this->write_bufferram = onenand_write_bufferram;
+
+	if (onenand_probe(mtd))
+		return -ENXIO;
+
+	this->state = FL_READY;
+	init_waitqueue_head(&this->wq);
+	spin_lock_init(&this->chip_lock);
+
+	switch (mtd->oobsize) {
+	case 64:
+		this->autooob = &onenand_oob_64;
+		break;
+
+	case 32:
+		this->autooob = &onenand_oob_32;
+		break;
+
+	default:
+		printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n",
+			mtd->oobsize);
+		/* To prevent kernel oops */
+		this->autooob = &onenand_oob_32;
+		break;
+	}
+
+	memcpy(&mtd->oobinfo, this->autooob, sizeof(mtd->oobinfo));
+	
+	/* Fill in remaining MTD driver data */
+	mtd->type = MTD_NANDFLASH;
+	mtd->flags = MTD_CAP_NANDFLASH | MTD_ECC;
+	mtd->ecctype = MTD_ECC_SW;
+	mtd->erase = onenand_erase;
+	mtd->point = NULL;
+	mtd->unpoint = NULL;
+	mtd->read = onenand_read;
+	mtd->write = onenand_write;
+	mtd->read_ecc = onenand_read_ecc;
+	mtd->write_ecc = onenand_write_ecc;
+	mtd->read_oob = onenand_read_oob;
+	mtd->write_oob = onenand_write_oob;
+	mtd->readv = NULL;
+	mtd->readv_ecc = NULL;
+	mtd->writev = onenand_writev;
+	mtd->writev_ecc = onenand_writev_ecc;
+	mtd->sync = onenand_sync;
+	mtd->lock = NULL;
+	mtd->unlock = onenand_unlock;
+	mtd->suspend = NULL;
+	mtd->resume = NULL;
+	mtd->block_isbad = onenand_block_isbad;
+	mtd->block_markbad = onenand_block_markbad;
+	mtd->owner = THIS_MODULE;
+
+	/* Unlock whole block */
+	mtd->unlock(mtd, 0x0, this->chipsize);
+
+	return 0;
+}
+
+/**
+ * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device
+ * @param mtd		MTD device structure
+ */
+void onenand_release(struct mtd_info *mtd)
+{
+#ifdef CONFIG_MTD_PARTITIONS
+	/* Deregister partitions */
+	del_mtd_partitions (mtd);
+#endif
+	/* Deregister the device */
+	del_mtd_device (mtd);
+}
+
+EXPORT_SYMBOL_GPL(onenand_scan);
+EXPORT_SYMBOL_GPL(onenand_release);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("Generic OneNAND flash driver code");
Index: include/linux/mtd/onenand.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand.h  (mode:100644)
@@ -0,0 +1,134 @@
+/*
+ *  linux/include/linux/mtd/onenand.h
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MTD_ONENAND_H
+#define __LINUX_MTD_ONENAND_H
+
+#include <linux/spinlock.h>
+#include <linux/mtd/onenand_regs.h>
+
+#define MAX_BUFFERRAM		2
+
+/* Scan and identify a OneNAND device */
+extern int onenand_scan(struct mtd_info *mtd, int max_chips);
+/* Free resources held by the OneNAND device */
+extern void onenand_release(struct mtd_info *mtd);
+
+/**
+ * onenand_state_t - chip states
+ * Enumeration for OneNAND flash chip state
+ */
+typedef enum {
+	FL_READY,
+	FL_READING,
+	FL_WRITING,
+	FL_ERASING,
+	FL_SYNCING,
+	FL_UNLOCKING,
+	FL_LOCKING,
+} onenand_state_t;
+
+/**
+ * struct onenand_bufferram - OneNAND BufferRAM Data
+ * @param block		block address in BufferRAM
+ * @param page		page address in BufferRAM
+ * @param valid		valid flag
+ */
+struct onenand_bufferram {
+	int block;
+	int page;
+	int valid;
+};
+
+/**
+ * struct onenand_chip - OneNAND Private Flash Chip Data
+ * @param base		[BOARDSPECIFIC] address to access OneNAND
+ * @param chipsize	[INTERN] the size of one chip for multichip arrays
+ * @param device_id	[INTERN] device ID
+ * @param verstion_id	[INTERN] version ID
+ * @param options	[BOARDSPECIFIC] various chip options. They can partly be set to inform onenand_scan about
+ * @param erase_shift	[INTERN] number of address bits in a block
+ * @param page_shift	[INTERN] number of address bits in a page
+ * @param ppb_shift	[INTERN] number of address bits in a pages per block
+ * @param page_mask	[INTERN] a page per block mask
+ * @param bufferam_index	[INTERN] BufferRAM index
+ * @param bufferam	[INTERN] BufferRAM info
+ * @param readw		[REPLACEABLE] hardware specific function for read short
+ * @param writew	[REPLACEABLE] hardware specific function for write short
+ * @param command	[REPLACEABLE] hardware specific function for writing commands to the chip
+ * @param wait		[REPLACEABLE] hardware specific function for wait on ready
+ * @param read_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param write_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
+ * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
+ * @param state		[INTERN] the current state of the OneNAND device
+ * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param priv		[OPTIONAL] pointer to private chip date
+ */
+struct onenand_chip {
+	void __iomem		*base;
+	unsigned int		chipsize;
+	unsigned int		device_id;
+	unsigned int		options;
+
+	unsigned int		erase_shift;
+	unsigned int		page_shift;
+	unsigned int		ppb_shift;	/* Pages per block shift */
+	unsigned int		page_mask;
+
+	unsigned int		bufferram_index;
+	struct onenand_bufferram	bufferram[MAX_BUFFERRAM];
+
+	int (*command)(struct mtd_info *mtd, int cmd, loff_t address, size_t len);
+	int (*wait)(struct mtd_info *mtd, int state);
+	int (*read_bufferram)(struct mtd_info *mtd, int area,
+			unsigned char *buffer, int offset, size_t count);
+	int (*write_bufferram)(struct mtd_info *mtd, int area,
+			const unsigned char *buffer, int offset, size_t count);
+	unsigned short (*read_word)(void __iomem *addr);
+	void (*write_word)(unsigned short value, void __iomem *addr);
+
+	spinlock_t		chip_lock;
+	wait_queue_head_t	wq;
+	onenand_state_t		state;
+
+	struct nand_oobinfo	*autooob;
+
+	void			*priv;
+};
+
+#define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
+#define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
+#define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
+
+/*
+ * Options bits
+ */
+#define ONENAND_CONT_LOCK		(0x0001)
+
+
+/*
+ * OneNAND Flash Manufacturer ID Codes
+ */
+#define ONENAND_MFR_SAMSUNG	0xec
+#define ONENAND_MFR_UNKNOWN	0x00
+
+/**
+ * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
+ * @param name:		Manufacturer name
+ * @param id:		manufacturer ID code of device.
+*/
+struct onenand_manufacturers {
+        int id;
+        char *name;
+};
+
+#endif	/* __LINUX_MTD_ONENAND_H */
Index: include/linux/mtd/onenand_regs.h
===================================================================
--- /dev/null  (tree:4b825dc642cb6eb9a060e54bf8d69288fbee4904)
+++ uncommitted/include/linux/mtd/onenand_regs.h  (mode:100644)
@@ -0,0 +1,167 @@
+/*
+ *  linux/include/linux/mtd/onenand_regs.h
+ *
+ *  OneNAND Register header file
+ *
+ *  Copyright (C) 2005 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ONENAND_REG_H
+#define __ONENAND_REG_H
+
+/* Memory Address Map Translation (Word order) */
+#define ONENAND_MEMORY_MAP(x)		((x) << 1)
+
+/*
+ * External BufferRAM area
+ */
+#define	ONENAND_BOOTRAM			ONENAND_MEMORY_MAP(0x0000)
+#define	ONENAND_DATARAM			ONENAND_MEMORY_MAP(0x0200)
+#define	ONENAND_SPARERAM		ONENAND_MEMORY_MAP(0x8010)
+
+/*
+ * OneNAND Registers
+ */
+#define ONENAND_REG_MANUFACTURER_ID	ONENAND_MEMORY_MAP(0xF000)
+#define ONENAND_REG_DEVICE_ID		ONENAND_MEMORY_MAP(0xF001)
+#define ONENAND_REG_VERSION_ID		ONENAND_MEMORY_MAP(0xF002)
+#define ONENAND_REG_DATA_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF003)
+#define ONENAND_REG_BOOT_BUFFER_SIZE	ONENAND_MEMORY_MAP(0xF004)
+#define ONENAND_REG_NUM_BUFFERS		ONENAND_MEMORY_MAP(0xF005)
+#define ONENAND_REG_TECHNOLOGY		ONENAND_MEMORY_MAP(0xF006)
+
+#define ONENAND_REG_START_ADDRESS1	ONENAND_MEMORY_MAP(0xF100)
+#define ONENAND_REG_START_ADDRESS2	ONENAND_MEMORY_MAP(0xF101)
+#define ONENAND_REG_START_ADDRESS3	ONENAND_MEMORY_MAP(0xF102)
+#define ONENAND_REG_START_ADDRESS4	ONENAND_MEMORY_MAP(0xF103)
+#define ONENAND_REG_START_ADDRESS5	ONENAND_MEMORY_MAP(0xF104)
+#define ONENAND_REG_START_ADDRESS6	ONENAND_MEMORY_MAP(0xF105)
+#define ONENAND_REG_START_ADDRESS7	ONENAND_MEMORY_MAP(0xF106)
+#define ONENAND_REG_START_ADDRESS8	ONENAND_MEMORY_MAP(0xF107)
+
+#define ONENAND_REG_START_BUFFER	ONENAND_MEMORY_MAP(0xF200)
+#define ONENAND_REG_COMMAND		ONENAND_MEMORY_MAP(0xF220)
+#define ONENAND_REG_SYS_CFG1		ONENAND_MEMORY_MAP(0xF221)
+#define ONENAND_REG_SYS_CFG2		ONENAND_MEMORY_MAP(0xF222)
+#define ONENAND_REG_CTRL_STATUS		ONENAND_MEMORY_MAP(0xF240)
+#define ONENAND_REG_INTERRUPT		ONENAND_MEMORY_MAP(0xF241)
+#define ONENAND_REG_START_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24C)
+#define ONENAND_REG_END_BLOCK_ADDRESS	ONENAND_MEMORY_MAP(0xF24D)
+#define ONENAND_REG_WP_STATUS		ONENAND_MEMORY_MAP(0xF24E)
+
+#define ONENAND_REG_ECC_STATUS		ONENAND_MEMORY_MAP(0xFF00)
+#define ONENAND_REG_ECC_M0		ONENAND_MEMORY_MAP(0xFF01)
+#define ONENAND_REG_ECC_S0		ONENAND_MEMORY_MAP(0xFF02)
+#define ONENAND_REG_ECC_M1		ONENAND_MEMORY_MAP(0xFF03)
+#define ONENAND_REG_ECC_S1		ONENAND_MEMORY_MAP(0xFF04)
+#define ONENAND_REG_ECC_M2		ONENAND_MEMORY_MAP(0xFF05)
+#define ONENAND_REG_ECC_S2		ONENAND_MEMORY_MAP(0xFF06)
+#define ONENAND_REG_ECC_M3		ONENAND_MEMORY_MAP(0xFF07)
+#define ONENAND_REG_ECC_S3		ONENAND_MEMORY_MAP(0xFF08)
+
+/*
+ * Device ID Register F001h (R)
+ */
+#define ONENAND_DEVICE_DENSITY_SHIFT	(4)
+#define ONENAND_DEVICE_IS_DDP		(1 << 3)
+#define ONENAND_DEVICE_IS_DEMUX		(1 << 2)
+#define ONENAND_DEVICE_VCC_MASK		(0x3)
+
+#define ONENAND_DEVICE_DENSITY_512Mb	(0x002)
+
+/*
+ * Version ID Register F002h (R)
+ */
+#define ONENAND_VERSION_PROCESS_SHIFT	(8)
+
+/*
+ * Start Address 1 F100h (R/W)
+ */
+#define ONENAND_DDP_SHIFT		(15)
+
+/*
+ * Start Address 8 F107h (R/W)
+ */
+#define ONENAND_FPA_MASK		(0x3f)
+#define ONENAND_FPA_SHIFT		(2)
+#define ONENAND_FSA_MASK		(0x03)
+
+/*
+ * Start Buffer Register F200h (R/W)
+ */
+#define ONENAND_BSA_MASK		(0x03)
+#define ONENAND_BSA_SHIFT		(8)
+#define ONENAND_BSA_BOOTRAM		(0 << 2)
+#define ONENAND_BSA_DATARAM0		(2 << 2)
+#define ONENAND_BSA_DATARAM1		(3 << 2)
+#define ONENAND_BSC_MASK		(0x03)
+
+/*
+ * Command Register F220h (R/W)
+ */
+#define ONENAND_CMD_READ		(0x00)
+#define ONENAND_CMD_READOOB		(0x13)
+#define ONENAND_CMD_PROG		(0x80)
+#define ONENAND_CMD_PROGOOB		(0x1A)
+#define ONENAND_CMD_UNLOCK		(0x23)
+#define ONENAND_CMD_LOCK		(0x2A)
+#define ONENAND_CMD_LOCK_TIGHT		(0x2C)
+#define ONENAND_CMD_ERASE		(0x94)
+#define ONENAND_CMD_RESET		(0xF0)
+#define ONENAND_CMD_READID		(0x90)
+
+/* NOTE: Those are not *REAL* commands */
+#define ONENAND_CMD_BUFFERRAM		(0x1978)
+
+/*
+ * System Configuration 1 Register F221h (R, R/W)
+ */
+#define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
+#define ONENAND_SYS_CFG1_BRL		(1 << 12)
+#define ONENAND_SYS_CFG1_BL		(1 << 9)
+#define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
+#define ONENAND_SYS_CFG1_RDY		(1 << 7)
+#define ONENAND_SYS_CFG1_INT		(1 << 6)
+#define ONENAND_SYS_CFG1_IOBE		(1 << 5)
+#define ONENAND_SYS_CFG1_RDY_CONF	(1 << 4)
+
+/*
+ * Controller Status Register F240h (R)
+ */
+#define ONENAND_CTRL_ONGO		(1 << 15)
+#define ONENAND_CTRL_LOCK		(1 << 14)
+#define ONENAND_CTRL_LOAD		(1 << 13)
+#define ONENAND_CTRL_PROGRAM		(1 << 12)
+#define ONENAND_CTRL_ERASE		(1 << 11)
+#define ONENAND_CTRL_ERROR		(1 << 10)
+#define ONENAND_CTRL_RSTB		(1 << 7)
+
+/*
+ * Interrupt Status Register F241h (R)
+ */
+#define ONENAND_INT_MASTER		(1 << 15)
+#define ONENAND_INT_READ		(1 << 7)
+#define ONENAND_INT_WRITE		(1 << 6)
+#define ONENAND_INT_ERASE		(1 << 5)
+#define ONENAND_INT_RESET		(1 << 4)
+#define ONENAND_INT_CLEAR		(0 << 0)
+
+/*
+ * NAND Flash Write Protection Status Register F24Eh (R)
+ */
+#define ONENAND_WP_US			(1 << 2)
+#define ONENAND_WP_LS			(1 << 1)
+#define ONENAND_WP_LTS			(1 << 0)
+
+/*
+ * ECC Status Reigser FF00h (R)
+ */
+#define ONENAND_ECC_1BIT		(1 << 0)
+#define ONENAND_ECC_2BIT		(1 << 1)
+#define ONENAND_ECC_2BIT_ALL		(0xAAAA)
+
+#endif	/* __ONENAND_REG_H */

RE: [PATCH] OneNAND MTD support

[Thomas Gleixner]

On Mon, 2005-07-11 at 18:23 +0900, Kyungmin Park wrote:
> Is there another issue? :)

Not at the moment :)

Committed to CVS.


Thanks, 

tglx

RE: [PATCH] OneNAND MTD support

[Kyungmin Park]

[-- Attachment #1: Type: text/plain, Size: 1749 bytes --]

I'm sorry to bother you

It's my mistake. I'm not delete block, and page parameters.
At first implementation I used the block and page address scheme instead of
virtual address.

Simply delete block and page parameters.

And here's one total patch including previous three patches plus some minor
patches.

If do you have any question. Please let me know

Thanks

Kyungmin Park

> -----Original Message-----
> From: Bernhard Priewasser [mailto:bernhard.priewasser@in2soft.de] 
> Sent: Thursday, August 25, 2005 5:54 PM
> To: kyungmin.park@samsung.com; linux-mtd@lists.infradead.org
> Subject: Re: [PATCH] OneNAND MTD support
> 
> Hi Kyungmin,
> 
> when turning the "Verify OneNAND page write" on (make 
> xconfig), OneNAND 
> module does not compile:
> 
> drivers/mtd/onenand/onenand_base.c: In function `onenand_write_ecc':
> drivers/mtd/onenand/onenand_base.c:819: error: `block' 
> undeclared (first 
> use in this function)
> drivers/mtd/onenand/onenand_base.c:819: error: (Each undeclared 
> identifier is reported only once
> drivers/mtd/onenand/onenand_base.c:819: error: for each function it 
> appears in.)
> drivers/mtd/onenand/onenand_base.c:819: error: `page' 
> undeclared (first 
> use in this function)
> drivers/mtd/onenand/onenand_base.c: In function `onenand_writev_ecc':
> drivers/mtd/onenand/onenand_base.c:1028: error: `block' undeclared 
> (first use in this function)
> drivers/mtd/onenand/onenand_base.c:1028: error: `page' 
> undeclared (first 
> use in this function)
> make[3]: *** [drivers/mtd/onenand/onenand_base.o] Error 1
> make[2]: *** [drivers/mtd/onenand] Error 2
> make[1]: *** [drivers/mtd] Error 2
> make: *** [drivers] Error 2
> 
> Where should onenand_write_ecc() get block and page from?
> 
> Bernhard
> 
> 

[-- Attachment #2: onenand-050826.patch --]
[-- Type: application/octet-stream, Size: 33687 bytes --]

diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -29,4 +29,10 @@ config MTD_ONENAND_OMAP
 	help
 	  Support for OneNAND flash on TI OMAP board.
 
+config MTD_ONENAND_SYNC_READ
+	bool "OneNAND Sync. Burst Read Support"
+	depends on ARCH_OMAP
+	help
+	  This enables support for Sync. Burst Read.
+
 endmenu
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -3,7 +3,9 @@
 #
 
 # Core functionality.
-obj-$(CONFIG_MTD_ONENAND)		+= onenand_base.o
+obj-$(CONFIG_MTD_ONENAND)		+= onenand.o
 
 # Board specific.
 obj-$(CONFIG_MTD_ONENAND_OMAP)		+= omap-onenand.o
+
+onenand-objs = onenand_base.o onenand_bbt.o
diff --git a/drivers/mtd/onenand/omap-onenand.c b/drivers/mtd/onenand/omap-onenand.c
--- a/drivers/mtd/onenand/omap-onenand.c
+++ b/drivers/mtd/onenand/omap-onenand.c
@@ -4,174 +4,143 @@
  *  Copyright (c) 2005 Samsung Electronics
  *  Kyungmin Park <kyungmin.park@samsung.com>
  *
- *  Derived from linux/drivers/mtd/nand/omap-nand-flash.c
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
  *  Overview:
- *   This is a device driver for the OneNAND flash device for TI OMAP boards.
+ *   This is a device driver for the OneNAND flash for OMAP boards.
  */
 
-#include <linux/slab.h>
-#include <linux/init.h>
+#include <linux/device.h>
 #include <linux/module.h>
+#include <linux/init.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
 
 #include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/tc.h>
-#include <asm/sizes.h>
-
-#define OMAP_ONENAND_FLASH_START1	OMAP_CS2A_PHYS
-#define OMAP_ONENAND_FLASH_START2	OMAP_CS0_PHYS
-/*
- * MTD structure for OMAP board
- */
-static struct mtd_info *omap_onenand_mtd = NULL;
+#include <asm/mach/flash.h>
 
-/*
- * Define partitions for flash devices
- */
+#define DRIVER_NAME	"onenand"
 
-#ifdef CONFIG_MTD_PARTITIONS
-static struct mtd_partition static_partition[] = {
-	{
-		.name		= "X-Loader + U-Boot",
-		.offset		= 0,
-		.size		= SZ_128K,
-		.mask_flags	= MTD_WRITEABLE	/* force read-only */
- 	},
-	{
-		.name		= "U-Boot Environment",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= SZ_128K,
-		.mask_flags	= MTD_WRITEABLE	/* force read-only */
- 	},
-	{
-		.name		= "kernel",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= 2 * SZ_1M
-	},
-	{
-		.name		= "filesystem0",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= SZ_16M,
-	},
-	{
-		.name		= "filesystem1",
-		.offset		= MTDPART_OFS_APPEND,
-		.size		= MTDPART_SIZ_FULL,
-	},
-};
-
-const char *part_probes[] = { "cmdlinepart", NULL,  };
 
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *part_probes[] = { "cmdlinepart", NULL,  };
 #endif
 
-/* Scan to find existance of the device at base.
-   This also allocates oob and data internal buffers */
-static char onenand_name[] = "onenand";
+struct omap_onenand_info {
+	struct mtd_info		mtd;
+	struct mtd_partition	*parts;
+	struct onenand_chip	onenand;
+};
 
-/*
- * Main initialization routine
- */
-static int __init omap_onenand_init (void)
+static int __devinit omap_onenand_probe(struct device *dev)
 {
-	struct onenand_chip *this;
-	struct mtd_partition *dynamic_partition = 0;
-	int err = 0;
-
-	/* Allocate memory for MTD device structure and private data */
-	omap_onenand_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct onenand_chip),
-				GFP_KERNEL);
-	if (!omap_onenand_mtd) {
-		printk (KERN_WARNING "Unable to allocate OneNAND MTD device structure.\n");
-		err = -ENOMEM;
-		goto out;
+	struct omap_onenand_info *info;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct onenand_platform_data *pdata = pdev->dev.platform_data;
+	struct resource *res = pdev->resource;
+	unsigned long size = res->end - res->start + 1;
+	int err;
+
+	info = kmalloc(sizeof(struct omap_onenand_info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	memset(info, 0, sizeof(struct omap_onenand_info));
+
+	if (!request_mem_region(res->start, size, dev->driver->name)) {
+		err = -EBUSY;
+		goto out_free_info;
 	}
 
-	/* Get pointer to private data */
-	this = (struct onenand_chip *) (&omap_onenand_mtd[1]);
+	info->onenand.base = ioremap(res->start, size);
+	if (!info->onenand.base) {
+		err = -ENOMEM;
+		goto out_release_mem_region;
+	}
 
-	/* Initialize structures */
-	memset((char *) omap_onenand_mtd, 0, sizeof(struct mtd_info) + sizeof(struct onenand_chip));
+	info->onenand.mmcontrol = pdata->mmcontrol;
 
-	/* Link the private data with the MTD structure */
-	omap_onenand_mtd->priv = this;
+	info->mtd.name = pdev->dev.bus_id;
+	info->mtd.priv = &info->onenand;
+	info->mtd.owner = THIS_MODULE;
 
-        /* try the first address */
-	this->base = ioremap(OMAP_ONENAND_FLASH_START1, SZ_128K);
-	omap_onenand_mtd->name = onenand_name;
-	if (onenand_scan(omap_onenand_mtd, 1)){
-		/* try the second address */
-		iounmap(this->base);
-		this->base = ioremap(OMAP_ONENAND_FLASH_START2, SZ_128K);
-		if (onenand_scan(omap_onenand_mtd, 1)) {
-			iounmap(this->base);
-                        err = -ENXIO;
-                        goto out_mtd;
-		}
+	if (onenand_scan(&info->mtd, 1)) {
+		err = -ENXIO;
+		goto out_iounmap;
 	}
 
-	/* Register the partitions */
-	switch (omap_onenand_mtd->size) {
-	case SZ_128M:
-	case SZ_64M:
-	case SZ_32M:
 #ifdef CONFIG_MTD_PARTITIONS
-		err = parse_mtd_partitions(omap_onenand_mtd, part_probes,
-					&dynamic_partition, 0);
-		if (err > 0)
-			err = add_mtd_partitions(omap_onenand_mtd,
-					dynamic_partition, err);
-		else if (1)
-			err = add_mtd_partitions(omap_onenand_mtd,
-					static_partition,
-					ARRAY_SIZE(static_partition));
-		else
+	err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0);
+	if (err > 0)
+		add_mtd_partitions(&info->mtd, info->parts, err);
+	else if (err < 0 && pdata->parts)
+		add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
+	else
 #endif
-			err = add_mtd_device(omap_onenand_mtd);
-		if (err)
-			goto out_buf;
-		break;
+		err = add_mtd_device(&info->mtd);
 
-	default:
-		printk(KERN_WARNING "Unsupported OneNAND device\n");
-		err = -ENXIO;
-		goto out_buf;
-	}
+	dev_set_drvdata(&pdev->dev, info);
 
 	return 0;
 
-out_buf:
-	onenand_release(omap_onenand_mtd);
-	iounmap(this->base);
-out_mtd:
-	kfree(omap_onenand_mtd);
-out:
+out_iounmap:
+	iounmap(info->onenand.base);
+out_release_mem_region:
+	release_mem_region(res->start, size);
+out_free_info:
+	kfree(info);
+
 	return err;
 }
 
-/*
- * Clean up routine
- */
-static void __exit omap_onenand_cleanup (void)
+static int __devexit omap_onenand_remove(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_onenand_info *info = dev_get_drvdata(&pdev->dev);
+	struct resource *res = pdev->resource;
+	unsigned long size = res->end - res->start + 1;
+
+	dev_set_drvdata(&pdev->dev, NULL);
+
+	if (info) {
+		if (info->parts)
+			del_mtd_partitions(&info->mtd);
+		else
+			del_mtd_device(&info->mtd);
+
+		onenand_release(&info->mtd);
+		release_mem_region(res->start, size);
+		iounmap(info->onenand.base);
+		kfree(info);
+	}
+
+	return 0;
+}
+
+static struct device_driver omap_onenand_driver = {
+	.name		= DRIVER_NAME,
+	.bus		= &platform_bus_type,
+	.probe		= omap_onenand_probe,
+	.remove		= __devexit_p(omap_onenand_remove),
+};
+
+MODULE_ALIAS(DRIVER_NAME);
+
+static int __init omap_onenand_init(void)
 {
-	struct onenand_chip *this = omap_onenand_mtd->priv;
+	return driver_register(&omap_onenand_driver);
+}
 
-	/* onenand_release frees MTD partitions, MTD structure
-	   and onenand internal buffers */
-	onenand_release(omap_onenand_mtd);
-	iounmap(this->base);
-	kfree(omap_onenand_mtd);
+static void __exit omap_onenand_exit(void)
+{
+	driver_unregister(&omap_onenand_driver);
 }
 
 module_init(omap_onenand_init);
-module_exit(omap_onenand_cleanup);
+module_exit(omap_onenand_exit);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -311,19 +311,21 @@ static int onenand_wait(struct mtd_info 
 	ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS);
 
 	if (ctrl & ONENAND_CTRL_ERROR) {
-		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x", ctrl);
-		return -EIO;
+		/* It maybe occur at initial bad block */
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: controller error = 0x%04x\n", ctrl);
+		/* Clear other interrupt bits for preventing ECC error */
+		interrupt &= ONENAND_INT_MASTER;
 	}
 
 	if (ctrl & ONENAND_CTRL_LOCK) {
-		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x", ctrl);
-		return -EIO;
+		DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: it's locked error = 0x%04x\n", ctrl);
+		return -EACCES;
 	}
 
 	if (interrupt & ONENAND_INT_READ) {
 		ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS);
 		if (ecc & ONENAND_ECC_2BIT_ALL) {
-			DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x", ecc);
+			DEBUG(MTD_DEBUG_LEVEL0, "onenand_wait: ECC error = 0x%04x\n", ecc);
 			return -EBADMSG;
 		}
 	}
@@ -379,6 +381,35 @@ static int onenand_read_bufferram(struct
 }
 
 /**
+ * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode
+ * @param mtd		MTD data structure
+ * @param area		BufferRAM area
+ * @param buffer	the databuffer to put/get data
+ * @param offset	offset to read from or write to
+ * @param count		number of bytes to read/write
+ *
+ * Read the BufferRAM area with Sync. Burst Mode
+ */
+static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area,
+		unsigned char *buffer, int offset, size_t count)
+{
+	struct onenand_chip *this = mtd->priv;
+	void __iomem *bufferram;
+
+	bufferram = this->base + area;
+
+	bufferram += onenand_bufferram_offset(mtd, area);
+
+	this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ);
+
+	memcpy(buffer, bufferram + offset, count);
+
+	this->mmcontrol(mtd, 0);
+
+	return 0;
+}
+
+/**
  * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area
  * @param mtd		MTD data structure
  * @param area		BufferRAM area
@@ -688,13 +719,11 @@ out:
  * onenand_verify_page - [GENERIC] verify the chip contents after a write
  * @param mtd		MTD device structure
  * @param buf		the databuffer to verify
- * @param block		block address
- * @param page		page address
  *
  * Check DataRAM area directly
  */
 static int onenand_verify_page(struct mtd_info *mtd, u_char *buf,
-	loff_t addr, int block, int page)
+	loff_t addr)
 {
 	struct onenand_chip *this = mtd->priv;
 	void __iomem *dataram0, *dataram1;
@@ -785,7 +814,7 @@ static int onenand_write_ecc(struct mtd_
 		written += thislen;
 
 		/* Only check verify write turn on */
-		ret = onenand_verify_page(mtd, (u_char *) buf, to, block, page);
+		ret = onenand_verify_page(mtd, (u_char *) buf, to);
 		if (ret) {
 			DEBUG(MTD_DEBUG_LEVEL0, "onenand_write_ecc: verify failed %d\n", ret);
 			goto out;
@@ -909,7 +938,7 @@ static int onenand_writev_ecc(struct mtd
 	u_char *eccbuf, struct nand_oobinfo *oobsel)
 {
 	struct onenand_chip *this = mtd->priv;
-	unsigned char buffer[mtd->oobblock], *pbuf;
+	unsigned char buffer[MAX_ONENAND_PAGESIZE], *pbuf;
 	size_t total_len, len;
 	int i, written = 0;
 	int ret = 0;
@@ -994,7 +1023,7 @@ static int onenand_writev_ecc(struct mtd
 
 
 		/* Only check verify write turn on */
-		ret = onenand_verify_page(mtd, (u_char *) pbuf, to, block, page);
+		ret = onenand_verify_page(mtd, (u_char *) pbuf, to);
 		if (ret) {
 			DEBUG(MTD_DEBUG_LEVEL0, "onenand_writev_ecc: verify failed %d\n", ret);
 			goto out;
@@ -1031,6 +1060,25 @@ static int onenand_writev(struct mtd_inf
 }
 
 /**
+ * onenand_block_checkbad - [GENERIC] Check if a block is marked bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset from device start
+ * @param getchip	0, if the chip is already selected
+ * @param allowbbt	1, if its allowed to access the bbt area
+ *
+ * Check, if the block is bad. Either by reading the bad block table or
+ * calling of the scan function.
+ */
+static int onenand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+
+	/* Return info from the table */
+	return bbm->isbad_bbt(mtd, ofs, allowbbt);
+}
+
+/**
  * onenand_erase - [MTD Interface] erase block(s)
  * @param mtd		MTD device structure
  * @param instr		erase instruction
@@ -1080,7 +1128,12 @@ static int onenand_erase(struct mtd_info
 
 	while (len) {
 
-		/* TODO Check badblock */
+		/* Check if we have a bad block, we do not erase bad blocks */
+		if (onenand_block_checkbad(mtd, addr, 0, 0)) {
+			printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr);
+			instr->state = MTD_ERASE_FAILED;
+			goto erase_exit;
+		}
 
 		this->command(mtd, ONENAND_CMD_ERASE, addr, block_size);
 
@@ -1132,34 +1185,70 @@ static void onenand_sync(struct mtd_info
 	onenand_release_device(mtd);
 }
 
+
 /**
  * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad
  * @param mtd		MTD device structure
  * @param ofs		offset relative to mtd start
+ *
+ * Check whether the block is bad
  */
 static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
 {
-	/*
-	 * TODO 
-	 * 1. Bad block table (BBT)
-	 *   -> using NAND BBT to support JFFS2
-	 * 2. Bad block management (BBM)
-	 *   -> bad block replace scheme
-	 *
-	 * Currently we do nothing
-	 */
-	return 0;
+	/* Check for invalid offset */
+	if (ofs > mtd->size)
+		return -EINVAL;
+
+	return onenand_block_checkbad(mtd, ofs, 1, 0);
+}
+
+/**
+ * onenand_default_block_markbad - [DEFAULT] mark a block bad
+ * @param mtd		MTD device structure
+ * @param ofs		offset from device start
+ *
+ * This is the default implementation, which can be overridden by
+ * a hardware specific driver.
+ */
+static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	u_char buf[2] = {0, 0};
+	size_t retlen;
+	int block;
+
+	/* Get block number */
+	block = ((int) ofs) >> bbm->bbt_erase_shift;
+        if (bbm->bbt)
+                bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
+
+        /* We write two bytes, so we dont have to mess with 16 bit access */
+        ofs += mtd->oobsize + (bbm->badblockpos & ~0x01);
+        return mtd->write_oob(mtd, ofs , 2, &retlen, buf);
 }
 
 /**
  * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad
  * @param mtd		MTD device structure
  * @param ofs		offset relative to mtd start
+ *
+ * Mark the block as bad
  */
 static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	/* see above */
-	return 0;
+	struct onenand_chip *this = mtd->priv;
+	int ret;
+
+	ret = onenand_block_isbad(mtd, ofs);
+	if (ret) {
+		/* If it was bad already, return success and do nothing */
+		if (ret > 0)
+			return 0;
+		return ret;
+	}
+
+	return this->block_markbad(mtd, ofs);
 }
 
 /**
@@ -1273,8 +1362,8 @@ static int onenand_check_maf(int manuf)
                         break;
         }
 
-        printk(KERN_DEBUG "OneNAND Manufacturer: %s\n",
-                onenand_manuf_ids[i].name);
+        printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n",
+                onenand_manuf_ids[i].name, manuf);
 
         return (i != ONENAND_MFR_UNKNOWN);
 }
@@ -1382,9 +1471,20 @@ int onenand_scan(struct mtd_info *mtd, i
 	if (!this->write_bufferram)
 		this->write_bufferram = onenand_write_bufferram;
 
+	if (!this->block_markbad)
+		this->block_markbad = onenand_default_block_markbad;
+	if (!this->scan_bbt)
+		this->scan_bbt = onenand_default_bbt;
+
 	if (onenand_probe(mtd))
 		return -ENXIO;
 
+	/* Set Sync. Burst Read after probing */
+	if (this->mmcontrol) {
+		printk(KERN_INFO "OneNAND Sync. Burst Read support\n");
+		this->read_bufferram = onenand_sync_read_bufferram;
+	}
+
 	this->state = FL_READY;
 	init_waitqueue_head(&this->wq);
 	spin_lock_init(&this->chip_lock);
@@ -1437,7 +1537,7 @@ int onenand_scan(struct mtd_info *mtd, i
 	/* Unlock whole block */
 	mtd->unlock(mtd, 0x0, this->chipsize);
 
-	return 0;
+	return this->scan_bbt(mtd);
 }
 
 /**
diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c
new file mode 100644
--- /dev/null
+++ b/drivers/mtd/onenand/onenand_bbt.c
@@ -0,0 +1,246 @@
+/*
+ *  linux/drivers/mtd/onenand/onenand_bbt.c
+ *
+ *  Bad Block Table support for the OneNAND driver
+ *
+ *  Copyright(c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Derived from nand_bbt.c
+ *
+ *  TODO:
+ *    Split BBT core and chip specific BBT.
+ */
+
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/compatmac.h>
+
+/**
+ * check_short_pattern - [GENERIC] check if a pattern is in the buffer
+ * @param buf		the buffer to search
+ * @param len		the length of buffer to search
+ * @param paglen	the pagelength
+ * @param td		search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block
+ * tables and good / bad block identifiers. Same as check_pattern, but
+ * no optional empty check and the pattern is expected to start
+ * at offset 0.
+ *
+ */
+static int check_short_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)
+{
+	int i;
+	uint8_t *p = buf;
+
+	/* Compare the pattern */
+	for (i = 0; i < td->len; i++) {
+		if (p[i] != td->pattern[i])
+			return -1;
+	}
+        return 0;
+}
+
+/**
+ * create_bbt - [GENERIC] Create a bad block table by scanning the device
+ * @param mtd		MTD device structure
+ * @param buf		temporary buffer
+ * @param bd		descriptor for the good/bad block search pattern
+ * @param chip		create the table for a specific chip, -1 read all chips.
+ *              Applies only if NAND_BBT_PERCHIP option is set
+ *
+ * Create a bad block table by scanning the device
+ * for the given good/bad block identify pattern
+ */
+static int create_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd, int chip)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int i, j, numblocks, len, scanlen;
+	int startblock;
+	loff_t from;
+	size_t readlen, ooblen;
+
+	printk(KERN_INFO "Scanning device for bad blocks\n");
+
+	len = 1;
+
+	/* We need only read few bytes from the OOB area */
+	scanlen = ooblen = 0;
+	readlen = bd->len;
+
+	/* chip == -1 case only */
+	/* Note that numblocks is 2 * (real numblocks) here;
+	 * see i += 2 below as it makses shifting and masking less painful
+	 */
+	numblocks = mtd->size >> (bbm->bbt_erase_shift - 1);
+	startblock = 0;
+	from = 0;
+
+	for (i = startblock; i < numblocks; ) {
+		int ret;
+
+		for (j = 0; j < len; j++) {
+			size_t retlen;
+
+			/* No need to read pages fully,
+			 * just read required OOB bytes */
+			ret = mtd->read_oob(mtd, from + j * mtd->oobblock + bd->offs,
+						readlen, &retlen, &buf[0]);
+
+			if (ret)
+				return ret;
+
+			if (check_short_pattern(&buf[j * scanlen], scanlen, mtd->oobblock, bd)) {
+				bbm->bbt[i >> 3] |= 0x03 << (i & 0x6);
+				printk(KERN_WARNING "Bad eraseblock %d at 0x%08x\n",
+					i >> 1, (unsigned int) from);
+				break;
+			}
+		}
+		i += 2;
+		from += (1 << bbm->bbt_erase_shift);
+	}
+
+	return 0;
+}
+
+
+/**
+ * onenand_memory_bbt - [GENERIC] create a memory based bad block table
+ * @param mtd		MTD device structure
+ * @param bd		descriptor for the good/bad block search pattern
+ *
+ * The function creates a memory based bbt by scanning the device
+ * for manufacturer / software marked good / bad blocks
+ */
+static inline int onenand_memory_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+	unsigned char data_buf[MAX_ONENAND_PAGESIZE];
+
+        bd->options &= ~NAND_BBT_SCANEMPTY;
+        return create_bbt(mtd, data_buf, bd, -1);
+}
+
+/**
+ * onenand_isbad_bbt - [OneNAND Interface] Check if a block is bad
+ * @param mtd		MTD device structure
+ * @param offs		offset in the device
+ * @param allowbbt	allow access to bad block table region
+ */
+static int onenand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int block;
+	uint8_t res;
+
+	/* Get block number * 2 */
+	block = (int) (offs >> (bbm->bbt_erase_shift - 1));
+	res = (bbm->bbt[block >> 3] >> (block & 0x06)) & 0x03;
+
+	DEBUG(MTD_DEBUG_LEVEL2, "onenand_isbad_bbt: bbt info for offs 0x%08x: (block %d) 0x%02x\n",
+		(unsigned int) offs, block >> 1, res);
+
+	switch ((int) res) {
+	case 0x00:	return 0;
+	case 0x01:	return 1;
+	case 0x02:	return allowbbt ? 0 : 1;
+	}
+
+	return 1;
+}
+
+/**
+ * onenand_scan_bbt - [OneNAND Interface] scan, find, read and maybe create bad block table(s)
+ * @param mtd		MTD device structure
+ * @param bd		descriptor for the good/bad block search pattern
+ *
+ * The function checks, if a bad block table(s) is/are already
+ * available. If not it scans the device for manufacturer
+ * marked good / bad blocks and writes the bad block table(s) to
+ * the selected place.
+ *
+ * The bad block table memory is allocated here. It must be freed
+ * by calling the onenand_free_bbt function.
+ *
+ */
+int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm = this->bbm;
+	int len, ret = 0;
+
+	len = mtd->size >> (this->erase_shift + 2);
+	/* Allocate memory (2bit per block) */
+	bbm->bbt = kmalloc(len, GFP_KERNEL);
+	if (!bbm->bbt) {
+		printk(KERN_ERR "onenand_scan_bbt: Out of memory\n");
+		return -ENOMEM;
+	}
+	/* Clear the memory bad block table */
+	memset(bbm->bbt, 0x00, len);
+
+	/* Set the bad block position */
+	bbm->badblockpos = ONENAND_BADBLOCK_POS;
+
+	/* Set erase shift */
+	bbm->bbt_erase_shift = this->erase_shift;
+
+	if (!bbm->isbad_bbt)
+		bbm->isbad_bbt = onenand_isbad_bbt;
+
+	/* Scan the device to build a memory based bad block table */
+	if ((ret = onenand_memory_bbt(mtd, bd))) {
+		printk(KERN_ERR "onenand_scan_bbt: Can't scan flash and build the RAM-based BBT\n");
+		kfree(bbm->bbt);
+		bbm->bbt = NULL;
+	}
+
+	return ret;
+}
+
+/*
+ * Define some generic bad / good block scan pattern which are used
+ * while scanning a device for factory marked good / bad blocks.
+ */
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr largepage_memorybased = {
+	.options = 0,
+	.offs = 0,
+	.len = 2,
+	.pattern = scan_ff_pattern,
+};
+
+/**
+ * onenand_default_bbt - [OneNAND Interface] Select a default bad block table for the device
+ * @param mtd		MTD device structure
+ *
+ * This function selects the default bad block table
+ * support for the device and calls the onenand_scan_bbt function
+ */
+int onenand_default_bbt(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct bbm_info *bbm;
+
+	this->bbm = kmalloc(sizeof(struct bbm_info), GFP_KERNEL);
+	if (!this->bbm)
+		return -ENOMEM;
+
+	bbm = this->bbm;
+
+	memset(bbm, 0, sizeof(struct bbm_info));
+
+	/* 1KB page has same configuration as 2KB page */
+	if (!bbm->badblock_pattern)
+		bbm->badblock_pattern = &largepage_memorybased;
+
+	return onenand_scan_bbt(mtd, bbm->badblock_pattern);
+}
+
+EXPORT_SYMBOL(onenand_scan_bbt);
+EXPORT_SYMBOL(onenand_default_bbt);
diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h
new file mode 100644
--- /dev/null
+++ b/include/linux/mtd/bbm.h
@@ -0,0 +1,122 @@
+/*
+ *  linux/include/linux/mtd/bbm.h
+ *
+ *  NAND family Bad Block Management (BBM) header file
+ *    - Bad Block Table (BBT) implementation
+ *
+ *  Copyright (c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ *  Copyright (c) 2000-2005
+ *  Thomas Gleixner <tglx@linuxtronix.de>
+ *
+ */
+#ifndef __LINUX_MTD_BBM_H
+#define __LINUX_MTD_BBM_H
+
+/* The maximum number of NAND chips in an array */
+#define NAND_MAX_CHIPS		8
+
+/**
+ * struct nand_bbt_descr - bad block table descriptor
+ * @param options	options for this descriptor
+ * @param pages		the page(s) where we find the bbt, used with
+ * 			option BBT_ABSPAGE when bbt is searched,
+ * 			then we store the found bbts pages here.
+ *			Its an array and supports up to 8 chips now
+ * @param offs		offset of the pattern in the oob area of the page
+ * @param veroffs	offset of the bbt version counter in the oob are of the page
+ * @param version	version read from the bbt page during scan
+ * @param len		length of the pattern, if 0 no pattern check is performed
+ * @param maxblocks	maximum number of blocks to search for a bbt. This number of
+ *			blocks is reserved at the end of the device 
+ *			where the tables are written.
+ * @param reserved_block_code	if non-0, this pattern denotes a reserved
+ *			(rather than bad) block in the stored bbt
+ * @param pattern	pattern to identify bad block table or factory marked
+ *			good / bad blocks, can be NULL, if len = 0
+ *
+ * Descriptor for the bad block table marker and the descriptor for the
+ * pattern which identifies good and bad blocks. The assumption is made
+ * that the pattern and the version count are always located in the oob area
+ * of the first block.
+ */
+struct nand_bbt_descr {
+	int options;
+	int pages[NAND_MAX_CHIPS];
+	int offs;
+	int veroffs;
+	uint8_t version[NAND_MAX_CHIPS];
+	int len;
+	int maxblocks;
+	int reserved_block_code;
+	uint8_t *pattern;
+};
+
+/* Options for the bad block table descriptors */
+
+/* The number of bits used per block in the bbt on the device */
+#define NAND_BBT_NRBITS_MSK	0x0000000F
+#define NAND_BBT_1BIT		0x00000001
+#define NAND_BBT_2BIT		0x00000002
+#define NAND_BBT_4BIT		0x00000004
+#define NAND_BBT_8BIT		0x00000008
+/* The bad block table is in the last good block of the device */
+#define NAND_BBT_LASTBLOCK	0x00000010
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_ABSPAGE	0x00000020
+/* The bbt is at the given page, else we must scan for the bbt */
+#define NAND_BBT_SEARCH		0x00000040
+/* bbt is stored per chip on multichip devices */
+#define NAND_BBT_PERCHIP	0x00000080
+/* bbt has a version counter at offset veroffs */
+#define NAND_BBT_VERSION	0x00000100
+/* Create a bbt if none axists */
+#define NAND_BBT_CREATE		0x00000200
+/* Search good / bad pattern through all pages of a block */
+#define NAND_BBT_SCANALLPAGES	0x00000400
+/* Scan block empty during good / bad block scan */
+#define NAND_BBT_SCANEMPTY	0x00000800
+/* Write bbt if neccecary */
+#define NAND_BBT_WRITE		0x00001000
+/* Read and write back block contents when writing bbt */
+#define NAND_BBT_SAVECONTENT	0x00002000
+/* Search good / bad pattern on the first and the second page */
+#define NAND_BBT_SCAN2NDPAGE	0x00004000
+
+/* The maximum number of blocks to scan for a bbt */
+#define NAND_BBT_SCAN_MAXBLOCKS	4
+
+/*
+ * Constants for oob configuration
+ */
+#define ONENAND_BADBLOCK_POS	0
+
+/**
+ * struct bbt_info - [GENERIC] Bad Block Table data structure
+ * @param bbt_erase_shift	[INTERN] number of address bits in a bbt entry
+ * @param badblockpos		[INTERN] position of the bad block marker in the oob area
+ * @param bbt			[INTERN] bad block table pointer
+ * @param badblock_pattern	[REPLACEABLE] bad block scan pattern used for initial bad block scan
+ * @param priv			[OPTIONAL] pointer to private bbm date
+ */
+struct bbm_info {
+	int bbt_erase_shift;
+	int badblockpos;
+	int options;
+
+	uint8_t *bbt;
+
+	int (*isbad_bbt)(struct mtd_info *mtd, loff_t ofs, int allowbbt);
+
+	/* TODO Add more NAND specific fileds */
+	struct nand_bbt_descr *badblock_pattern;
+
+	void *priv;
+};
+
+/* OneNAND BBT interface */
+extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
+extern int onenand_default_bbt(struct mtd_info *mtd);
+
+#endif	/* __LINUX_MTD_BBM_H */
diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h
--- a/include/linux/mtd/onenand.h
+++ b/include/linux/mtd/onenand.h
@@ -14,8 +14,10 @@
 
 #include <linux/spinlock.h>
 #include <linux/mtd/onenand_regs.h>
+#include <linux/mtd/bbm.h>
 
 #define MAX_BUFFERRAM		2
+#define MAX_ONENAND_PAGESIZE	(2048 + 64)
 
 /* Scan and identify a OneNAND device */
 extern int onenand_scan(struct mtd_info *mtd, int max_chips);
@@ -67,10 +69,14 @@ struct onenand_bufferram {
  * @param wait		[REPLACEABLE] hardware specific function for wait on ready
  * @param read_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
  * @param write_bufferram	[REPLACEABLE] hardware specific function for BufferRAM Area
+ * @param read_word	[REPLACEABLE] hardware specific function for read register of OneNAND
+ * @param write_word	[REPLACEABLE] hardware specific function for write register of OneNAND
+ * @param scan_bbt	[REPLACEALBE] hardware specific function for scaning Bad block Table
  * @param chip_lock	[INTERN] spinlock used to protect access to this structure and the chip
  * @param wq		[INTERN] wait queue to sleep on if a OneNAND operation is in progress
  * @param state		[INTERN] the current state of the OneNAND device
  * @param autooob	[REPLACEABLE] the default (auto)placement scheme
+ * @param bbm		[REPLACEABLE] pointer to Bad Block Management 
  * @param priv		[OPTIONAL] pointer to private chip date
  */
 struct onenand_chip {
@@ -95,6 +101,9 @@ struct onenand_chip {
 			const unsigned char *buffer, int offset, size_t count);
 	unsigned short (*read_word)(void __iomem *addr);
 	void (*write_word)(unsigned short value, void __iomem *addr);
+	void (*mmcontrol)(struct mtd_info *mtd, int sync_read);
+	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
+	int (*scan_bbt)(struct mtd_info *mtd);
 
 	spinlock_t		chip_lock;
 	wait_queue_head_t	wq;
@@ -102,13 +111,23 @@ struct onenand_chip {
 
 	struct nand_oobinfo	*autooob;
 
+	void 			*bbm;
+
 	void			*priv;
 };
 
+/*
+ * Helper macros
+ */
 #define ONENAND_CURRENT_BUFFERRAM(this)		(this->bufferram_index)
 #define ONENAND_NEXT_BUFFERRAM(this)		(this->bufferram_index ^ 1)
 #define ONENAND_SET_NEXT_BUFFERRAM(this)	(this->bufferram_index ^= 1)
 
+#define ONENAND_GET_SYS_CFG1(this)					\
+	(this->read_word(this->base + ONENAND_REG_SYS_CFG1))
+#define ONENAND_SET_SYS_CFG1(v, this)					\
+	(this->write_word(v, this->base + ONENAND_REG_SYS_CFG1))
+
 /*
  * Options bits
  */
diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h
--- a/include/linux/mtd/onenand_regs.h
+++ b/include/linux/mtd/onenand_regs.h
@@ -121,8 +121,21 @@
  * System Configuration 1 Register F221h (R, R/W)
  */
 #define ONENAND_SYS_CFG1_SYNC_READ	(1 << 15)
-#define ONENAND_SYS_CFG1_BRL		(1 << 12)
-#define ONENAND_SYS_CFG1_BL		(1 << 9)
+#define ONENAND_SYS_CFG1_BRL_7		(7 << 12)
+#define ONENAND_SYS_CFG1_BRL_6		(6 << 12)
+#define ONENAND_SYS_CFG1_BRL_5		(5 << 12)
+#define ONENAND_SYS_CFG1_BRL_4		(4 << 12)
+#define ONENAND_SYS_CFG1_BRL_3		(3 << 12)
+#define ONENAND_SYS_CFG1_BRL_10		(2 << 12)
+#define ONENAND_SYS_CFG1_BRL_9		(1 << 12)
+#define ONENAND_SYS_CFG1_BRL_8		(0 << 12)
+#define ONENAND_SYS_CFG1_BRL_SHIFT	(12)
+#define ONENAND_SYS_CFG1_BL_32		(4 << 9)
+#define ONENAND_SYS_CFG1_BL_16		(3 << 9)
+#define ONENAND_SYS_CFG1_BL_8		(2 << 9)
+#define ONENAND_SYS_CFG1_BL_4		(1 << 9)
+#define ONENAND_SYS_CFG1_BL_CONT	(0 << 9)
+#define ONENAND_SYS_CFG1_BL_SHIFT	(9)
 #define ONENAND_SYS_CFG1_NO_ECC		(1 << 8)
 #define ONENAND_SYS_CFG1_RDY		(1 << 7)
 #define ONENAND_SYS_CFG1_INT		(1 << 6)
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
--- a/include/asm-arm/mach/flash.h
+++ b/include/asm-arm/mach/flash.h
@@ -11,6 +11,7 @@
 #define ASMARM_MACH_FLASH_H

 struct mtd_partition;
+struct mtd_info;

 /*
  * map_name:   the map probe function name
@@ -31,4 +32,16 @@ struct flash_platform_data {
        unsigned int    nr_parts;
 };

+/**
+ * struct onenand_platform_data - platform data describing OneNAND flash banks
+ * @param mmcontrol    Handle memroy control for Sync. Burst Read
+ * @param parts                optional array of mtd_partitions for static partioning
+ * @param nr_parts     number of mtd_partitions for static partitioning
+ */
+struct onenand_platform_data {
+       void            (*mmcontrol)(struct mtd_info *mtd, int sync_read);
+       struct mtd_partition *parts;
+       unsigned int    nr_parts;
+};
+
 #endif

Re: [PATCH] OneNAND MTD support

[Bernhard Priewasser]

> I'm sorry to bother you
No, I'm sorry to bother YOU. You did the work, and you did it good, so 
you bother noone at all.

> And here's one total patch including previous three patches plus some minor
> patches.
It patches and compiles error free on a 2.6.11 kernel with recent MTD.

> If do you have any question. Please let me know
I will...

Regards
Bernhard

[PATCH] OneNAND: simulator support

[Kyungmin Park]

Hi

This patch enables OneNAND simulator on OneNAND MTD.

Any comments are welcome.

Begards.

Kyungmin Park

--


diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -35,4 +35,11 @@ config MTD_ONENAND_SYNC_READ
 	help
 	  This enables support for Sync. Burst Read.
 
+config MTD_ONENAND_SIM
+	tristate "Support for OneNAND flash simulator"
+	depends on MTD_ONENAND
+	help
+	  The simulator may simulate verious OneNAND flash chips for the
+          MTD onenand layer.
+
 endmenu
diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
--- a/drivers/mtd/onenand/Makefile
+++ b/drivers/mtd/onenand/Makefile
@@ -8,4 +8,7 @@ obj-$(CONFIG_MTD_ONENAND)		+= onenand.o
 # Board specific.
 obj-$(CONFIG_MTD_ONENAND_OMAP)		+= omap-onenand.o
 
+# Simulator
+obj-$(CONFIG_MTD_ONENAND_SIM)		+= onenand_sim.o
+
 onenand-objs = onenand_base.o onenand_bbt.o
diff --git a/drivers/mtd/onenand/onenand_sim.c
b/drivers/mtd/onenand/onenand_sim.c
new file mode 100644
--- /dev/null
+++ b/drivers/mtd/onenand/onenand_sim.c
@@ -0,0 +1,464 @@
+/*
+ *  linux/drivers/mtd/onenand/simulator.c
+ *
+ *  The OneNAND simulator
+ *
+ *  Copyright(c) 2005 Samsung Electronics
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+
+#include <asm/io.h>
+#include <asm/sizes.h>
+
+#ifndef CONFIG_ONENAND_SIM_MANUFACTURER
+#define CONFIG_ONENAND_SIM_MANUFACTURER		0xec
+#endif
+#ifndef CONFIG_ONENAND_SIM_DEVICE_ID
+#define CONFIG_ONENAND_SIM_DEVICE_ID		0x04
+#endif
+#ifndef CONFIG_ONENAND_SIM_VERSION_ID
+#define CONFIG_ONENAND_SIM_VERSION_ID		0x1e
+#endif
+
+static int manuf_id = CONFIG_ONENAND_SIM_MANUFACTURER;
+static int device_id = CONFIG_ONENAND_SIM_DEVICE_ID;
+static int version_id = CONFIG_ONENAND_SIM_VERSION_ID;
+
+struct onenand_flash {
+	void __iomem	*base;
+	void __iomem	*data;
+};
+
+#define ONENAND_CORE(flash)	(flash->data)
+
+#define ONENAND_MAIN_AREA(this, offset)
\
+	(this->base + ONENAND_DATARAM + offset)
+
+#define ONENAND_SPARE_AREA(this, offset)				\
+	(this->base + ONENAND_SPARERAM + offset)
+
+#define ONENAND_GET_WP_STATUS(this)					\
+	(readw(this->base + ONENAND_REG_WP_STATUS))
+
+#define ONENAND_SET_WP_STATUS(v, this)					\
+	(writew(v, this->base + ONENAND_REG_WP_STATUS))
+
+/* It has all 0xff chars */
+static unsigned char *ffchars;
+
+/*
+ * OneNAND simulator mtd
+ */
+struct mtd_info *onenand_sim;
+
+
+/**
+ * onenand_lock_handle - Handle Lock scheme
+ * @param this		OneNAND device structure
+ * @param cmd		The command to be sent
+ *
+ * Send lock command to OneNAND device.
+ * The lock scheme is depends on chip type.
+ */
+static void onenand_lock_handle(struct onenand_chip *this, int cmd)
+{
+	int block_lock_scheme;
+	int status;
+
+	status = ONENAND_GET_WP_STATUS(this);
+	block_lock_scheme = !(this->options & ONENAND_CONT_LOCK);
+	
+	switch (cmd) {
+	case ONENAND_CMD_UNLOCK:
+		if (block_lock_scheme)
+			ONENAND_SET_WP_STATUS(ONENAND_WP_US, this);
+		else
+			ONENAND_SET_WP_STATUS(status | ONENAND_WP_US, this);
+		break;
+
+	case ONENAND_CMD_LOCK:
+		if (block_lock_scheme)
+			ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this);
+		else
+			ONENAND_SET_WP_STATUS(status | ONENAND_WP_LS, this);
+		break;
+
+	case ONENAND_CMD_LOCK_TIGHT:
+		if (block_lock_scheme)
+			ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this);
+		else
+			ONENAND_SET_WP_STATUS(status | ONENAND_WP_LTS,
this);
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * onenand_bootram_handle - Handle BootRAM area
+ * @param this		OneNAND device structure
+ * @param cmd		The command to be sent
+ *
+ * Emulate BootRAM area. It is possible to do basic operation using
BootRAM.
+ */
+static void onenand_bootram_handle(struct onenand_chip *this, int cmd)
+{
+	switch (cmd) {
+	case ONENAND_CMD_READID:
+		writew(manuf_id, this->base);
+		writew(device_id, this->base + 2);
+		writew(version_id, this->base + 4);
+		break;
+
+	default:
+		/* REVIST: Handle other commands */
+		break;
+	}
+}
+
+/**
+ * onenand_update_interrupt - Set interrupt register
+ * @param this		OneNAND device structure
+ * @param cmd		The command to be sent
+ *
+ * Update interrupt register. The status is depends on command.
+ */
+static void onenand_update_interrupt(struct onenand_chip *this, int cmd)
+{
+	int interrupt = ONENAND_INT_MASTER;
+
+	switch (cmd) {
+	case ONENAND_CMD_READ:
+	case ONENAND_CMD_READOOB:
+		interrupt |= ONENAND_INT_READ;
+		break;
+
+	case ONENAND_CMD_PROG:
+	case ONENAND_CMD_PROGOOB:
+		interrupt |= ONENAND_INT_WRITE;
+		break;
+
+	case ONENAND_CMD_ERASE:
+		interrupt |= ONENAND_INT_ERASE;
+		break;
+
+	case ONENAND_CMD_RESET:
+		interrupt |= ONENAND_INT_RESET;
+		break;
+
+	default:
+		break;
+	}
+
+	writew(interrupt, this->base + ONENAND_REG_INTERRUPT);
+}
+
+/**
+ * onenand_check_overwrite - Check over-write if happend
+ * @param dest		The destination pointer
+ * @param src		The source pointer
+ * @param count		The length to be check
+ * @return 		0 on same, otherwise 1
+ *
+ * Compare the source with destination
+ */
+static int onenand_check_overwrite(void *dest, void *src, size_t count)
+{
+	unsigned int *s = (unsigned int *) src;
+	unsigned int *d = (unsigned int *) dest;
+	int i;
+	count >>= 2;
+
+	for (i = 0; i < count; i++)
+		if ((*s++ ^ *d++) != 0)
+			return 1;
+
+	return 0;
+}
+
+/**
+ * onenand_data_handle - Handle OneNAND Core and DataRAM
+ * @param this		OneNAND device structure
+ * @param cmd		The command to be sent
+ * @param dataram	Which dataram used
+ * @param offset	The offset to OneNAND Core
+ *
+ * Copy data from OneNAND Core to DataRAM (read)
+ * Copy data from DataRAM to OneNAND Core (write)
+ * Erase the OneNAND Core (erase)
+ */
+static void onenand_data_handle(struct onenand_chip *this, int cmd,
+					int dataram, unsigned int offset)
+{
+	struct onenand_flash *flash = this->priv;
+	int main_offset, spare_offset;
+	void __iomem *src;
+	void __iomem *dest;
+
+	if (dataram) {
+		main_offset = onenand_sim->oobblock;
+		spare_offset = onenand_sim->oobsize;
+	} else {
+		main_offset = 0;
+		spare_offset = 0;
+	}
+
+	switch (cmd) {
+	case ONENAND_CMD_READ:
+		src = ONENAND_CORE(flash) + offset;
+		dest = ONENAND_MAIN_AREA(this, main_offset);
+		memcpy(dest, src, onenand_sim->oobblock);
+		/* Fall through */
+
+	case ONENAND_CMD_READOOB:
+		src = ONENAND_CORE(flash) + this->chipsize + (offset >> 5);
+		dest = ONENAND_SPARE_AREA(this, spare_offset);
+		memcpy(dest, src, onenand_sim->oobsize);
+		break;
+
+	case ONENAND_CMD_PROG:
+		src = ONENAND_MAIN_AREA(this, main_offset);
+		dest = ONENAND_CORE(flash) + offset;
+		if (memcmp(dest, ffchars, onenand_sim->oobblock) &&
+		    onenand_check_overwrite(dest, src,
onenand_sim->oobblock))
+			printk(KERN_ERR "over-write happend at 0x%08x\n",
offset);
+		memcpy(dest, src, onenand_sim->oobblock);
+		/* Fall through */
+
+	case ONENAND_CMD_PROGOOB:
+		src = ONENAND_SPARE_AREA(this, spare_offset);
+		/* Check all data is 0xff chars */
+		if (!memcmp(src, ffchars, onenand_sim->oobsize))
+			break;
+
+		dest = ONENAND_CORE(flash) + this->chipsize + (offset >> 5);
+		if (memcmp(dest, ffchars, onenand_sim->oobsize) &&
+		    onenand_check_overwrite(dest, src,
onenand_sim->oobsize)) 
+			printk(KERN_ERR "OOB: over-write happend at
0x%08x\n", offset);
+		memcpy(dest, src, onenand_sim->oobsize);
+		break;
+
+	case ONENAND_CMD_ERASE:
+		memset(ONENAND_CORE(flash) + offset, 0xff, (1 <<
this->erase_shift));
+		break;
+
+	default:
+		break;
+	}
+}
+
+/**
+ * onenand_command_handle - Handle command
+ * @param this		OneNAND device structure
+ * @param cmd		The command to be sent
+ *
+ * Emulate OneNAND command.
+ */
+static void onenand_command_handle(struct onenand_chip *this, int cmd)
+{
+	unsigned long offset = 0;
+	int block = -1, page = -1, bufferram = -1;
+	int dataram = 0;
+
+	switch (cmd) {
+	case ONENAND_CMD_UNLOCK:
+	case ONENAND_CMD_LOCK:
+	case ONENAND_CMD_LOCK_TIGHT:
+		onenand_lock_handle(this, cmd);
+		break;
+
+	case ONENAND_CMD_BUFFERRAM:
+		/* Do nothing */
+		return;
+
+	default:
+		block = (int) readw(this->base +
ONENAND_REG_START_ADDRESS1);
+		if (block & (1 << ONENAND_DDP_SHIFT)) {
+			block &= ~(1 << ONENAND_DDP_SHIFT);
+			/* The half of chip block */
+			block += this->chipsize >> (this->erase_shift + 1);
+		}
+		if (cmd == ONENAND_CMD_ERASE)
+			break;
+
+		page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
+		page = (page >> ONENAND_FPA_SHIFT);
+		bufferram = (int) readw(this->base +
ONENAND_REG_START_BUFFER);
+		bufferram >>= ONENAND_BSA_SHIFT;
+		bufferram &= ONENAND_BSA_DATARAM1;
+		dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0;
+		break;
+	}
+
+	if (block != -1)
+		offset += block << this->erase_shift;
+
+	if (page != -1)
+		offset += page << this->page_shift;
+
+	onenand_data_handle(this, cmd, dataram, offset);
+
+	onenand_update_interrupt(this, cmd);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Emulate write operation
+ * @param value		value to write
+ * @param addr		address to write
+ *
+ * Write OneNAND reigser with value
+ */
+static void onenand_writew(unsigned short value, void __iomem *addr)
+{
+	struct onenand_chip *this = onenand_sim->priv;
+
+	/* BootRAM handling */
+	if (addr < this->base + ONENAND_DATARAM) {
+		onenand_bootram_handle(this, value);
+		return;
+	}
+	/* Command handling */
+	if (addr == this->base + ONENAND_REG_COMMAND)
+		onenand_command_handle(this, value);
+
+	writew(value, addr);
+}
+
+/**
+ * flash_init - Initialize OneNAND simulator
+ * @param flash		OneNAND simulaotr data strucutres
+ *
+ * Initialize OneNAND simulator.
+ */
+static int __init flash_init(struct onenand_flash *flash)
+{
+	int density, size;
+	int buffer_size;
+
+	flash->base = kmalloc(SZ_128K, GFP_KERNEL);
+	if (!flash->base) {
+		printk(KERN_ERR "Unalbe to allocate base address.\n");
+		return -ENOMEM;
+	}
+
+	memset(flash->base, 0, SZ_128K);
+
+	density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+	size = ((16 << 20) << density);
+
+	ONENAND_CORE(flash) = vmalloc(size + (size >> 5));
+	if (!ONENAND_CORE(flash)) {
+		printk(KERN_ERR "Unalbe to allocate nand core address.\n");
+		kfree(flash->base);
+		return -ENOMEM;
+	}
+
+	memset(ONENAND_CORE(flash), 0xff, size + (size >> 5));
+
+	/* Setup registers */
+	writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID);
+	writew(device_id, flash->base + ONENAND_REG_DEVICE_ID);
+	writew(version_id, flash->base + ONENAND_REG_VERSION_ID);
+
+	if (density < 2)
+		buffer_size = 0x0400;	/* 1KB page */
+	else
+		buffer_size = 0x0800;	/* 2KB page */
+	writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE);
+		
+	return 0;
+}
+
+/**
+ * flash_exit - Clean up OneNAND simulator
+ * @param flash		OneNAND simulaotr data strucutres
+ *
+ * Clean up OneNAND simulator.
+ */
+static void flash_exit(struct onenand_flash *flash)
+{
+	vfree(ONENAND_CORE(flash));
+	kfree(flash->base);
+	kfree(flash);
+}
+
+static int __init onenand_sim_init(void)
+{
+	struct onenand_chip *this;
+	struct onenand_flash *flash;
+	int len;
+
+	/* Allocate all 0xff chars pointer */
+	ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL);
+	if (!ffchars) {
+		printk(KERN_ERR "Unable to allocate ff chars.\n");
+		return -ENOMEM;
+	}
+	memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE);
+
+	len = sizeof(struct mtd_info) + sizeof(struct onenand_chip) + sizeof
(struct onenand_flash);
+
+	/* Allocate OneNAND simulator mtd pointer */
+	onenand_sim = kmalloc(len, GFP_KERNEL);
+	if (!onenand_sim) {
+		printk(KERN_ERR "Unable to allocate core structures.\n");
+		kfree(ffchars);
+		return -ENOMEM;
+	}
+
+	memset(onenand_sim, 0, len);
+
+	this = (struct onenand_chip *) (onenand_sim + 1);
+	/* Override write_word function */
+	this->write_word = onenand_writew;
+
+	flash = (struct onenand_flash *) (this + 1);
+
+	if (flash_init(flash)) {
+		printk(KERN_ERR "Unable to allocat flash.\n");
+		kfree(ffchars);
+		kfree(onenand_sim);
+		return -ENOMEM;
+	}
+
+	this->base = flash->base;
+	this->priv = flash;
+	onenand_sim->priv = this;
+
+	if (onenand_scan(onenand_sim, 1)) {
+		kfree(ffchars);
+		kfree(onenand_sim);
+		flash_exit(flash);
+		return -ENXIO;
+	}
+
+	add_mtd_device(onenand_sim);
+
+	return 0;
+}
+
+static void __exit onenand_sim_exit(void)
+{
+	struct onenand_chip *this = onenand_sim->priv;
+	struct onenand_flash *flash = this->priv;
+
+	kfree(ffchars);
+	onenand_release(onenand_sim);
+	flash_exit(flash);
+	kfree(onenand_sim);
+}
+
+module_init(onenand_sim_init);
+module_exit(onenand_sim_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("The OneNAND flash simulator");