* [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D
@ 2021-12-27 9:16 vincent
2021-12-27 9:16 ` [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix vincent
0 siblings, 1 reply; 8+ messages in thread
From: vincent @ 2021-12-27 9:16 UTC (permalink / raw)
To: linux-mtd; +Cc: Nick Hainke, David Bauer
From: Nick Hainke <vincent@systemli.org>
Macronix MX25L6405D supports locking with four block-protection bits.
Currently, the driver only sets three bits. If the bootloader does not
sustain the flash chip in an unlocked state, the flash might be
non-writeable. Add the corresponding flag to enable locking support with
four bits in the status register.
Tested on Nanostation M2 XM.
Similar to commit 7ea40b54e83b ("mtd: spi-nor: enable locking support for
MX25L12805D")
Signed-off-by: David Bauer <mail@david-bauer.net>
Signed-off-by: Nick Hainke <vincent@systemli.org>
---
drivers/mtd/spi-nor/macronix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 27498ed0cc0d..f07b59a4120a 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -41,7 +41,8 @@ static const struct flash_info macronix_parts[] = {
{ "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
- { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
+ { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
{ "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
{ "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ |
--
2.34.1
______________________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2021-12-27 9:16 [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D vincent
@ 2021-12-27 9:16 ` vincent
2021-12-29 14:08 ` Tudor.Ambarus
0 siblings, 1 reply; 8+ messages in thread
From: vincent @ 2021-12-27 9:16 UTC (permalink / raw)
To: linux-mtd; +Cc: Nick Hainke, David Bauer
From: Nick Hainke <vincent@systemli.org>
Macronix flash chips seem to consist of only one status register.
These chips will not work with the "16-bit Write Status (01h) Command".
Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
Tested with MX25L6405D.
Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
lock()/unlock()")
Signed-off-by: David Bauer <mail@david-bauer.net>
Signed-off-by: Nick Hainke <vincent@systemli.org>
---
drivers/mtd/spi-nor/macronix.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index f07b59a4120a..d530ab0b3b13 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -94,6 +94,7 @@ static void macronix_default_init(struct spi_nor *nor)
{
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
}
static const struct spi_nor_fixups macronix_fixups = {
--
2.34.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2021-12-27 9:16 ` [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix vincent
@ 2021-12-29 14:08 ` Tudor.Ambarus
2021-12-31 9:10 ` Nick
0 siblings, 1 reply; 8+ messages in thread
From: Tudor.Ambarus @ 2021-12-29 14:08 UTC (permalink / raw)
To: vincent, linux-mtd; +Cc: mail
On 12/27/21 11:16 AM, vincent@systemli.org wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Nick Hainke <vincent@systemli.org>
>
> Macronix flash chips seem to consist of only one status register.
> These chips will not work with the "16-bit Write Status (01h) Command".
> Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
Hi, Vincent!
Have you checked all the existing macronix flash_info entries and determined
that neither of them support SNOR_F_HAS_16BIT_SR? Per manufacturer settings
are a bit sensible because we can't predict what manufacturers are doing with
new flash designs and whether they'll respect their "legacy" flash settings or
not. Thus I'm a bit reluctant in adding per manufacturer settings.
Cheers,
ta
>
> Tested with MX25L6405D.
>
> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
> lock()/unlock()")
>
> Signed-off-by: David Bauer <mail@david-bauer.net>
> Signed-off-by: Nick Hainke <vincent@systemli.org>
> ---
> drivers/mtd/spi-nor/macronix.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index f07b59a4120a..d530ab0b3b13 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -94,6 +94,7 @@ static void macronix_default_init(struct spi_nor *nor)
> {
> nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
> nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> }
>
> static const struct spi_nor_fixups macronix_fixups = {
> --
> 2.34.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2021-12-29 14:08 ` Tudor.Ambarus
@ 2021-12-31 9:10 ` Nick
2021-12-31 9:50 ` Nick
2022-01-19 15:49 ` Michael Walle
0 siblings, 2 replies; 8+ messages in thread
From: Nick @ 2021-12-31 9:10 UTC (permalink / raw)
To: Tudor.Ambarus, linux-mtd; +Cc: mail
I looked now through all datasheets I found and the sizes of the status
register. However, I did not find any datasheet for the "mx66l1g55g".
However, I am not sure if I maybe miss something to see if
"SNOR_F_HAS_16BIT_SR" is supported. I only looked at the status register
size.
It is also now merged in OpenWrt, so maybe we wait some time and see if
someone complains?
https://github.com/openwrt/openwrt/commit/83b5fbddf28e943e8c90b4099a1e36d158f5995c
Otherwise, I documented my findings:
mx25l512e: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7398/MX25L512E,%203V,%20512Kb,%20v1.4.pdf
(slide 13)
mx25l2005a: 8bit
https://www.macrogroup.ru/sites/default/files/uploads/mx25l2005_3v_2mb_v1.9.pdf
(slide 12)
mx25l4005a: 8bit
https://pdf1.alldatasheet.com/datasheet-pdf/view/267913/MCNIX/MX25L4005A.html
(slide 11)
mx25l8005: 8bit
https://pdf1.alldatasheet.com/datasheet-pdf/view/267915/MCNIX/MX25L8005.html
(slide 11)
mx25l1606e: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7465/MX25L1606E,%203V,%2016Mb,%20v1.9.pdf
(slide 18)
mx25l3205d: 8bit
https://pdf1.alldatasheet.com/datasheet-pdf/view/267908/MCNIX/MX25L3205D.html
(slide 19)
mx25l3255e: 8bit
https://www.application-datasheet.com/pdf/macronix/mx25l3255em2i-10g.pdf
(slide 22)
mx25l6405d: 8bit
https://datasheet.octopart.com/MX25L6405DZNI-12G-Macronix-datasheet-8325093.pdf
(slide 19)
mx25u2033e: 8bit
https://datasheetspdf.com/pdf-file/792587/MACRONIX/MX25U2033E/1 (slide 21)
mx25u3235f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7438/MX25U3235F,%201.8V,%2032Mb,%20v1.6.pdf
(slide 31)
mx25u4035: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7295/MX25U4035,%201.8V,%204Mb,%20v1.4.pdf
(slide 19)
mx25u8035: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7295/MX25U4035,%201.8V,%204Mb,%20v1.4.pdf
(slide 19)
mx25u6435f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7411/MX25U6435F,%201.8V,%2064Mb,%20v1.5.pdf
(slide 31)
mx25l12805d: 8bit
https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf
(slide 13)
mx25l12855e: 8bit
https://datasheetspdf.com/pdf-file/653682/MacronixInternational/MX25L12855E/1
(slide 17)
mx25r1635f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7595/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf
(slide 30)
mx25r3235f: 8bit
https://www.digikey.de/en/datasheets/macronix/macronixmx25r3235f20wide20range2032mb20v16
(slide 31)
mx25u12835f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7656/MX25U12835F,%201.8V,%20128Mb,%20v1.9.pdf
(slide 31)
mx25l25635e: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7331/MX25L25635E,%203V,%20256Mb,%20v1.3.pdf
(slide 18)
mx25u25635f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7410/MX25U25635F,%201.8V,%20256Mb,%20v1.5.pdf
(slide 33)
mx25u51245g: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7874/MX25U51245G,%201.8V,%20512Mb,%20v1.3.pdf
(slide 27)
mx25v8035f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7432/MX25V8035F,%202.5V,%208Mb,%20v1.4.pdf
(slide 29)
mx25l25655e: 8bit
https://datasheetspdf.com/pdf-file/843325/MACRONIX/MX25L25655E/1 (slide 18)
mx66l51235f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7401/MX66L51235F,%203V,%20512Mb,%20v1.1.pdf
(slide 34)
mx66u51235f: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7674/MX66U51235F,%201.8V,%20512Mb,%20v1.1.pdf
(slide 34)
mx66l1g45g: 8bit
https://www.macronix.com/Lists/Datasheet/Attachments/7857/MX66L1G45G,%203V,%201Gb,%20v1.5.pdf
(slide 37)
mx66u2g45g:
https://www.macronix.com/Lists/Datasheet/Attachments/7884/MX66U2G45G,%201.8V,%202Gb,%20v1.1.pdf
(slide 27)
On 12/29/21 15:08, Tudor.Ambarus@microchip.com wrote:
> On 12/27/21 11:16 AM, vincent@systemli.org wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> From: Nick Hainke <vincent@systemli.org>
>>
>> Macronix flash chips seem to consist of only one status register.
>> These chips will not work with the "16-bit Write Status (01h) Command".
>> Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
> Hi, Vincent!
>
> Have you checked all the existing macronix flash_info entries and determined
> that neither of them support SNOR_F_HAS_16BIT_SR? Per manufacturer settings
> are a bit sensible because we can't predict what manufacturers are doing with
> new flash designs and whether they'll respect their "legacy" flash settings or
> not. Thus I'm a bit reluctant in adding per manufacturer settings.
>
> Cheers,
> ta
>
>> Tested with MX25L6405D.
>>
>> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
>> lock()/unlock()")
>>
>> Signed-off-by: David Bauer <mail@david-bauer.net>
>> Signed-off-by: Nick Hainke <vincent@systemli.org>
>> ---
>> drivers/mtd/spi-nor/macronix.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
>> index f07b59a4120a..d530ab0b3b13 100644
>> --- a/drivers/mtd/spi-nor/macronix.c
>> +++ b/drivers/mtd/spi-nor/macronix.c
>> @@ -94,6 +94,7 @@ static void macronix_default_init(struct spi_nor *nor)
>> {
>> nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
>> nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode;
>> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
>> }
>>
>> static const struct spi_nor_fixups macronix_fixups = {
>> --
>> 2.34.1
>>
>>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2021-12-31 9:10 ` Nick
@ 2021-12-31 9:50 ` Nick
2022-01-19 15:49 ` Michael Walle
1 sibling, 0 replies; 8+ messages in thread
From: Nick @ 2021-12-31 9:50 UTC (permalink / raw)
To: linux-mtd
Meanwhile I also tested on:
- mx25l12805d (Litebeam AC Gen2)
On 12/31/21 10:10, Nick wrote:
> I looked now through all datasheets I found and the sizes of the
> status register. However, I did not find any datasheet for the
> "mx66l1g55g".
> However, I am not sure if I maybe miss something to see if
> "SNOR_F_HAS_16BIT_SR" is supported. I only looked at the status
> register size.
>
> It is also now merged in OpenWrt, so maybe we wait some time and see
> if someone complains?
> https://github.com/openwrt/openwrt/commit/83b5fbddf28e943e8c90b4099a1e36d158f5995c
>
>
> Otherwise, I documented my findings:
> mx25l512e: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7398/MX25L512E,%203V,%20512Kb,%20v1.4.pdf
> (slide 13)
> mx25l2005a: 8bit
> https://www.macrogroup.ru/sites/default/files/uploads/mx25l2005_3v_2mb_v1.9.pdf
> (slide 12)
> mx25l4005a: 8bit
> https://pdf1.alldatasheet.com/datasheet-pdf/view/267913/MCNIX/MX25L4005A.html
> (slide 11)
> mx25l8005: 8bit
> https://pdf1.alldatasheet.com/datasheet-pdf/view/267915/MCNIX/MX25L8005.html
> (slide 11)
> mx25l1606e: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7465/MX25L1606E,%203V,%2016Mb,%20v1.9.pdf
> (slide 18)
> mx25l3205d: 8bit
> https://pdf1.alldatasheet.com/datasheet-pdf/view/267908/MCNIX/MX25L3205D.html
> (slide 19)
> mx25l3255e: 8bit
> https://www.application-datasheet.com/pdf/macronix/mx25l3255em2i-10g.pdf
> (slide 22)
> mx25l6405d: 8bit
> https://datasheet.octopart.com/MX25L6405DZNI-12G-Macronix-datasheet-8325093.pdf
> (slide 19)
> mx25u2033e: 8bit
> https://datasheetspdf.com/pdf-file/792587/MACRONIX/MX25U2033E/1 (slide
> 21)
> mx25u3235f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7438/MX25U3235F,%201.8V,%2032Mb,%20v1.6.pdf
> (slide 31)
> mx25u4035: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7295/MX25U4035,%201.8V,%204Mb,%20v1.4.pdf
> (slide 19)
> mx25u8035: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7295/MX25U4035,%201.8V,%204Mb,%20v1.4.pdf
> (slide 19)
> mx25u6435f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7411/MX25U6435F,%201.8V,%2064Mb,%20v1.5.pdf
> (slide 31)
> mx25l12805d: 8bit
> https://www.mxic.com.tw/Lists/Datasheet/Attachments/7321/MX25L12805D,%203V,%20128Mb,%20v1.2.pdf
> (slide 13)
> mx25l12855e: 8bit
> https://datasheetspdf.com/pdf-file/653682/MacronixInternational/MX25L12855E/1
> (slide 17)
> mx25r1635f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7595/MX25R1635F,%20Wide%20Range,%2016Mb,%20v1.6.pdf
> (slide 30)
> mx25r3235f: 8bit
> https://www.digikey.de/en/datasheets/macronix/macronixmx25r3235f20wide20range2032mb20v16
> (slide 31)
> mx25u12835f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7656/MX25U12835F,%201.8V,%20128Mb,%20v1.9.pdf
> (slide 31)
> mx25l25635e: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7331/MX25L25635E,%203V,%20256Mb,%20v1.3.pdf
> (slide 18)
> mx25u25635f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7410/MX25U25635F,%201.8V,%20256Mb,%20v1.5.pdf
> (slide 33)
> mx25u51245g: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7874/MX25U51245G,%201.8V,%20512Mb,%20v1.3.pdf
> (slide 27)
> mx25v8035f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7432/MX25V8035F,%202.5V,%208Mb,%20v1.4.pdf
> (slide 29)
> mx25l25655e: 8bit
> https://datasheetspdf.com/pdf-file/843325/MACRONIX/MX25L25655E/1
> (slide 18)
> mx66l51235f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7401/MX66L51235F,%203V,%20512Mb,%20v1.1.pdf
> (slide 34)
> mx66u51235f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7674/MX66U51235F,%201.8V,%20512Mb,%20v1.1.pdf
> (slide 34)
> mx66l1g45g: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7857/MX66L1G45G,%203V,%201Gb,%20v1.5.pdf
> (slide 37)
> mx66u2g45g:
> https://www.macronix.com/Lists/Datasheet/Attachments/7884/MX66U2G45G,%201.8V,%202Gb,%20v1.1.pdf
> (slide 27)
>
> On 12/29/21 15:08, Tudor.Ambarus@microchip.com wrote:
>> On 12/27/21 11:16 AM, vincent@systemli.org wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>>> know the content is safe
>>>
>>> From: Nick Hainke <vincent@systemli.org>
>>>
>>> Macronix flash chips seem to consist of only one status register.
>>> These chips will not work with the "16-bit Write Status (01h) Command".
>>> Disable SNOR_F_HAS_16BIT_SR for all Macronix chips.
>> Hi, Vincent!
>>
>> Have you checked all the existing macronix flash_info entries and
>> determined
>> that neither of them support SNOR_F_HAS_16BIT_SR? Per manufacturer
>> settings
>> are a bit sensible because we can't predict what manufacturers are
>> doing with
>> new flash designs and whether they'll respect their "legacy" flash
>> settings or
>> not. Thus I'm a bit reluctant in adding per manufacturer settings.
>>
>> Cheers,
>> ta
>>
>>> Tested with MX25L6405D.
>>>
>>> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
>>> lock()/unlock()")
>>>
>>> Signed-off-by: David Bauer <mail@david-bauer.net>
>>> Signed-off-by: Nick Hainke <vincent@systemli.org>
>>> ---
>>> drivers/mtd/spi-nor/macronix.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/mtd/spi-nor/macronix.c
>>> b/drivers/mtd/spi-nor/macronix.c
>>> index f07b59a4120a..d530ab0b3b13 100644
>>> --- a/drivers/mtd/spi-nor/macronix.c
>>> +++ b/drivers/mtd/spi-nor/macronix.c
>>> @@ -94,6 +94,7 @@ static void macronix_default_init(struct spi_nor
>>> *nor)
>>> {
>>> nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
>>> nor->params->set_4byte_addr_mode =
>>> spi_nor_set_4byte_addr_mode;
>>> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
>>> }
>>>
>>> static const struct spi_nor_fixups macronix_fixups = {
>>> --
>>> 2.34.1
>>>
>>>
>>> ______________________________________________________
>>> Linux MTD discussion mailing list
>>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2021-12-31 9:10 ` Nick
2021-12-31 9:50 ` Nick
@ 2022-01-19 15:49 ` Michael Walle
2022-01-19 20:36 ` David Bauer
1 sibling, 1 reply; 8+ messages in thread
From: Michael Walle @ 2022-01-19 15:49 UTC (permalink / raw)
To: Nick; +Cc: Tudor.Ambarus, linux-mtd, mail
Am 2021-12-31 10:10, schrieb Nick:
> I looked now through all datasheets I found and the sizes of the
> status register. However, I did not find any datasheet for the
> "mx66l1g55g".
> However, I am not sure if I maybe miss something to see if
> "SNOR_F_HAS_16BIT_SR" is supported. I only looked at the status
> register size.
How did you check that?
random example:
> mx66u51235f: 8bit
> https://www.macronix.com/Lists/Datasheet/Attachments/7674/MX66U51235F,%201.8V,%20512Mb,%20v1.1.pdf
> (slide 34)
Figure 23:
WRSR takes both status register and configuration register.
That being said. I'd prefer to have a sane default for that
flag - which is to _not_ set it by default. For now, we can
just remove the flag from spi_nor_init_default_params() and
move it into the manufacturer default init. Then we can
go through the flashes and remove the flag there.
This is mainly because it seems to be a legacy feature. To
quote the datasheet of the Winbond W25Q32FW [1]:
| The W25Q32FW is also backward compatible to Winbond’s previous
| generations of serial flash memories, in which the Status
| Register-1&2 can be written using a single “Write Status
| Register-1 (01h)” command.
-michael
[1]
https://www.winbond.com/resource-files/w25q32fw%20revj%2004242018%20sfdp.pdf
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2022-01-19 15:49 ` Michael Walle
@ 2022-01-19 20:36 ` David Bauer
2022-01-20 8:08 ` Michael Walle
0 siblings, 1 reply; 8+ messages in thread
From: David Bauer @ 2022-01-19 20:36 UTC (permalink / raw)
To: Michael Walle, Nick; +Cc: Tudor.Ambarus, linux-mtd
Hi Michael,
On 1/19/22 16:49, Michael Walle wrote:
> Am 2021-12-31 10:10, schrieb Nick:
>> I looked now through all datasheets I found and the sizes of the
>> status register. However, I did not find any datasheet for the
>> "mx66l1g55g".
>> However, I am not sure if I maybe miss something to see if
>> "SNOR_F_HAS_16BIT_SR" is supported. I only looked at the status
>> register size.
>
> How did you check that?
>
> random example:
>> mx66u51235f: 8bit
>> https://www.macronix.com/Lists/Datasheet/Attachments/7674/MX66U51235F,%201.8V,%20512Mb,%20v1.1.pdf
>> (slide 34)
>
> Figure 23:
> WRSR takes both status register and configuration register.
>
> That being said. I'd prefer to have a sane default for that
> flag - which is to _not_ set it by default. For now, we can
> just remove the flag from spi_nor_init_default_params() and
> move it into the manufacturer default init. Then we can
> go through the flashes and remove the flag there.
I was working on a similar series in parallel - and i just want to
confirm this before i submit it. [0]
Your take would be to remove the flag from spi_nor_init_default_params
and place it in all vendor init-calls, right?
My current take would be to add a new flag which denotes flashes that
only have a single 8-bit SR, no second SR / CR.
This would require minimal changes, although after your E-Mail i would
rename it so it becomes clear it is rather for denoting flashes which
only support writing a single 8-bit register with a WRSR command.
What do you think?
[0] https://github.com/blocktrron/linux/commits/spi-not-8sr-flag
Best
David
>
> This is mainly because it seems to be a legacy feature. To
> quote the datasheet of the Winbond W25Q32FW [1]:
>
> | The W25Q32FW is also backward compatible to Winbond’s previous
> | generations of serial flash memories, in which the Status
> | Register-1&2 can be written using a single “Write Status
> | Register-1 (01h)” command.
>
> -michael
>
> [1] https://www.winbond.com/resource-files/w25q32fw%20revj%2004242018%20sfdp.pdf
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix
2022-01-19 20:36 ` David Bauer
@ 2022-01-20 8:08 ` Michael Walle
0 siblings, 0 replies; 8+ messages in thread
From: Michael Walle @ 2022-01-20 8:08 UTC (permalink / raw)
To: David Bauer; +Cc: Nick, Tudor.Ambarus, linux-mtd
Hi David,
Am 2022-01-19 21:36, schrieb David Bauer:
> On 1/19/22 16:49, Michael Walle wrote:
>> That being said. I'd prefer to have a sane default for that
>> flag - which is to _not_ set it by default. For now, we can
>> just remove the flag from spi_nor_init_default_params() and
>> move it into the manufacturer default init. Then we can
>> go through the flashes and remove the flag there.
>
> I was working on a similar series in parallel - and i just want to
> confirm this before i submit it. [0]
>
> Your take would be to remove the flag from spi_nor_init_default_params
> and place it in all vendor init-calls, right?
correct.
> My current take would be to add a new flag which denotes flashes that
> only have a single 8-bit SR, no second SR / CR.
but that new flag has the same meaning as the current one, no? In fact
I see you are just clearing the 16bit flag if the 8bit one is set.
Therefore, you have to bits for just two states. We want to
use less flags and IMHO this isn't good for readability.
Also it doesn't fix the bad default. I doubt anyone adding
a new vendor/flash is aware that the default is a WRSR with
16bit SR. Eg. I just had a quick look at gigadevice and it
doesn't seem to support this neither. Now depending on the
SFDP content the flag is overwritten anyways. But still.
I'd really like to get rid of this and just identify the
flashes that doesn't have an opcode to write the second
status register/configuration register.
-michael
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-01-20 8:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-12-27 9:16 [PATCH 1/2] mtd: spi-nor: locking support for MX25L6405D vincent
2021-12-27 9:16 ` [PATCH 2/2] mtd: spi-nor: disable 16-bit-sr for macronix vincent
2021-12-29 14:08 ` Tudor.Ambarus
2021-12-31 9:10 ` Nick
2021-12-31 9:50 ` Nick
2022-01-19 15:49 ` Michael Walle
2022-01-19 20:36 ` David Bauer
2022-01-20 8:08 ` Michael Walle
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