RE: NAND Configuration

[Thomas Gleixner <tglx@linutronix.de>]

On Tue, 2002-08-06 at 12:25, Steve Tsai wrote:
> I use GPIO to control NCE, ALE and CLE. RE and WE are connected to CS of
> ROM bank 1 and ROM bank 2.
> The test program are work fine to do read/write and it seems work fine
> also when I did not use CONFIG_JFFS2_FS_NAND. Thanks.
> 
> ================================================================
> Change in nand.c for our board.
> =================================================================
> 
> #undef readb
> #undef writeb
> 
> #define readb(a)  (*(volatile unsigned char *)(a))
It's really innovative to reinvent the wheel.
 
> /* Use function call for more delay in write cycle */
> void writeb(unsigned char v, unsigned int a)
> {
> 	*(volatile unsigned char *)(a) = v;
> }
For what do you need more delay ??? NAND is fast enough.
> 
> 
> 	/* Set address of NAND IO lines */
> 	/* 0x2000000 for ROM bank 1, 0x2200000 form ROM bank 2 */
> 	/* Above 0x4000000 is noncachable area
> */
> 	this->IO_ADDR_W = (dnp_fio_base | 0x4000000);
> 	this->IO_ADDR_R = ((dnp_fio_base+0x200000) | 0x4000000);
Is your read address really different to your write address ???
If yes, get a baseball bat and trim the hardware guy. :)
If no, you read and write from/to different address ranges.

> 	/* Set address of hardware control function */
> 	this->hwcontrol = dnp_hwcontrol;
> 	this->dev_ready = NULL;
> 	/* 15 us command delay time */
> 	this->chip_delay = 15;		
Could you try to set chipdelay to a longer value ? 	
-- 
Thomas 
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