Re: nand flash driver

[Russ Dill <Russ.Dill@asu.edu>]

On Thu, 2003-07-10 at 08:12, jasmine@regolith.co.uk wrote:
> On Thu, 10 Jul 2003, David Woodhouse wrote:
> 
> > Hmmm. When sending multiple bytes of address, isn't ALE supposed to
> > remain high for the entire duration, without going low again between
> > cycles? How do you achieve this if it's on the address bus?
> 
> By waiting to see if the next write is to the same address-  it's not hard 
> to do that sort of thing in an FPGA or SoC.  Since the only line involved 
> is the ALE to the NAND, there's no downside in hanging on a little longer
> before dropping it.

yup, and a CPLD only costs about $1 (32 io, 32 mc) or $2.65 for a
72io/72 mc. Makes this sort of thing pretty trivial, although for 2 or 3
signals, discrete logic will do just fine.

-- 
Russ Dill <Russ.Dill@asu.edu>