Re: Handling multiple NAND chips

[David Woodhouse <dwmw2@infradead.org>]

On Fri, 2003-07-25 at 11:12, J.D. Bakker wrote:
> Hi all,
> 
> I have an expansion board for the LART (an embedded computer based on 
> the DEC/Intel StrongARM) with eight NAND flash devices on it. As 
> suggested by the Toshiba datasheet, they share data, CLE, ALE, nWE 
> and nRE and RDY. Each chip has its own nCE line.
> 

If they each had their own data/CLE/ALE etc you'd use mtdconcat. As it
is, you want the code I've half-written to handle multiple chips in one
MTD device.

> I would like to use all eight chips with mtdconcat and YAFFS. Given 
> the above, how should I hook the eight NANDs up to the mtd layer ? 
> I've gone through CVS, but haven't found any hints in The Source.

Look at the changes I've made recently. They're the first half of what's
needed.

> By the way, is mtd multi-threaded whne using multiple devices ? 
> Should I worry about overlapping address/data phases to separate NAND 
> chips ?

It will be, yes -- but at the moment it doesn't actually _use_ multiple
devices; it only manages the probe. We need to fix the read/write/erase
methods to handle multiple chips; selecting the right chip, etc.

> [who inflicted the LART_ENDIAN_BYTE ordering on mtd]

:)

-- 
dwmw2