Re: AG-AND requested changes

[Thomas Gleixner <tglx@linutronix.de>]

Hi David,

On Wed, 2005-01-12 at 22:27, David A. Marlin wrote:
> Thomas:
> Note: I have two additional comments regarding the proposed solutions.
> 
> 1) The code changes use an array of bad block table addresses (one for 
> each chip) in case the erase spans multiple chips and BBT per chip is 
> used.  Based on my testing I don't think this ever occurs (at least for 
> this device).  If we could assume that it would never occur, the code 
> for this could be simplified (no array or loops required).

Let it this way, so all possible combinations are covered. Please do not
make it dependend on NAND_IS_AND, invent a new option like
BBT_AUTO_REFRESH or what ever nice symbol you imagine.

So in case other chips suffer from the same problem we have the solution
handy without touching the code. The trend is going to those multibit
cells so I expect this to be neccecary for other devices too.

> 2) The command for 'device recovery' is a two cycle command, but the 
> first command byte is 0x00 (same as for READ0).  Since the process 
> requires that we can distinguish between a recovery and a read 
> operation, I added a high order bit to the initial command (0x100) to 
> make it unique and masked it off when actually sending the command. 
> Please let me know if you have a more elegant (or acceptable) solution.

Looks sane. You call this from the board driver I guess ?

tglx