Re: [PATCH] AT91RM9200 NAND support

Thomas Gleixner
2006-06-20T11:11:37Z

Savin,

On Tue, 2006-06-20 at 12:49 +0200, Savin Zlobec wrote:

Patch is correct, applied. Thanks

> And managed to erase the nand flash and mount JFFS2 on it, but writting
> still
> didn't work - got errors like :
>
> Data CRC d507eb40 != calculated CRC 2e617dde for node at 00e4f700
>
> The I put a call to nand_wait_ready at the top of nand_command function and
> as far as I could test everything worked (exept that the flash is still
> recognized as Toshiba (0x98) not Samsung (0xec)).

Well, we read the manufacturer ID. When we get 98H, how should we know
that this is a Samsung part ? And I doubt that this is a quad bit flip.

> It looks (to me) that there are still some parts of the code that should
> wait for nand to get ready before sending commands.

The only point where this really matters is, when we read data from
those chips. They have a horrible feature, which automatically loads the
next page into the internal buffer. There are only two places where we
actually read from the device. On has the check at the correct place
already, the other fixed you up.

Can you please remove the nand_wait_ready() call in nand_command() and
test the following patch ? It disables the ready busy pin and uses the
chip_delay. Please check, whether the 20us are correct. You can safely
set it to 50 without breaking stuff.

tglx

Index: mtd/drivers/mtd/nand/at91_nand.c
===================================================================
--- mtd.orig/drivers/mtd/nand/at91_nand.c
+++ mtd/drivers/mtd/nand/at91_nand.c
@@ -141,7 +141,6 @@ static int __init at91_nand_probe(struct
nand_chip->IO_ADDR_R = host->io_base;
nand_chip->IO_ADDR_W = host->io_base;
nand_chip->cmd_ctrl = at91_nand_cmd;
- nand_chip->dev_ready = at91_nand_device_ready;
nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
nand_chip->chip_delay = 20; /* 20us command delay time */