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	for linux-mtd@lists.infradead.org; Tue, 20 Jun 2006 13:43:42 +0100
Subject: Re: [PATCH] AT91RM9200 NAND support
From: Thomas Gleixner <tglx@linutronix.de>
To: Savin Zlobec <savin@epico.si>
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Date: Tue, 20 Jun 2006 14:44:40 +0200
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Savin,

On Tue, 2006-06-20 at 14:28 +0200, Savin Zlobec wrote:
> Chip not ready in nand_command():
> Last caller: c012aa04 (nand_base.c:389)
> Last command: 0x70
> Current caller: c012c0e8 (nand_base.c:1720)
> Current command: 0x60
> 
> 384     static int nand_check_wp(struct mtd_info *mtd)
> 385     {
> 386             struct nand_chip *chip = mtd->priv;
> 387             /* Check the WP bit */
> 388             chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
> 389             return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
> 390     }
>
> 1715    static void single_erase_cmd(struct mtd_info *mtd, int page)
> 1716    {
> 1717            struct nand_chip *chip = mtd->priv;
> 1718            /* Send commands to erase a block */
> 1719            chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
> 1720            chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
> 1721    }

The status command does not influence ready/busy. The one before that
nand_check_wp() call, is a chip reset command, but we wait for the chip
to become ready again.

Please give me the exact part number, so I can lookup the data sheet.

	tglx