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Subject: Re: [PATCH] PNX8550 NAND flash driver
From: Thomas Gleixner <tglx@linutronix.de>
To: Jurgen <jurgen.parmentier@telenet.be>
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Date: Wed, 26 Jul 2006 09:02:53 +0200
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Cc: Todd Poynor <tpoynor@mvista.com>,
	"Vladimir A. Barinov" <vbarinov@ru.mvista.com>,
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On Tue, 2006-07-25 at 20:34 +0200, Jurgen wrote:
> Root cause of the problem lies within the early implementation of the 
> low-level NAND commands. There was a severe risk that the PCI accesses 
> were stalled because of a Read Status command for the NAND Flash. This 
> Read Status was launched immediately after program/erase command. The 
> hardware itself will wait for the Ready/Busy to be high and only then 
> launch the Read Status command. This behavior caused timeout on the 
> internal bus because PCI was unable to use the pins during this wait.

The hardware design is broken. Status Read can be requested while R/B is
low. See NAND datasheets.

> If this problem was coinciding with an ISR that tried to perform a PCI 
> status register, then this PCI access could possibly timeout (because 
> the PCI pins were already claimed for the XIO access that is depending 
> on the RBY signal).
> 
> Since the problem only showed during the PCI device ISR, the 
> quick'n'dirty hack was to disable interrupts during XIO accesses.
> 
> A better fix that should be available somewhere, is to improve the 
> low-level NAND driver that will first check the status of the Ready/Busy 
> line and only THEN launch the Read NAND Status command...

Thats not an improvement. Thats a hack for your broken hardware. You'd
burden the R/B check on every sane hardware out there.

You can add the R/B check to the chip->cmd_ctrl() function of your board
driver.

	tglx